Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T25,T22,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T25,T22,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T25,T22,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T25
1	0	Covered	T1,T5,T6
1	1	Covered	T25,T22,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T25,T22,T41
0	1	Not Covered
1	0	Covered	T53

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T25,T22,T41
0	1	Covered	T25,T22,T41
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T25,T22,T41
1	-	Covered	T25,T22,T41

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T25,T22,T41
DetectSt	168	Covered	T25,T22,T41
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T25,T22,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T25,T22,T41
DebounceSt->IdleSt	163	Covered	T108,T193
DetectSt->IdleSt	186	Covered	T53
DetectSt->StableSt	191	Covered	T25,T22,T41
IdleSt->DebounceSt	148	Covered	T25,T22,T41
StableSt->IdleSt	206	Covered	T25,T22,T41

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T25,T22,T41
0	1	Covered	T25,T22,T41
0	0	Excluded	T1,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T25,T22,T41
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T25,T22,T41
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T108
DebounceSt	-	0	1	1	-	-	-	Covered	T25,T22,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T193
DebounceSt	-	0	0	-	-	-	-	Covered	T25,T22,T41
DetectSt	-	-	-	-	1	-	-	Covered	T53
DetectSt	-	-	-	-	0	1	-	Covered	T25,T22,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T25,T22,T41
StableSt	-	-	-	-	-	-	0	Covered	T25,T22,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7903577	102	0	0
CntIncr_A	7903577	92997	0	0
CntNoWrap_A	7903577	7250985	0	0
DetectStDropOut_A	7903577	0	0	0
DetectedOut_A	7903577	91741	0	0
DetectedPulseOut_A	7903577	49	0	0
DisabledIdleSt_A	7903577	6639361	0	0
DisabledNoDetection_A	7903577	6641590	0	0
EnterDebounceSt_A	7903577	52	0	0
EnterDetectSt_A	7903577	50	0	0
EnterStableSt_A	7903577	49	0	0
PulseIsPulse_A	7903577	49	0	0
StayInStableSt	7903577	91668	0	0
gen_high_level_sva.HighLevelEvent_A	7903577	7253370	0	0
gen_not_sticky_sva.StableStDropOut_A	7903577	25	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7903577	102
T22	166215	2
T25	13294	2
T39	8763	0
T41	0	10
T42	15471	0
T45	679	0
T61	3451	0
T108	0	1
T113	0	2
T123	0	4
T140	0	2
T160	430	0
T161	616	0
T162	521	0
T163	425	0
T168	0	2
T171	0	4
T194	0	4

CntIncr_A

Name	Attempts	Real Successes
Total	7903577	92997
T22	166215	26
T25	13294	17
T39	8763	0
T41	0	341
T42	15471	0
T45	679	0
T61	3451	0
T108	0	29
T113	0	31
T123	0	188
T140	0	16
T160	430	0
T161	616	0
T162	521	0
T163	425	0
T168	0	44168
T171	0	128
T194	0	24

CntNoWrap_A

Name	Attempts	Real Successes
Total	7903577	7250985
T1	25831	25363
T2	1099	698
T5	4417	649
T6	651	250
T13	5067	4666
T14	427	26
T15	508	107
T16	502	101
T17	5367	4966
T18	502	101

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7903577	91741
T22	166215	43
T25	13294	2
T39	8763	0
T41	0	303
T42	15471	0
T45	679	0
T61	3451	0
T113	0	43
T123	0	84
T140	0	41
T160	430	0
T161	616	0
T162	521	0
T163	425	0
T168	0	55526
T171	0	276
T173	0	79
T194	0	135

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7903577	49
T22	166215	1
T25	13294	1
T39	8763	0
T41	0	5
T42	15471	0
T45	679	0
T61	3451	0
T113	0	1
T123	0	2
T140	0	1
T160	430	0
T161	616	0
T162	521	0
T163	425	0
T168	0	1
T171	0	2
T173	0	2
T194	0	2

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7903577	6639361
T1	25831	25363
T2	1099	698
T5	4417	649
T6	651	250
T13	5067	4666
T14	427	26
T15	508	107
T16	502	101
T17	5367	4966
T18	502	101

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7903577	6641590
T1	25831	25373
T2	1099	699
T5	4417	660
T6	651	251
T13	5067	4667
T14	427	27
T15	508	108
T16	502	102
T17	5367	4967
T18	502	102

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7903577	52
T22	166215	1
T25	13294	1
T39	8763	0
T41	0	5
T42	15471	0
T45	679	0
T61	3451	0
T108	0	1
T113	0	1
T123	0	2
T140	0	1
T160	430	0
T161	616	0
T162	521	0
T163	425	0
T168	0	1
T171	0	2
T194	0	2

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7903577	50
T22	166215	1
T25	13294	1
T39	8763	0
T41	0	5
T42	15471	0
T45	679	0
T61	3451	0
T113	0	1
T123	0	2
T140	0	1
T160	430	0
T161	616	0
T162	521	0
T163	425	0
T168	0	1
T171	0	2
T173	0	2
T194	0	2

EnterStableSt_A

Name	Attempts	Real Successes
Total	7903577	49
T22	166215	1
T25	13294	1
T39	8763	0
T41	0	5
T42	15471	0
T45	679	0
T61	3451	0
T113	0	1
T123	0	2
T140	0	1
T160	430	0
T161	616	0
T162	521	0
T163	425	0
T168	0	1
T171	0	2
T173	0	2
T194	0	2

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7903577	49
T22	166215	1
T25	13294	1
T39	8763	0
T41	0	5
T42	15471	0
T45	679	0
T61	3451	0
T113	0	1
T123	0	2
T140	0	1
T160	430	0
T161	616	0
T162	521	0
T163	425	0
T168	0	1
T171	0	2
T173	0	2
T194	0	2

StayInStableSt

Name	Attempts	Real Successes
Total	7903577	91668
T22	166215	42
T25	13294	1
T39	8763	0
T41	0	296
T42	15471	0
T45	679	0
T61	3451	0
T113	0	41
T123	0	81
T140	0	40
T160	430	0
T161	616	0
T162	521	0
T163	425	0
T168	0	55524
T171	0	273
T173	0	76
T194	0	132

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	7903577	7253370
T1	25831	25373
T2	1099	699
T5	4417	660
T6	651	251
T13	5067	4667
T14	427	27
T15	508	108
T16	502	102
T17	5367	4967
T18	502	102

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7903577	25
T22	166215	1
T25	13294	1
T39	8763	0
T41	0	3
T42	15471	0
T45	679	0
T61	3451	0
T123	0	1
T140	0	1
T160	430	0
T161	616	0
T162	521	0
T163	425	0
T171	0	1
T173	0	1
T194	0	1
T195	0	1
T196	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T9,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T7,T9,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T9,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T9
1	0	Covered	T1,T5,T14
1	1	Covered	T7,T9,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T40
0	1	Covered	T41,T173,T197
1	0	Covered	T53

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T40
0	1	Covered	T9,T25,T111
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T9,T40
1	-	Covered	T9,T25,T111

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T9,T40
DetectSt	168	Covered	T7,T9,T40
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T7,T9,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T9,T40
DebounceSt->IdleSt	163	Covered	T22,T198,T108
DetectSt->IdleSt	186	Covered	T41,T173,T53
DetectSt->StableSt	191	Covered	T7,T9,T40
IdleSt->DebounceSt	148	Covered	T7,T9,T40
StableSt->IdleSt	206	Covered	T9,T25,T39

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T9,T40
0	1	Covered	T7,T9,T40
0	0	Excluded	T1,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T40
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T9,T40
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T108
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T9,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T22,T198,T194
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T9,T40
DetectSt	-	-	-	-	1	-	-	Covered	T41,T173,T53
DetectSt	-	-	-	-	0	1	-	Covered	T7,T9,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T25,T111
StableSt	-	-	-	-	-	-	0	Covered	T7,T9,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7903577	157	0	0
CntIncr_A	7903577	160256	0	0
CntNoWrap_A	7903577	7250930	0	0
DetectStDropOut_A	7903577	4	0	0
DetectedOut_A	7903577	38250	0	0
DetectedPulseOut_A	7903577	70	0	0
DisabledIdleSt_A	7903577	6694161	0	0
DisabledNoDetection_A	7903577	6696381	0	0
EnterDebounceSt_A	7903577	82	0	0
EnterDetectSt_A	7903577	75	0	0
EnterStableSt_A	7903577	70	0	0
PulseIsPulse_A	7903577	70	0	0
StayInStableSt	7903577	38148	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7903577	2915	0	0
gen_low_level_sva.LowLevelEvent_A	7903577	7253370	0	0
gen_not_sticky_sva.StableStDropOut_A	7903577	38	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7903577	157
T7	850	2
T8	602	0
T9	729	4
T22	0	3
T25	0	2
T26	532	0
T38	0	2
T39	0	2
T40	0	2
T41	0	6
T55	615	0
T56	740	0
T57	639	0
T58	556	0
T60	1418	0
T71	502	0
T111	0	2
T168	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	7903577	160256
T7	850	36
T8	602	0
T9	729	120
T22	0	52
T25	0	79
T26	532	0
T38	0	54
T39	0	62
T40	0	73
T41	0	141
T55	615	0
T56	740	0
T57	639	0
T58	556	0
T60	1418	0
T71	502	0
T111	0	49
T168	0	44168

CntNoWrap_A

Name	Attempts	Real Successes
Total	7903577	7250930
T1	25831	25363
T2	1099	698
T5	4417	649
T6	651	250
T13	5067	4666
T14	427	26
T15	508	107
T16	502	101
T17	5367	4966
T18	502	101

DetectStDropOut_A

Name	Attempts	Real Successes
Total	7903577	4
T41	263390	1
T139	11128	0
T141	32603	0
T173	0	1
T183	0	1
T188	422	0
T189	29382	0
T190	22091	0
T191	505	0
T197	0	1
T199	40079	0
T200	5322	0
T201	503	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7903577	38250
T7	850	256
T8	602	0
T9	729	85
T22	0	81
T25	0	58
T26	532	0
T38	0	268
T39	0	52
T40	0	272
T41	0	15
T55	615	0
T56	740	0
T57	639	0
T58	556	0
T60	1418	0
T71	502	0
T111	0	1
T168	0	43

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7903577	70
T7	850	1
T8	602	0
T9	729	2
T22	0	1
T25	0	1
T26	532	0
T38	0	1
T39	0	1
T40	0	1
T41	0	2
T55	615	0
T56	740	0
T57	639	0
T58	556	0
T60	1418	0
T71	502	0
T111	0	1
T168	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7903577	6694161
T1	25831	25363
T2	1099	698
T5	4417	649
T6	651	250
T13	5067	4666
T14	427	26
T15	508	107
T16	502	101
T17	5367	4966
T18	502	101

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7903577	6696381
T1	25831	25373
T2	1099	699
T5	4417	660
T6	651	251
T13	5067	4667
T14	427	27
T15	508	108
T16	502	102
T17	5367	4967
T18	502	102

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7903577	82
T7	850	1
T8	602	0
T9	729	2
T22	0	2
T25	0	1
T26	532	0
T38	0	1
T39	0	1
T40	0	1
T41	0	3
T55	615	0
T56	740	0
T57	639	0
T58	556	0
T60	1418	0
T71	502	0
T111	0	1
T168	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7903577	75
T7	850	1
T8	602	0
T9	729	2
T22	0	1
T25	0	1
T26	532	0
T38	0	1
T39	0	1
T40	0	1
T41	0	3
T55	615	0
T56	740	0
T57	639	0
T58	556	0
T60	1418	0
T71	502	0
T111	0	1
T168	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	7903577	70
T7	850	1
T8	602	0
T9	729	2
T22	0	1
T25	0	1
T26	532	0
T38	0	1
T39	0	1
T40	0	1
T41	0	2
T55	615	0
T56	740	0
T57	639	0
T58	556	0
T60	1418	0
T71	502	0
T111	0	1
T168	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7903577	70
T7	850	1
T8	602	0
T9	729	2
T22	0	1
T25	0	1
T26	532	0
T38	0	1
T39	0	1
T40	0	1
T41	0	2
T55	615	0
T56	740	0
T57	639	0
T58	556	0
T60	1418	0
T71	502	0
T111	0	1
T168	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7903577	38148
T7	850	254
T8	602	0
T9	729	82
T22	0	79
T25	0	57
T26	532	0
T38	0	266
T39	0	50
T40	0	270
T41	0	13
T55	615	0
T56	740	0
T57	639	0
T58	556	0
T60	1418	0
T71	502	0
T81	0	56
T168	0	42

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	7903577	2915
T2	1099	0
T5	4417	15
T6	651	0
T7	0	1
T13	5067	0
T14	427	2
T15	508	6
T16	502	4
T17	5367	0
T18	502	8
T48	504	7
T55	0	4
T70	0	5
T73	0	6

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	7903577	7253370
T1	25831	25373
T2	1099	699
T5	4417	660
T6	651	251
T13	5067	4667
T14	427	27
T15	508	108
T16	502	102
T17	5367	4967
T18	502	102

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7903577	38
T9	729	1
T10	124227	0
T11	12474	0
T12	22676	0
T23	493	0
T25	0	1
T30	20486	0
T41	0	2
T58	556	0
T66	409	0
T67	422	0
T68	526	0
T111	0	1
T144	0	1
T168	0	1
T171	0	2
T173	0	1
T194	0	1
T202	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T3,T7,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T3,T7,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T3,T7,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T5,T6
1	1	Covered	T3,T7,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T8
0	1	Covered	T3
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T8
0	1	Covered	T9,T10,T25
1	0	Covered	T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T8
1	-	Covered	T9,T10,T25

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T8
DetectSt	168	Covered	T3,T7,T8
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T3,T7,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T8
DebounceSt->IdleSt	163	Covered	T81,T108,T203
DetectSt->IdleSt	186	Covered	T3
DetectSt->StableSt	191	Covered	T3,T7,T8
IdleSt->DebounceSt	148	Covered	T3,T7,T8
StableSt->IdleSt	206	Covered	T9,T10,T25

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T7,T8
0	1	Covered	T3,T7,T8
0	0	Excluded	T1,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T108
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T81,T203,T196
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T8
DetectSt	-	-	-	-	1	-	-	Covered	T3
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T8
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T10,T25
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7903577	109	0	0
CntIncr_A	7903577	180573	0	0
CntNoWrap_A	7903577	7250978	0	0
DetectStDropOut_A	7903577	1	0	0
DetectedOut_A	7903577	355074	0	0
DetectedPulseOut_A	7903577	50	0	0
DisabledIdleSt_A	7903577	6434413	0	0
DisabledNoDetection_A	7903577	6436640	0	0
EnterDebounceSt_A	7903577	58	0	0
EnterDetectSt_A	7903577	51	0	0
EnterStableSt_A	7903577	50	0	0
PulseIsPulse_A	7903577	50	0	0
StayInStableSt	7903577	354996	0	0
gen_high_level_sva.HighLevelEvent_A	7903577	7253370	0	0
gen_not_sticky_sva.StableStDropOut_A	7903577	21	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7903577	109
T3	596	4
T4	1937	0
T7	850	2
T8	0	2
T9	0	2
T10	0	2
T25	0	2
T38	0	2
T41	0	2
T55	615	0
T56	740	0
T59	1557	0
T70	502	0
T71	502	0
T72	402	0
T73	440	0
T81	0	1
T168	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	7903577	180573
T3	596	46
T4	1937	0
T7	850	36
T8	0	62
T9	0	60
T10	0	27196
T25	0	79
T38	0	54
T41	0	59
T55	615	0
T56	740	0
T59	1557	0
T70	502	0
T71	502	0
T72	402	0
T73	440	0
T81	0	16
T168	0	44168

CntNoWrap_A

Name	Attempts	Real Successes
Total	7903577	7250978
T1	25831	25363
T2	1099	698
T5	4417	649
T6	651	250
T13	5067	4666
T14	427	26
T15	508	107
T16	502	101
T17	5367	4966
T18	502	101

DetectStDropOut_A

Name	Attempts	Real Successes
Total	7903577	1
T3	596	1
T4	1937	0
T7	850	0
T55	615	0
T56	740	0
T59	1557	0
T70	502	0
T71	502	0
T72	402	0
T73	440	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7903577	355074
T3	596	76
T4	1937	0
T7	850	56
T8	0	131
T9	0	43
T10	0	54698
T25	0	58
T38	0	18
T41	0	1
T55	615	0
T56	740	0
T59	1557	0
T70	502	0
T71	502	0
T72	402	0
T73	440	0
T168	0	53460
T170	0	46

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7903577	50
T3	596	1
T4	1937	0
T7	850	1
T8	0	1
T9	0	1
T10	0	1
T25	0	1
T38	0	1
T41	0	1
T55	615	0
T56	740	0
T59	1557	0
T70	502	0
T71	502	0
T72	402	0
T73	440	0
T168	0	1
T170	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7903577	6434413
T1	25831	25363
T2	1099	698
T5	4417	649
T6	651	250
T13	5067	4666
T14	427	26
T15	508	107
T16	502	101
T17	5367	4966
T18	502	101

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7903577	6436640
T1	25831	25373
T2	1099	699
T5	4417	660
T6	651	251
T13	5067	4667
T14	427	27
T15	508	108
T16	502	102
T17	5367	4967
T18	502	102

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7903577	58
T3	596	2
T4	1937	0
T7	850	1
T8	0	1
T9	0	1
T10	0	1
T25	0	1
T38	0	1
T41	0	1
T55	615	0
T56	740	0
T59	1557	0
T70	502	0
T71	502	0
T72	402	0
T73	440	0
T81	0	1
T168	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7903577	51
T3	596	2
T4	1937	0
T7	850	1
T8	0	1
T9	0	1
T10	0	1
T25	0	1
T38	0	1
T41	0	1
T55	615	0
T56	740	0
T59	1557	0
T70	502	0
T71	502	0
T72	402	0
T73	440	0
T168	0	1
T170	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	7903577	50
T3	596	1
T4	1937	0
T7	850	1
T8	0	1
T9	0	1
T10	0	1
T25	0	1
T38	0	1
T41	0	1
T55	615	0
T56	740	0
T59	1557	0
T70	502	0
T71	502	0
T72	402	0
T73	440	0
T168	0	1
T170	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7903577	50
T3	596	1
T4	1937	0
T7	850	1
T8	0	1
T9	0	1
T10	0	1
T25	0	1
T38	0	1
T41	0	1
T55	615	0
T56	740	0
T59	1557	0
T70	502	0
T71	502	0
T72	402	0
T73	440	0
T168	0	1
T170	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7903577	354996
T3	596	74
T4	1937	0
T7	850	54
T8	0	129
T9	0	42
T10	0	54697
T25	0	57
T38	0	17
T55	615	0
T56	740	0
T59	1557	0
T70	502	0
T71	502	0
T72	402	0
T73	440	0
T168	0	53459
T170	0	44
T204	0	132

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	7903577	7253370
T1	25831	25373
T2	1099	699
T5	4417	660
T6	651	251
T13	5067	4667
T14	427	27
T15	508	108
T16	502	102
T17	5367	4967
T18	502	102

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7903577	21
T9	729	1
T10	124227	1
T11	12474	0
T12	22676	0
T23	493	0
T25	0	1
T30	20486	0
T38	0	1
T41	0	1
T58	556	0
T66	409	0
T67	422	0
T68	526	0
T144	0	2
T168	0	1
T173	0	1
T196	0	1
T205	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T3,T25,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T3,T25,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T3,T25,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T25
1	0	Covered	T1,T5,T6
1	1	Covered	T3,T25,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T25,T39
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T25,T39
0	1	Covered	T3,T22,T41
1	0	Covered	T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T25,T39
1	-	Covered	T3,T22,T41

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T25,T39
DetectSt	168	Covered	T3,T25,T39
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T3,T25,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T25,T39
DebounceSt->IdleSt	163	Covered	T108,T206,T207
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T25,T39
IdleSt->DebounceSt	148	Covered	T3,T25,T39
StableSt->IdleSt	206	Covered	T3,T25,T39

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T25,T39
0	1	Covered	T3,T25,T39
0	0	Excluded	T1,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T3,T25,T39
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T25,T39
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T108
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T25,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T206,T207
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T25,T39
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T25,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T22,T41
StableSt	-	-	-	-	-	-	0	Covered	T3,T25,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7903577	75	0	0
CntIncr_A	7903577	21859	0	0
CntNoWrap_A	7903577	7251012	0	0
DetectStDropOut_A	7903577	0	0	0
DetectedOut_A	7903577	3339	0	0
DetectedPulseOut_A	7903577	36	0	0
DisabledIdleSt_A	7903577	7043963	0	0
DisabledNoDetection_A	7903577	7046191	0	0
EnterDebounceSt_A	7903577	39	0	0
EnterDetectSt_A	7903577	36	0	0
EnterStableSt_A	7903577	36	0	0
PulseIsPulse_A	7903577	36	0	0
StayInStableSt	7903577	3288	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7903577	6418	0	0
gen_low_level_sva.LowLevelEvent_A	7903577	7253370	0	0
gen_not_sticky_sva.StableStDropOut_A	7903577	20	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7903577	75
T3	596	2
T4	1937	0
T7	850	0
T22	0	2
T25	0	2
T38	0	2
T39	0	2
T41	0	4
T55	615	0
T56	740	0
T59	1557	0
T70	502	0
T71	502	0
T72	402	0
T73	440	0
T108	0	1
T171	0	4
T180	0	2
T208	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	7903577	21859
T3	596	23
T4	1937	0
T7	850	0
T22	0	66
T25	0	79
T38	0	54
T39	0	62
T41	0	65
T55	615	0
T56	740	0
T59	1557	0
T70	502	0
T71	502	0
T72	402	0
T73	440	0
T108	0	27
T171	0	128
T180	0	34
T208	0	54

CntNoWrap_A

Name	Attempts	Real Successes
Total	7903577	7251012
T1	25831	25363
T2	1099	698
T5	4417	649
T6	651	250
T13	5067	4666
T14	427	26
T15	508	107
T16	502	101
T17	5367	4966
T18	502	101

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7903577	3339
T3	596	40
T4	1937	0
T7	850	0
T22	0	169
T25	0	310
T38	0	46
T39	0	38
T41	0	88
T55	615	0
T56	740	0
T59	1557	0
T70	502	0
T71	502	0
T72	402	0
T73	440	0
T123	0	138
T171	0	189
T180	0	148
T208	0	95

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7903577	36
T3	596	1
T4	1937	0
T7	850	0
T22	0	1
T25	0	1
T38	0	1
T39	0	1
T41	0	2
T55	615	0
T56	740	0
T59	1557	0
T70	502	0
T71	502	0
T72	402	0
T73	440	0
T123	0	1
T171	0	2
T180	0	1
T208	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7903577	7043963
T1	25831	25363
T2	1099	698
T5	4417	649
T6	651	250
T13	5067	4666
T14	427	26
T15	508	107
T16	502	101
T17	5367	4966
T18	502	101

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7903577	7046191
T1	25831	25373
T2	1099	699
T5	4417	660
T6	651	251
T13	5067	4667
T14	427	27
T15	508	108
T16	502	102
T17	5367	4967
T18	502	102

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7903577	39
T3	596	1
T4	1937	0
T7	850	0
T22	0	1
T25	0	1
T38	0	1
T39	0	1
T41	0	2
T55	615	0
T56	740	0
T59	1557	0
T70	502	0
T71	502	0
T72	402	0
T73	440	0
T108	0	1
T171	0	2
T180	0	1
T208	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7903577	36
T3	596	1
T4	1937	0
T7	850	0
T22	0	1
T25	0	1
T38	0	1
T39	0	1
T41	0	2
T55	615	0
T56	740	0
T59	1557	0
T70	502	0
T71	502	0
T72	402	0
T73	440	0
T123	0	1
T171	0	2
T180	0	1
T208	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	7903577	36
T3	596	1
T4	1937	0
T7	850	0
T22	0	1
T25	0	1
T38	0	1
T39	0	1
T41	0	2
T55	615	0
T56	740	0
T59	1557	0
T70	502	0
T71	502	0
T72	402	0
T73	440	0
T123	0	1
T171	0	2
T180	0	1
T208	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7903577	36
T3	596	1
T4	1937	0
T7	850	0
T22	0	1
T25	0	1
T38	0	1
T39	0	1
T41	0	2
T55	615	0
T56	740	0
T59	1557	0
T70	502	0
T71	502	0
T72	402	0
T73	440	0
T123	0	1
T171	0	2
T180	0	1
T208	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7903577	3288
T3	596	39
T4	1937	0
T7	850	0
T22	0	168
T25	0	308
T38	0	44
T39	0	36
T41	0	85
T55	615	0
T56	740	0
T59	1557	0
T70	502	0
T71	502	0
T72	402	0
T73	440	0
T123	0	137
T171	0	186
T180	0	146
T208	0	94

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	7903577	6418
T1	25831	12
T2	1099	3
T5	4417	13
T6	651	2
T13	5067	10
T14	427	2
T15	508	4
T16	502	4
T17	5367	23
T18	502	6

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	7903577	7253370
T1	25831	25373
T2	1099	699
T5	4417	660
T6	651	251
T13	5067	4667
T14	427	27
T15	508	108
T16	502	102
T17	5367	4967
T18	502	102

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7903577	20
T3	596	1
T4	1937	0
T7	850	0
T22	0	1
T41	0	1
T55	615	0
T56	740	0
T59	1557	0
T70	502	0
T71	502	0
T72	402	0
T73	440	0
T123	0	1
T171	0	1
T181	0	3
T196	0	1
T203	0	1
T208	0	1
T209	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T9,T25,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T9,T25,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T9,T25,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T25,T22
1	0	Covered	T1,T5,T13
1	1	Covered	T9,T25,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T25,T22
0	1	Covered	T197,T210
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T25,T22
0	1	Covered	T9,T25,T22
1	0	Covered	T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T25,T22
1	-	Covered	T9,T25,T22

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T25,T22
DetectSt	168	Covered	T9,T25,T22
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T9,T25,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T25,T22
DebounceSt->IdleSt	163	Covered	T22,T169,T108
DetectSt->IdleSt	186	Covered	T197,T210
DetectSt->StableSt	191	Covered	T9,T25,T22
IdleSt->DebounceSt	148	Covered	T9,T25,T22
StableSt->IdleSt	206	Covered	T9,T25,T22

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T25,T22
0	1	Covered	T9,T25,T22
0	0	Excluded	T1,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T9,T25,T22
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T25,T22
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T108
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T25,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T22,T169,T211
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T25,T22
DetectSt	-	-	-	-	1	-	-	Covered	T197,T210
DetectSt	-	-	-	-	0	1	-	Covered	T9,T25,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T25,T22
StableSt	-	-	-	-	-	-	0	Covered	T9,T25,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7903577	127	0	0
CntIncr_A	7903577	144019	0	0
CntNoWrap_A	7903577	7250960	0	0
DetectStDropOut_A	7903577	2	0	0
DetectedOut_A	7903577	89432	0	0
DetectedPulseOut_A	7903577	58	0	0
DisabledIdleSt_A	7903577	6830369	0	0
DisabledNoDetection_A	7903577	6832601	0	0
EnterDebounceSt_A	7903577	67	0	0
EnterDetectSt_A	7903577	60	0	0
EnterStableSt_A	7903577	58	0	0
PulseIsPulse_A	7903577	58	0	0
StayInStableSt	7903577	89357	0	0
gen_high_level_sva.HighLevelEvent_A	7903577	7253370	0	0
gen_not_sticky_sva.StableStDropOut_A	7903577	40	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7903577	127
T9	729	2
T10	124227	0
T11	12474	0
T12	22676	0
T22	0	5
T23	493	0
T25	0	4
T30	20486	0
T41	0	2
T58	556	0
T66	409	0
T67	422	0
T68	526	0
T108	0	1
T169	0	3
T171	0	6
T192	0	2
T198	0	2
T208	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	7903577	144019
T9	729	60
T10	124227	0
T11	12474	0
T12	22676	0
T22	0	118
T23	493	0
T25	0	34
T30	20486	0
T41	0	59
T58	556	0
T66	409	0
T67	422	0
T68	526	0
T108	0	27
T169	0	158
T171	0	192
T192	0	37
T198	0	18
T208	0	54

CntNoWrap_A

Name	Attempts	Real Successes
Total	7903577	7250960
T1	25831	25363
T2	1099	698
T5	4417	649
T6	651	250
T13	5067	4666
T14	427	26
T15	508	107
T16	502	101
T17	5367	4966
T18	502	101

DetectStDropOut_A

Name	Attempts	Real Successes
Total	7903577	2
T127	16541	0
T165	1452	0
T197	823	1
T210	0	1
T212	507	0
T213	10571	0
T214	422	0
T215	57156	0
T216	8638	0
T217	27871	0
T218	5521	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7903577	89432
T9	729	158
T10	124227	0
T11	12474	0
T12	22676	0
T22	0	221
T23	493	0
T25	0	75
T30	20486	0
T41	0	104
T58	556	0
T66	409	0
T67	422	0
T68	526	0
T169	0	68
T171	0	248
T192	0	3
T198	0	59
T208	0	42
T219	0	29

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7903577	58
T9	729	1
T10	124227	0
T11	12474	0
T12	22676	0
T22	0	2
T23	493	0
T25	0	2
T30	20486	0
T41	0	1
T58	556	0
T66	409	0
T67	422	0
T68	526	0
T169	0	1
T171	0	3
T192	0	1
T198	0	1
T208	0	1
T219	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7903577	6830369
T1	25831	25363
T2	1099	698
T5	4417	649
T6	651	250
T13	5067	4666
T14	427	26
T15	508	107
T16	502	101
T17	5367	4966
T18	502	101

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7903577	6832601
T1	25831	25373
T2	1099	699
T5	4417	660
T6	651	251
T13	5067	4667
T14	427	27
T15	508	108
T16	502	102
T17	5367	4967
T18	502	102

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7903577	67
T9	729	1
T10	124227	0
T11	12474	0
T12	22676	0
T22	0	3
T23	493	0
T25	0	2
T30	20486	0
T41	0	1
T58	556	0
T66	409	0
T67	422	0
T68	526	0
T108	0	1
T169	0	2
T171	0	3
T192	0	1
T198	0	1
T208	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7903577	60
T9	729	1
T10	124227	0
T11	12474	0
T12	22676	0
T22	0	2
T23	493	0
T25	0	2
T30	20486	0
T41	0	1
T58	556	0
T66	409	0
T67	422	0
T68	526	0
T169	0	1
T171	0	3
T192	0	1
T198	0	1
T208	0	1
T219	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	7903577	58
T9	729	1
T10	124227	0
T11	12474	0
T12	22676	0
T22	0	2
T23	493	0
T25	0	2
T30	20486	0
T41	0	1
T58	556	0
T66	409	0
T67	422	0
T68	526	0
T169	0	1
T171	0	3
T192	0	1
T198	0	1
T208	0	1
T219	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7903577	58
T9	729	1
T10	124227	0
T11	12474	0
T12	22676	0
T22	0	2
T23	493	0
T25	0	2
T30	20486	0
T41	0	1
T58	556	0
T66	409	0
T67	422	0
T68	526	0
T169	0	1
T171	0	3
T192	0	1
T198	0	1
T208	0	1
T219	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7903577	89357
T9	729	157
T10	124227	0
T11	12474	0
T12	22676	0
T22	0	218
T23	493	0
T25	0	72
T30	20486	0
T41	0	102
T58	556	0
T66	409	0
T67	422	0
T68	526	0
T169	0	67
T171	0	244
T192	0	2
T198	0	57
T208	0	41
T219	0	28

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	7903577	7253370
T1	25831	25373
T2	1099	699
T5	4417	660
T6	651	251
T13	5067	4667
T14	427	27
T15	508	108
T16	502	102
T17	5367	4967
T18	502	102

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7903577	40
T9	729	1
T10	124227	0
T11	12474	0
T12	22676	0
T22	0	1
T23	493	0
T25	0	1
T30	20486	0
T58	556	0
T66	409	0
T67	422	0
T68	526	0
T144	0	1
T169	0	1
T171	0	2
T173	0	1
T192	0	1
T208	0	1
T219	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T13
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T13
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T9,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T8,T9,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T9,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T5,T13
1	1	Covered	T8,T9,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T10
0	1	Covered	T220
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T10
0	1	Covered	T10,T25,T22
1	0	Covered	T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T9,T10
1	-	Covered	T10,T25,T22

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T10
DetectSt	168	Covered	T8,T9,T10
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T8,T9,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T10
DebounceSt->IdleSt	163	Covered	T108
DetectSt->IdleSt	186	Covered	T220
DetectSt->StableSt	191	Covered	T8,T9,T10
IdleSt->DebounceSt	148	Covered	T8,T9,T10
StableSt->IdleSt	206	Covered	T10,T25,T22

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T9,T10
0	1	Covered	T8,T9,T10
0	0	Excluded	T1,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T108
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T10
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T10
DetectSt	-	-	-	-	1	-	-	Covered	T220
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T25,T22
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7903577	81	0	0
CntIncr_A	7903577	200537	0	0
CntNoWrap_A	7903577	7251006	0	0
DetectStDropOut_A	7903577	1	0	0
DetectedOut_A	7903577	153573	0	0
DetectedPulseOut_A	7903577	39	0	0
DisabledIdleSt_A	7903577	6274769	0	0
DisabledNoDetection_A	7903577	6276997	0	0
EnterDebounceSt_A	7903577	41	0	0
EnterDetectSt_A	7903577	40	0	0
EnterStableSt_A	7903577	39	0	0
PulseIsPulse_A	7903577	39	0	0
StayInStableSt	7903577	153510	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7903577	6015	0	0
gen_low_level_sva.LowLevelEvent_A	7903577	7253370	0	0
gen_not_sticky_sva.StableStDropOut_A	7903577	14	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7903577	81
T8	602	2
T9	729	2
T10	124227	4
T22	0	4
T23	493	0
T25	0	2
T26	532	0
T40	0	2
T41	0	2
T57	639	0
T58	556	0
T60	1418	0
T66	409	0
T67	422	0
T168	0	2
T169	0	4
T208	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	7903577	200537
T8	602	62
T9	729	60
T10	124227	54392
T22	0	92
T23	493	0
T25	0	17
T26	532	0
T40	0	73
T41	0	18
T57	639	0
T58	556	0
T60	1418	0
T66	409	0
T67	422	0
T168	0	44168
T169	0	158
T208	0	54

CntNoWrap_A

Name	Attempts	Real Successes
Total	7903577	7251006
T1	25831	25363
T2	1099	698
T5	4417	649
T6	651	250
T13	5067	4666
T14	427	26
T15	508	107
T16	502	101
T17	5367	4966
T18	502	101

DetectStDropOut_A

Name	Attempts	Real Successes
Total	7903577	1
T184	681	0
T220	963	1
T221	15439	0
T222	725	0
T223	424	0
T224	509	0
T225	20756	0
T226	1444	0
T227	522	0
T228	719	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7903577	153573
T8	602	42
T9	729	41
T10	124227	88
T22	0	113
T23	493	0
T25	0	40
T26	532	0
T40	0	271
T41	0	2
T57	639	0
T58	556	0
T60	1418	0
T66	409	0
T67	422	0
T168	0	55525
T169	0	87
T208	0	296

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7903577	39
T8	602	1
T9	729	1
T10	124227	2
T22	0	2
T23	493	0
T25	0	1
T26	532	0
T40	0	1
T41	0	1
T57	639	0
T58	556	0
T60	1418	0
T66	409	0
T67	422	0
T168	0	1
T169	0	2
T208	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7903577	6274769
T1	25831	25363
T2	1099	698
T5	4417	649
T6	651	250
T13	5067	4666
T14	427	26
T15	508	107
T16	502	101
T17	5367	4966
T18	502	101

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7903577	6276997
T1	25831	25373
T2	1099	699
T5	4417	660
T6	651	251
T13	5067	4667
T14	427	27
T15	508	108
T16	502	102
T17	5367	4967
T18	502	102

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7903577	41
T8	602	1
T9	729	1
T10	124227	2
T22	0	2
T23	493	0
T25	0	1
T26	532	0
T40	0	1
T41	0	1
T57	639	0
T58	556	0
T60	1418	0
T66	409	0
T67	422	0
T168	0	1
T169	0	2
T208	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7903577	40
T8	602	1
T9	729	1
T10	124227	2
T22	0	2
T23	493	0
T25	0	1
T26	532	0
T40	0	1
T41	0	1
T57	639	0
T58	556	0
T60	1418	0
T66	409	0
T67	422	0
T168	0	1
T169	0	2
T208	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	7903577	39
T8	602	1
T9	729	1
T10	124227	2
T22	0	2
T23	493	0
T25	0	1
T26	532	0
T40	0	1
T41	0	1
T57	639	0
T58	556	0
T60	1418	0
T66	409	0
T67	422	0
T168	0	1
T169	0	2
T208	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7903577	39
T8	602	1
T9	729	1
T10	124227	2
T22	0	2
T23	493	0
T25	0	1
T26	532	0
T40	0	1
T41	0	1
T57	639	0
T58	556	0
T60	1418	0
T66	409	0
T67	422	0
T168	0	1
T169	0	2
T208	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7903577	153510
T8	602	40
T9	729	39
T10	124227	85
T22	0	110
T23	493	0
T25	0	39
T26	532	0
T40	0	269
T41	0	1
T57	639	0
T58	556	0
T60	1418	0
T66	409	0
T67	422	0
T168	0	55523
T169	0	84
T208	0	294

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	7903577	6015
T1	25831	10
T2	1099	0
T5	4417	9
T6	651	0
T13	5067	12
T14	427	2
T15	508	8
T16	502	5
T17	5367	18
T18	502	5
T48	0	4
T70	0	4

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	7903577	7253370
T1	25831	25373
T2	1099	699
T5	4417	660
T6	651	251
T13	5067	4667
T14	427	27
T15	508	108
T16	502	102
T17	5367	4967
T18	502	102

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7903577	14
T10	124227	1
T11	12474	0
T12	22676	0
T22	0	1
T25	0	1
T27	766	0
T30	20486	0
T41	0	1
T43	20986	0
T49	624	0
T67	422	0
T68	526	0
T69	409	0
T102	0	1
T127	0	1
T169	0	1
T181	0	1
T183	0	1
T194	0	1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr