Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.85	100.00	90.48		100.00	100.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.85	100.00	90.48		100.00	100.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T3,T9,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T3,T9,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T3,T9,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T40
1	0	Covered	T1,T5,T13
1	1	Covered	T3,T9,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T40
0	1	Covered	T41,T229
1	0	Covered	T53

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T40
0	1	Covered	T40,T41,T140
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T9,T40
1	-	Covered	T40,T41,T140

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T9,T40
DetectSt	168	Covered	T3,T9,T40
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T3,T9,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T9,T40
DebounceSt->IdleSt	163	Covered	T22,T108,T230
DetectSt->IdleSt	186	Covered	T41,T53,T229
DetectSt->StableSt	191	Covered	T3,T9,T40
IdleSt->DebounceSt	148	Covered	T3,T9,T40
StableSt->IdleSt	206	Covered	T40,T41,T140

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T9,T40
0	1	Covered	T3,T9,T40
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T40
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T9,T40
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T108
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T9,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T22,T230,T181
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T9,T40
DetectSt	-	-	-	-	1	-	-	Covered	T41,T53,T229
DetectSt	-	-	-	-	0	1	-	Covered	T3,T9,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T41,T140
StableSt	-	-	-	-	-	-	0	Covered	T3,T9,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7903577	147	0	0
CntIncr_A	7903577	166401	0	0
CntNoWrap_A	7903577	7250940	0	0
DetectStDropOut_A	7903577	2	0	0
DetectedOut_A	7903577	168162	0	0
DetectedPulseOut_A	7903577	67	0	0
DisabledIdleSt_A	7903577	6636469	0	0
DisabledNoDetection_A	7903577	6638689	0	0
EnterDebounceSt_A	7903577	77	0	0
EnterDetectSt_A	7903577	70	0	0
EnterStableSt_A	7903577	67	0	0
PulseIsPulse_A	7903577	67	0	0
StayInStableSt	7903577	168064	0	0
gen_high_level_sva.HighLevelEvent_A	7903577	7253370	0	0
gen_not_sticky_sva.StableStDropOut_A	7903577	36	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	147	0	0
T3	596	2	0	0
T4	1937	0	0	0
T7	850	0	0	0
T9	0	2	0	0
T22	0	1	0	0
T40	0	2	0	0
T41	0	6	0	0
T55	615	0	0	0
T56	740	0	0	0
T59	1557	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T108	0	1	0	0
T140	0	4	0	0
T204	0	2	0	0
T208	0	4	0	0
T231	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	166401	0	0
T3	596	23	0	0
T4	1937	0	0	0
T7	850	0	0	0
T9	0	60	0	0
T22	0	26	0	0
T40	0	73	0	0
T41	0	206	0	0
T55	615	0	0	0
T56	740	0	0	0
T59	1557	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T108	0	28	0	0
T140	0	32	0	0
T204	0	61	0	0
T208	0	108	0	0
T231	0	56	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7250940	0	0
T1	25831	25363	0	0
T2	1099	698	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	4666	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	4966	0	0
T18	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	2	0	0
T41	263390	1	0	0
T139	11128	0	0	0
T141	32603	0	0	0
T188	422	0	0	0
T189	29382	0	0	0
T190	22091	0	0	0
T191	505	0	0	0
T199	40079	0	0	0
T200	5322	0	0	0
T201	503	0	0	0
T229	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	168162	0	0
T3	596	75	0	0
T4	1937	0	0	0
T7	850	0	0	0
T9	0	102	0	0
T40	0	43	0	0
T41	0	510	0	0
T55	615	0	0	0
T56	740	0	0	0
T59	1557	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T123	0	275	0	0
T140	0	85	0	0
T192	0	39	0	0
T204	0	30	0	0
T208	0	296	0	0
T231	0	22	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	67	0	0
T3	596	1	0	0
T4	1937	0	0	0
T7	850	0	0	0
T9	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T55	615	0	0	0
T56	740	0	0	0
T59	1557	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T123	0	1	0	0
T140	0	2	0	0
T192	0	1	0	0
T204	0	1	0	0
T208	0	2	0	0
T231	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6636469	0	0
T1	25831	25363	0	0
T2	1099	698	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	4666	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	4966	0	0
T18	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6638689	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	77	0	0
T3	596	1	0	0
T4	1937	0	0	0
T7	850	0	0	0
T9	0	1	0	0
T22	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T55	615	0	0	0
T56	740	0	0	0
T59	1557	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T108	0	1	0	0
T140	0	2	0	0
T204	0	1	0	0
T208	0	2	0	0
T231	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	70	0	0
T3	596	1	0	0
T4	1937	0	0	0
T7	850	0	0	0
T9	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T55	615	0	0	0
T56	740	0	0	0
T59	1557	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T123	0	1	0	0
T140	0	2	0	0
T192	0	1	0	0
T204	0	1	0	0
T208	0	2	0	0
T231	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	67	0	0
T3	596	1	0	0
T4	1937	0	0	0
T7	850	0	0	0
T9	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T55	615	0	0	0
T56	740	0	0	0
T59	1557	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T123	0	1	0	0
T140	0	2	0	0
T192	0	1	0	0
T204	0	1	0	0
T208	0	2	0	0
T231	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	67	0	0
T3	596	1	0	0
T4	1937	0	0	0
T7	850	0	0	0
T9	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T55	615	0	0	0
T56	740	0	0	0
T59	1557	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T123	0	1	0	0
T140	0	2	0	0
T192	0	1	0	0
T204	0	1	0	0
T208	0	2	0	0
T231	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	168064	0	0
T3	596	73	0	0
T4	1937	0	0	0
T7	850	0	0	0
T9	0	100	0	0
T40	0	42	0	0
T41	0	507	0	0
T55	615	0	0	0
T56	740	0	0	0
T59	1557	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T123	0	273	0	0
T140	0	82	0	0
T192	0	37	0	0
T204	0	29	0	0
T208	0	293	0	0
T231	0	21	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7253370	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	36	0	0
T22	166215	0	0	0
T25	13294	0	0	0
T39	8763	0	0	0
T40	850	1	0	0
T41	0	1	0	0
T42	15471	0	0	0
T44	643	0	0	0
T45	679	0	0	0
T61	3451	0	0	0
T126	0	1	0	0
T140	0	1	0	0
T160	430	0	0	0
T161	616	0	0	0
T176	0	1	0	0
T178	0	1	0	0
T181	0	1	0	0
T204	0	1	0	0
T208	0	1	0	0
T231	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T13
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T13
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T10,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T7,T10,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T10,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T9,T10
1	0	Covered	T1,T5,T13
1	1	Covered	T7,T10,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T25
0	1	Not Covered
1	0	Covered	T53

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T25
0	1	Covered	T10,T25,T140
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T10,T25
1	-	Covered	T10,T25,T140

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T10,T25
DetectSt	168	Covered	T7,T10,T25
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T7,T10,T25

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T10,T25
DebounceSt->IdleSt	163	Covered	T180,T108
DetectSt->IdleSt	186	Covered	T53
DetectSt->StableSt	191	Covered	T7,T10,T25
IdleSt->DebounceSt	148	Covered	T7,T10,T25
StableSt->IdleSt	206	Covered	T10,T25,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T10,T25
0	1	Covered	T7,T10,T25
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T25
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T10,T25
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T108
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T10,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T180
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T10,T25
DetectSt	-	-	-	-	1	-	-	Covered	T53
DetectSt	-	-	-	-	0	1	-	Covered	T7,T10,T25
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T25,T140
StableSt	-	-	-	-	-	-	0	Covered	T7,T10,T25
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7903577	84	0	0
CntIncr_A	7903577	100173	0	0
CntNoWrap_A	7903577	7251003	0	0
DetectStDropOut_A	7903577	0	0	0
DetectedOut_A	7903577	30585	0	0
DetectedPulseOut_A	7903577	40	0	0
DisabledIdleSt_A	7903577	6762665	0	0
DisabledNoDetection_A	7903577	6764893	0	0
EnterDebounceSt_A	7903577	43	0	0
EnterDetectSt_A	7903577	41	0	0
EnterStableSt_A	7903577	40	0	0
PulseIsPulse_A	7903577	40	0	0
StayInStableSt	7903577	30517	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7903577	6073	0	0
gen_low_level_sva.LowLevelEvent_A	7903577	7253370	0	0
gen_not_sticky_sva.StableStDropOut_A	7903577	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	84	0	0
T7	850	2	0	0
T8	602	0	0	0
T9	729	0	0	0
T10	0	4	0	0
T22	0	2	0	0
T25	0	6	0	0
T26	532	0	0	0
T41	0	2	0	0
T55	615	0	0	0
T56	740	0	0	0
T57	639	0	0	0
T58	556	0	0	0
T60	1418	0	0	0
T71	502	0	0	0
T140	0	2	0	0
T168	0	2	0	0
T171	0	2	0	0
T180	0	3	0	0
T198	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	100173	0	0
T7	850	36	0	0
T8	602	0	0	0
T9	729	0	0	0
T10	0	54392	0	0
T22	0	26	0	0
T25	0	113	0	0
T26	532	0	0	0
T41	0	18	0	0
T55	615	0	0	0
T56	740	0	0	0
T57	639	0	0	0
T58	556	0	0	0
T60	1418	0	0	0
T71	502	0	0	0
T140	0	16	0	0
T168	0	44168	0	0
T171	0	64	0	0
T180	0	68	0	0
T198	0	18	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7251003	0	0
T1	25831	25363	0	0
T2	1099	698	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	4666	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	4966	0	0
T18	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	30585	0	0
T7	850	257	0	0
T8	602	0	0	0
T9	729	0	0	0
T10	0	27285	0	0
T22	0	54	0	0
T25	0	290	0	0
T26	532	0	0	0
T41	0	62	0	0
T55	615	0	0	0
T56	740	0	0	0
T57	639	0	0	0
T58	556	0	0	0
T60	1418	0	0	0
T71	502	0	0	0
T140	0	40	0	0
T168	0	41	0	0
T171	0	16	0	0
T180	0	23	0	0
T198	0	47	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	40	0	0
T7	850	1	0	0
T8	602	0	0	0
T9	729	0	0	0
T10	0	2	0	0
T22	0	1	0	0
T25	0	3	0	0
T26	532	0	0	0
T41	0	1	0	0
T55	615	0	0	0
T56	740	0	0	0
T57	639	0	0	0
T58	556	0	0	0
T60	1418	0	0	0
T71	502	0	0	0
T140	0	1	0	0
T168	0	1	0	0
T171	0	1	0	0
T180	0	1	0	0
T198	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6762665	0	0
T1	25831	25363	0	0
T2	1099	698	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	4666	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	4966	0	0
T18	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6764893	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	43	0	0
T7	850	1	0	0
T8	602	0	0	0
T9	729	0	0	0
T10	0	2	0	0
T22	0	1	0	0
T25	0	3	0	0
T26	532	0	0	0
T41	0	1	0	0
T55	615	0	0	0
T56	740	0	0	0
T57	639	0	0	0
T58	556	0	0	0
T60	1418	0	0	0
T71	502	0	0	0
T140	0	1	0	0
T168	0	1	0	0
T171	0	1	0	0
T180	0	2	0	0
T198	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	41	0	0
T7	850	1	0	0
T8	602	0	0	0
T9	729	0	0	0
T10	0	2	0	0
T22	0	1	0	0
T25	0	3	0	0
T26	532	0	0	0
T41	0	1	0	0
T55	615	0	0	0
T56	740	0	0	0
T57	639	0	0	0
T58	556	0	0	0
T60	1418	0	0	0
T71	502	0	0	0
T140	0	1	0	0
T168	0	1	0	0
T171	0	1	0	0
T180	0	1	0	0
T198	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	40	0	0
T7	850	1	0	0
T8	602	0	0	0
T9	729	0	0	0
T10	0	2	0	0
T22	0	1	0	0
T25	0	3	0	0
T26	532	0	0	0
T41	0	1	0	0
T55	615	0	0	0
T56	740	0	0	0
T57	639	0	0	0
T58	556	0	0	0
T60	1418	0	0	0
T71	502	0	0	0
T140	0	1	0	0
T168	0	1	0	0
T171	0	1	0	0
T180	0	1	0	0
T198	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	40	0	0
T7	850	1	0	0
T8	602	0	0	0
T9	729	0	0	0
T10	0	2	0	0
T22	0	1	0	0
T25	0	3	0	0
T26	532	0	0	0
T41	0	1	0	0
T55	615	0	0	0
T56	740	0	0	0
T57	639	0	0	0
T58	556	0	0	0
T60	1418	0	0	0
T71	502	0	0	0
T140	0	1	0	0
T168	0	1	0	0
T171	0	1	0	0
T180	0	1	0	0
T198	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	30517	0	0
T7	850	255	0	0
T8	602	0	0	0
T9	729	0	0	0
T10	0	27282	0	0
T22	0	52	0	0
T25	0	285	0	0
T26	532	0	0	0
T41	0	60	0	0
T55	615	0	0	0
T56	740	0	0	0
T57	639	0	0	0
T58	556	0	0	0
T60	1418	0	0	0
T71	502	0	0	0
T140	0	39	0	0
T168	0	39	0	0
T171	0	15	0	0
T180	0	22	0	0
T198	0	45	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6073	0	0
T1	25831	9	0	0
T2	1099	0	0	0
T5	4417	10	0	0
T6	651	0	0	0
T13	5067	10	0	0
T14	427	1	0	0
T15	508	5	0	0
T16	502	6	0	0
T17	5367	28	0	0
T18	502	5	0	0
T48	0	3	0	0
T70	0	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7253370	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	12	0	0
T10	124227	1	0	0
T11	12474	0	0	0
T12	22676	0	0	0
T25	0	1	0	0
T27	766	0	0	0
T30	20486	0	0	0
T43	20986	0	0	0
T49	624	0	0	0
T67	422	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T140	0	1	0	0
T171	0	1	0	0
T180	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T196	0	1	0	0
T205	0	1	0	0
T232	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T10,T40,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T10,T40,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T10,T40,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T40,T25
1	0	Covered	T1,T5,T13
1	1	Covered	T10,T40,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T40,T25
0	1	Covered	T210
1	0	Covered	T53

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T40,T25
0	1	Covered	T10,T40,T25
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T40,T25
1	-	Covered	T10,T40,T25

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T40,T25
DetectSt	168	Covered	T10,T40,T25
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T10,T40,T25

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T40,T25
DebounceSt->IdleSt	163	Covered	T10,T108,T196
DetectSt->IdleSt	186	Covered	T53,T210
DetectSt->StableSt	191	Covered	T10,T40,T25
IdleSt->DebounceSt	148	Covered	T10,T40,T25
StableSt->IdleSt	206	Covered	T10,T40,T25

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T40,T25
0	1	Covered	T10,T40,T25
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T40,T25
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T40,T25
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T108
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T40,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T196,T220
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T40,T25
DetectSt	-	-	-	-	1	-	-	Covered	T53,T210
DetectSt	-	-	-	-	0	1	-	Covered	T10,T40,T25
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T40,T25
StableSt	-	-	-	-	-	-	0	Covered	T10,T40,T25
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7903577	154	0	0
CntIncr_A	7903577	204473	0	0
CntNoWrap_A	7903577	7250933	0	0
DetectStDropOut_A	7903577	1	0	0
DetectedOut_A	7903577	178164	0	0
DetectedPulseOut_A	7903577	72	0	0
DisabledIdleSt_A	7903577	6567933	0	0
DisabledNoDetection_A	7903577	6570166	0	0
EnterDebounceSt_A	7903577	80	0	0
EnterDetectSt_A	7903577	74	0	0
EnterStableSt_A	7903577	72	0	0
PulseIsPulse_A	7903577	72	0	0
StayInStableSt	7903577	178065	0	0
gen_high_level_sva.HighLevelEvent_A	7903577	7253370	0	0
gen_not_sticky_sva.StableStDropOut_A	7903577	45	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	154	0	0
T10	124227	5	0	0
T11	12474	0	0	0
T12	22676	0	0	0
T22	0	2	0	0
T25	0	6	0	0
T27	766	0	0	0
T30	20486	0	0	0
T38	0	2	0	0
T40	0	2	0	0
T41	0	4	0	0
T43	20986	0	0	0
T49	624	0	0	0
T67	422	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T140	0	2	0	0
T169	0	4	0	0
T171	0	4	0	0
T208	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	204473	0	0
T10	124227	81588	0	0
T11	12474	0	0	0
T12	22676	0	0	0
T22	0	26	0	0
T25	0	51	0	0
T27	766	0	0	0
T30	20486	0	0	0
T38	0	54	0	0
T40	0	73	0	0
T41	0	94	0	0
T43	20986	0	0	0
T49	624	0	0	0
T67	422	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T140	0	16	0	0
T169	0	158	0	0
T171	0	128	0	0
T208	0	54	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7250933	0	0
T1	25831	25363	0	0
T2	1099	698	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	4666	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	4966	0	0
T18	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	1	0	0
T210	649	1	0	0
T233	92709	0	0	0
T234	522	0	0	0
T235	28337	0	0	0
T236	423	0	0	0
T237	493	0	0	0
T238	525	0	0	0
T239	785	0	0	0
T240	522	0	0	0
T241	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	178164	0	0
T10	124227	27284	0	0
T11	12474	0	0	0
T12	22676	0	0	0
T22	0	97	0	0
T25	0	146	0	0
T27	766	0	0	0
T30	20486	0	0	0
T38	0	112	0	0
T40	0	139	0	0
T41	0	15	0	0
T43	20986	0	0	0
T49	624	0	0	0
T67	422	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T140	0	58	0	0
T169	0	113	0	0
T171	0	108	0	0
T208	0	53	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	72	0	0
T10	124227	2	0	0
T11	12474	0	0	0
T12	22676	0	0	0
T22	0	1	0	0
T25	0	3	0	0
T27	766	0	0	0
T30	20486	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T43	20986	0	0	0
T49	624	0	0	0
T67	422	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T140	0	1	0	0
T169	0	2	0	0
T171	0	2	0	0
T208	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6567933	0	0
T1	25831	25363	0	0
T2	1099	698	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	4666	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	4966	0	0
T18	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6570166	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	80	0	0
T10	124227	3	0	0
T11	12474	0	0	0
T12	22676	0	0	0
T22	0	1	0	0
T25	0	3	0	0
T27	766	0	0	0
T30	20486	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T43	20986	0	0	0
T49	624	0	0	0
T67	422	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T140	0	1	0	0
T169	0	2	0	0
T171	0	2	0	0
T208	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	74	0	0
T10	124227	2	0	0
T11	12474	0	0	0
T12	22676	0	0	0
T22	0	1	0	0
T25	0	3	0	0
T27	766	0	0	0
T30	20486	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T43	20986	0	0	0
T49	624	0	0	0
T67	422	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T140	0	1	0	0
T169	0	2	0	0
T171	0	2	0	0
T208	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	72	0	0
T10	124227	2	0	0
T11	12474	0	0	0
T12	22676	0	0	0
T22	0	1	0	0
T25	0	3	0	0
T27	766	0	0	0
T30	20486	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T43	20986	0	0	0
T49	624	0	0	0
T67	422	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T140	0	1	0	0
T169	0	2	0	0
T171	0	2	0	0
T208	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	72	0	0
T10	124227	2	0	0
T11	12474	0	0	0
T12	22676	0	0	0
T22	0	1	0	0
T25	0	3	0	0
T27	766	0	0	0
T30	20486	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T43	20986	0	0	0
T49	624	0	0	0
T67	422	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T140	0	1	0	0
T169	0	2	0	0
T171	0	2	0	0
T208	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	178065	0	0
T10	124227	27281	0	0
T11	12474	0	0	0
T12	22676	0	0	0
T22	0	96	0	0
T25	0	142	0	0
T27	766	0	0	0
T30	20486	0	0	0
T38	0	111	0	0
T40	0	138	0	0
T41	0	13	0	0
T43	20986	0	0	0
T49	624	0	0	0
T67	422	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T140	0	57	0	0
T169	0	110	0	0
T171	0	105	0	0
T208	0	52	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7253370	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	45	0	0
T10	124227	1	0	0
T11	12474	0	0	0
T12	22676	0	0	0
T22	0	1	0	0
T25	0	2	0	0
T27	766	0	0	0
T30	20486	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T43	20986	0	0	0
T49	624	0	0	0
T67	422	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T140	0	1	0	0
T169	0	1	0	0
T171	0	1	0	0
T208	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T13
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T13
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T10,T25,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T10,T25,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T10,T25,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T25,T39
1	0	Covered	T1,T5,T13
1	1	Covered	T10,T25,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T25,T22
0	1	Covered	T210
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T25,T22
0	1	Covered	T10,T25,T41
1	0	Covered	T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T25,T22
1	-	Covered	T10,T25,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T25,T22
DetectSt	168	Covered	T10,T25,T22
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T10,T25,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T25,T22
DebounceSt->IdleSt	163	Covered	T10,T108,T144
DetectSt->IdleSt	186	Covered	T210
DetectSt->StableSt	191	Covered	T10,T25,T22
IdleSt->DebounceSt	148	Covered	T10,T25,T22
StableSt->IdleSt	206	Covered	T10,T25,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T25,T22
0	1	Covered	T10,T25,T22
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T25,T22
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T25,T22
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T108
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T25,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T144,T183
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T25,T22
DetectSt	-	-	-	-	1	-	-	Covered	T210
DetectSt	-	-	-	-	0	1	-	Covered	T10,T25,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T25,T41
StableSt	-	-	-	-	-	-	0	Covered	T10,T25,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7903577	102	0	0
CntIncr_A	7903577	209861	0	0
CntNoWrap_A	7903577	7250985	0	0
DetectStDropOut_A	7903577	1	0	0
DetectedOut_A	7903577	271601	0	0
DetectedPulseOut_A	7903577	48	0	0
DisabledIdleSt_A	7903577	6273557	0	0
DisabledNoDetection_A	7903577	6275780	0	0
EnterDebounceSt_A	7903577	53	0	0
EnterDetectSt_A	7903577	49	0	0
EnterStableSt_A	7903577	48	0	0
PulseIsPulse_A	7903577	48	0	0
StayInStableSt	7903577	271527	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7903577	6092	0	0
gen_low_level_sva.LowLevelEvent_A	7903577	7253370	0	0
gen_not_sticky_sva.StableStDropOut_A	7903577	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	102	0	0
T10	124227	3	0	0
T11	12474	0	0	0
T12	22676	0	0	0
T22	0	2	0	0
T25	0	6	0	0
T27	766	0	0	0
T30	20486	0	0	0
T41	0	4	0	0
T43	20986	0	0	0
T49	624	0	0	0
T67	422	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T108	0	1	0	0
T168	0	2	0	0
T169	0	2	0	0
T180	0	4	0	0
T204	0	2	0	0
T242	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	209861	0	0
T10	124227	54392	0	0
T11	12474	0	0	0
T12	22676	0	0	0
T22	0	26	0	0
T25	0	113	0	0
T27	766	0	0	0
T30	20486	0	0	0
T41	0	200	0	0
T43	20986	0	0	0
T49	624	0	0	0
T67	422	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T108	0	27	0	0
T168	0	44168	0	0
T169	0	79	0	0
T180	0	68	0	0
T204	0	61	0	0
T242	0	28	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7250985	0	0
T1	25831	25363	0	0
T2	1099	698	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	4666	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	4966	0	0
T18	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	1	0	0
T210	649	1	0	0
T233	92709	0	0	0
T234	522	0	0	0
T235	28337	0	0	0
T236	423	0	0	0
T237	493	0	0	0
T238	525	0	0	0
T239	785	0	0	0
T240	522	0	0	0
T241	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	271601	0	0
T10	124227	40	0	0
T11	12474	0	0	0
T12	22676	0	0	0
T22	0	53	0	0
T25	0	60	0	0
T27	766	0	0	0
T30	20486	0	0	0
T41	0	182	0	0
T43	20986	0	0	0
T49	624	0	0	0
T67	422	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T168	0	143907	0	0
T169	0	122	0	0
T180	0	135	0	0
T192	0	38	0	0
T204	0	40	0	0
T242	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	48	0	0
T10	124227	1	0	0
T11	12474	0	0	0
T12	22676	0	0	0
T22	0	1	0	0
T25	0	3	0	0
T27	766	0	0	0
T30	20486	0	0	0
T41	0	2	0	0
T43	20986	0	0	0
T49	624	0	0	0
T67	422	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T168	0	1	0	0
T169	0	1	0	0
T180	0	2	0	0
T192	0	1	0	0
T204	0	1	0	0
T242	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6273557	0	0
T1	25831	25363	0	0
T2	1099	698	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	4666	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	4966	0	0
T18	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6275780	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	53	0	0
T10	124227	2	0	0
T11	12474	0	0	0
T12	22676	0	0	0
T22	0	1	0	0
T25	0	3	0	0
T27	766	0	0	0
T30	20486	0	0	0
T41	0	2	0	0
T43	20986	0	0	0
T49	624	0	0	0
T67	422	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T108	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0
T180	0	2	0	0
T204	0	1	0	0
T242	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	49	0	0
T10	124227	1	0	0
T11	12474	0	0	0
T12	22676	0	0	0
T22	0	1	0	0
T25	0	3	0	0
T27	766	0	0	0
T30	20486	0	0	0
T41	0	2	0	0
T43	20986	0	0	0
T49	624	0	0	0
T67	422	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T168	0	1	0	0
T169	0	1	0	0
T180	0	2	0	0
T192	0	1	0	0
T204	0	1	0	0
T242	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	48	0	0
T10	124227	1	0	0
T11	12474	0	0	0
T12	22676	0	0	0
T22	0	1	0	0
T25	0	3	0	0
T27	766	0	0	0
T30	20486	0	0	0
T41	0	2	0	0
T43	20986	0	0	0
T49	624	0	0	0
T67	422	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T168	0	1	0	0
T169	0	1	0	0
T180	0	2	0	0
T192	0	1	0	0
T204	0	1	0	0
T242	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	48	0	0
T10	124227	1	0	0
T11	12474	0	0	0
T12	22676	0	0	0
T22	0	1	0	0
T25	0	3	0	0
T27	766	0	0	0
T30	20486	0	0	0
T41	0	2	0	0
T43	20986	0	0	0
T49	624	0	0	0
T67	422	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T168	0	1	0	0
T169	0	1	0	0
T180	0	2	0	0
T192	0	1	0	0
T204	0	1	0	0
T242	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	271527	0	0
T10	124227	39	0	0
T11	12474	0	0	0
T12	22676	0	0	0
T22	0	51	0	0
T25	0	56	0	0
T27	766	0	0	0
T30	20486	0	0	0
T41	0	179	0	0
T43	20986	0	0	0
T49	624	0	0	0
T67	422	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T168	0	143905	0	0
T169	0	121	0	0
T180	0	132	0	0
T192	0	36	0	0
T204	0	38	0	0
T242	0	36	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6092	0	0
T1	25831	14	0	0
T2	1099	0	0	0
T3	0	1	0	0
T5	4417	13	0	0
T6	651	0	0	0
T13	5067	9	0	0
T14	427	3	0	0
T15	508	5	0	0
T16	502	6	0	0
T17	5367	26	0	0
T18	502	6	0	0
T48	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7253370	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	21	0	0
T10	124227	1	0	0
T11	12474	0	0	0
T12	22676	0	0	0
T25	0	2	0	0
T27	766	0	0	0
T30	20486	0	0	0
T41	0	1	0	0
T43	20986	0	0	0
T49	624	0	0	0
T67	422	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T127	0	1	0	0
T169	0	1	0	0
T180	0	1	0	0
T183	0	1	0	0
T209	0	1	0	0
T220	0	1	0	0
T243	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T3,T9,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T3,T9,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T3,T9,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T9
1	0	Covered	T1,T5,T6
1	1	Covered	T3,T9,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T10
0	1	Covered	T3,T183,T185
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T10
0	1	Covered	T9,T10,T39
1	0	Covered	T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T9,T10
1	-	Covered	T9,T10,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T9,T10
DetectSt	168	Covered	T3,T9,T10
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T3,T9,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T9,T10
DebounceSt->IdleSt	163	Covered	T81,T108,T216
DetectSt->IdleSt	186	Covered	T3,T183,T185
DetectSt->StableSt	191	Covered	T3,T9,T10
IdleSt->DebounceSt	148	Covered	T3,T9,T10
StableSt->IdleSt	206	Covered	T9,T10,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T9,T10
0	1	Covered	T3,T9,T10
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T10
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T9,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T108
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T9,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T81,T216,T244
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T9,T10
DetectSt	-	-	-	-	1	-	-	Covered	T3,T183,T185
DetectSt	-	-	-	-	0	1	-	Covered	T3,T9,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T10,T39
StableSt	-	-	-	-	-	-	0	Covered	T3,T9,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7903577	126	0	0
CntIncr_A	7903577	132232	0	0
CntNoWrap_A	7903577	7250961	0	0
DetectStDropOut_A	7903577	3	0	0
DetectedOut_A	7903577	30828	0	0
DetectedPulseOut_A	7903577	57	0	0
DisabledIdleSt_A	7903577	7004026	0	0
DisabledNoDetection_A	7903577	7006262	0	0
EnterDebounceSt_A	7903577	66	0	0
EnterDetectSt_A	7903577	60	0	0
EnterStableSt_A	7903577	57	0	0
PulseIsPulse_A	7903577	57	0	0
StayInStableSt	7903577	30750	0	0
gen_high_level_sva.HighLevelEvent_A	7903577	7253370	0	0
gen_not_sticky_sva.StableStDropOut_A	7903577	35	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	126	0	0
T3	596	4	0	0
T4	1937	0	0	0
T7	850	0	0	0
T9	0	2	0	0
T10	0	4	0	0
T22	0	4	0	0
T38	0	2	0	0
T39	0	4	0	0
T40	0	2	0	0
T41	0	4	0	0
T55	615	0	0	0
T56	740	0	0	0
T59	1557	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T81	0	1	0	0
T170	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	132232	0	0
T3	596	46	0	0
T4	1937	0	0	0
T7	850	0	0	0
T9	0	60	0	0
T10	0	54392	0	0
T22	0	92	0	0
T38	0	54	0	0
T39	0	124	0	0
T40	0	73	0	0
T41	0	94	0	0
T55	615	0	0	0
T56	740	0	0	0
T59	1557	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T81	0	16	0	0
T170	0	18	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7250961	0	0
T1	25831	25363	0	0
T2	1099	698	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	4666	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	4966	0	0
T18	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	3	0	0
T3	596	1	0	0
T4	1937	0	0	0
T7	850	0	0	0
T55	615	0	0	0
T56	740	0	0	0
T59	1557	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T183	0	1	0	0
T185	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	30828	0	0
T3	596	75	0	0
T4	1937	0	0	0
T7	850	0	0	0
T9	0	96	0	0
T10	0	27501	0	0
T22	0	157	0	0
T38	0	1	0	0
T39	0	80	0	0
T40	0	154	0	0
T41	0	129	0	0
T55	615	0	0	0
T56	740	0	0	0
T59	1557	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T170	0	46	0	0
T171	0	61	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	57	0	0
T3	596	1	0	0
T4	1937	0	0	0
T7	850	0	0	0
T9	0	1	0	0
T10	0	2	0	0
T22	0	2	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	2	0	0
T55	615	0	0	0
T56	740	0	0	0
T59	1557	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T170	0	1	0	0
T171	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7004026	0	0
T1	25831	25363	0	0
T2	1099	698	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	4666	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	4966	0	0
T18	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7006262	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	66	0	0
T3	596	2	0	0
T4	1937	0	0	0
T7	850	0	0	0
T9	0	1	0	0
T10	0	2	0	0
T22	0	2	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	2	0	0
T55	615	0	0	0
T56	740	0	0	0
T59	1557	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T81	0	1	0	0
T170	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	60	0	0
T3	596	2	0	0
T4	1937	0	0	0
T7	850	0	0	0
T9	0	1	0	0
T10	0	2	0	0
T22	0	2	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	2	0	0
T55	615	0	0	0
T56	740	0	0	0
T59	1557	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T170	0	1	0	0
T171	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	57	0	0
T3	596	1	0	0
T4	1937	0	0	0
T7	850	0	0	0
T9	0	1	0	0
T10	0	2	0	0
T22	0	2	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	2	0	0
T55	615	0	0	0
T56	740	0	0	0
T59	1557	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T170	0	1	0	0
T171	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	57	0	0
T3	596	1	0	0
T4	1937	0	0	0
T7	850	0	0	0
T9	0	1	0	0
T10	0	2	0	0
T22	0	2	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	2	0	0
T55	615	0	0	0
T56	740	0	0	0
T59	1557	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T170	0	1	0	0
T171	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	30750	0	0
T3	596	73	0	0
T4	1937	0	0	0
T7	850	0	0	0
T9	0	95	0	0
T10	0	27498	0	0
T22	0	155	0	0
T39	0	77	0	0
T40	0	152	0	0
T41	0	126	0	0
T55	615	0	0	0
T56	740	0	0	0
T59	1557	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T72	402	0	0	0
T73	440	0	0	0
T170	0	44	0	0
T171	0	60	0	0
T204	0	30	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7253370	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	35	0	0
T9	729	1	0	0
T10	124227	1	0	0
T11	12474	0	0	0
T12	22676	0	0	0
T22	0	2	0	0
T23	493	0	0	0
T30	20486	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T58	556	0	0	0
T66	409	0	0	0
T67	422	0	0	0
T68	526	0	0	0
T123	0	2	0	0
T171	0	1	0	0
T173	0	2	0	0
T204	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T10,T39,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T10,T39,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T10,T22,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T10,T40
1	0	Covered	T1,T5,T6
1	1	Covered	T10,T39,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T22,T38
0	1	Covered	T180
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T22,T38
0	1	Covered	T10,T168,T123
1	0	Covered	T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T22,T38
1	-	Covered	T10,T168,T123

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T39,T22
DetectSt	168	Covered	T10,T22,T38
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T10,T22,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T22,T38
DebounceSt->IdleSt	163	Covered	T39,T108,T207
DetectSt->IdleSt	186	Covered	T180
DetectSt->StableSt	191	Covered	T10,T22,T38
IdleSt->DebounceSt	148	Covered	T10,T39,T22
StableSt->IdleSt	206	Covered	T10,T41,T168

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T39,T22
0	1	Covered	T10,T39,T22
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T22,T38
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T39,T22
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T108
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T22,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T207
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T39,T22
DetectSt	-	-	-	-	1	-	-	Covered	T180
DetectSt	-	-	-	-	0	1	-	Covered	T10,T22,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T168,T123
StableSt	-	-	-	-	-	-	0	Covered	T10,T22,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7903577	87	0	0
CntIncr_A	7903577	180004	0	0
CntNoWrap_A	7903577	7251000	0	0
DetectStDropOut_A	7903577	1	0	0
DetectedOut_A	7903577	62392	0	0
DetectedPulseOut_A	7903577	41	0	0
DisabledIdleSt_A	7903577	6434212	0	0
DisabledNoDetection_A	7903577	6436442	0	0
EnterDebounceSt_A	7903577	45	0	0
EnterDetectSt_A	7903577	42	0	0
EnterStableSt_A	7903577	41	0	0
PulseIsPulse_A	7903577	41	0	0
StayInStableSt	7903577	62329	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7903577	6775	0	0
gen_low_level_sva.LowLevelEvent_A	7903577	7253370	0	0
gen_not_sticky_sva.StableStDropOut_A	7903577	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	87	0	0
T10	124227	2	0	0
T11	12474	0	0	0
T12	22676	0	0	0
T22	0	2	0	0
T27	766	0	0	0
T30	20486	0	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	4	0	0
T43	20986	0	0	0
T49	624	0	0	0
T67	422	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T81	0	2	0	0
T168	0	2	0	0
T171	0	2	0	0
T180	0	2	0	0
T204	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	180004	0	0
T10	124227	27196	0	0
T11	12474	0	0	0
T12	22676	0	0	0
T22	0	26	0	0
T27	766	0	0	0
T30	20486	0	0	0
T38	0	54	0	0
T39	0	62	0	0
T41	0	118	0	0
T43	20986	0	0	0
T49	624	0	0	0
T67	422	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T81	0	16	0	0
T168	0	44168	0	0
T171	0	64	0	0
T180	0	34	0	0
T204	0	61	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7251000	0	0
T1	25831	25363	0	0
T2	1099	698	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	4666	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	4966	0	0
T18	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	1	0	0
T121	28176	0	0	0
T180	770	1	0	0
T245	462	0	0	0
T246	435	0	0	0
T247	986	0	0	0
T248	405	0	0	0
T249	19800	0	0	0
T250	422	0	0	0
T251	447	0	0	0
T252	13117	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	62392	0	0
T10	124227	43	0	0
T11	12474	0	0	0
T12	22676	0	0	0
T22	0	54	0	0
T27	766	0	0	0
T30	20486	0	0	0
T38	0	213	0	0
T41	0	180	0	0
T43	20986	0	0	0
T49	624	0	0	0
T67	422	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T81	0	45	0	0
T113	0	43	0	0
T123	0	299	0	0
T168	0	11315	0	0
T171	0	439	0	0
T204	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	41	0	0
T10	124227	1	0	0
T11	12474	0	0	0
T12	22676	0	0	0
T22	0	1	0	0
T27	766	0	0	0
T30	20486	0	0	0
T38	0	1	0	0
T41	0	2	0	0
T43	20986	0	0	0
T49	624	0	0	0
T67	422	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T81	0	1	0	0
T113	0	1	0	0
T123	0	2	0	0
T168	0	1	0	0
T171	0	1	0	0
T204	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6434212	0	0
T1	25831	25363	0	0
T2	1099	698	0	0
T5	4417	649	0	0
T6	651	250	0	0
T13	5067	4666	0	0
T14	427	26	0	0
T15	508	107	0	0
T16	502	101	0	0
T17	5367	4966	0	0
T18	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6436442	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	45	0	0
T10	124227	1	0	0
T11	12474	0	0	0
T12	22676	0	0	0
T22	0	1	0	0
T27	766	0	0	0
T30	20486	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	2	0	0
T43	20986	0	0	0
T49	624	0	0	0
T67	422	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T81	0	1	0	0
T168	0	1	0	0
T171	0	1	0	0
T180	0	1	0	0
T204	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	42	0	0
T10	124227	1	0	0
T11	12474	0	0	0
T12	22676	0	0	0
T22	0	1	0	0
T27	766	0	0	0
T30	20486	0	0	0
T38	0	1	0	0
T41	0	2	0	0
T43	20986	0	0	0
T49	624	0	0	0
T67	422	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T81	0	1	0	0
T123	0	2	0	0
T168	0	1	0	0
T171	0	1	0	0
T180	0	1	0	0
T204	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	41	0	0
T10	124227	1	0	0
T11	12474	0	0	0
T12	22676	0	0	0
T22	0	1	0	0
T27	766	0	0	0
T30	20486	0	0	0
T38	0	1	0	0
T41	0	2	0	0
T43	20986	0	0	0
T49	624	0	0	0
T67	422	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T81	0	1	0	0
T113	0	1	0	0
T123	0	2	0	0
T168	0	1	0	0
T171	0	1	0	0
T204	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	41	0	0
T10	124227	1	0	0
T11	12474	0	0	0
T12	22676	0	0	0
T22	0	1	0	0
T27	766	0	0	0
T30	20486	0	0	0
T38	0	1	0	0
T41	0	2	0	0
T43	20986	0	0	0
T49	624	0	0	0
T67	422	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T81	0	1	0	0
T113	0	1	0	0
T123	0	2	0	0
T168	0	1	0	0
T171	0	1	0	0
T204	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	62329	0	0
T10	124227	42	0	0
T11	12474	0	0	0
T12	22676	0	0	0
T22	0	52	0	0
T27	766	0	0	0
T30	20486	0	0	0
T38	0	211	0	0
T41	0	176	0	0
T43	20986	0	0	0
T49	624	0	0	0
T67	422	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T81	0	43	0	0
T113	0	41	0	0
T123	0	296	0	0
T168	0	11314	0	0
T171	0	437	0	0
T204	0	38	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	6775	0	0
T1	25831	7	0	0
T2	1099	3	0	0
T5	4417	11	0	0
T6	651	2	0	0
T13	5067	8	0	0
T14	427	2	0	0
T15	508	6	0	0
T16	502	5	0	0
T17	5367	27	0	0
T18	502	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	7253370	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7903577	18	0	0
T10	124227	1	0	0
T11	12474	0	0	0
T12	22676	0	0	0
T27	766	0	0	0
T30	20486	0	0	0
T43	20986	0	0	0
T49	624	0	0	0
T67	422	0	0	0
T68	526	0	0	0
T69	409	0	0	0
T123	0	1	0	0
T126	0	1	0	0
T127	0	1	0	0
T168	0	1	0	0
T173	0	1	0	0
T183	0	1	0	0
T220	0	1	0	0
T230	0	1	0	0
T253	0	1	0	0