Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1447468969	10331	0	0
auto_block_debounce_ctl_rd_A	1447468969	1007	0	0
auto_block_out_ctl_rd_A	1447468969	1273	0	0
com_det_ctl_0_rd_A	1447468969	2856	0	0
com_det_ctl_1_rd_A	1447468969	3056	0	0
com_det_ctl_2_rd_A	1447468969	3094	0	0
com_det_ctl_3_rd_A	1447468969	3073	0	0
com_out_ctl_0_rd_A	1447468969	3472	0	0
com_out_ctl_1_rd_A	1447468969	3213	0	0
com_out_ctl_2_rd_A	1447468969	3404	0	0
com_out_ctl_3_rd_A	1447468969	3462	0	0
com_pre_det_ctl_0_rd_A	1447468969	689	0	0
com_pre_det_ctl_1_rd_A	1447468969	691	0	0
com_pre_det_ctl_2_rd_A	1447468969	634	0	0
com_pre_det_ctl_3_rd_A	1447468969	610	0	0
com_pre_sel_ctl_0_rd_A	1447468969	3594	0	0
com_pre_sel_ctl_1_rd_A	1447468969	3539	0	0
com_pre_sel_ctl_2_rd_A	1447468969	3549	0	0
com_pre_sel_ctl_3_rd_A	1447468969	3420	0	0
com_sel_ctl_0_rd_A	1447468969	3618	0	0
com_sel_ctl_1_rd_A	1447468969	3444	0	0
com_sel_ctl_2_rd_A	1447468969	3524	0	0
com_sel_ctl_3_rd_A	1447468969	3580	0	0
ec_rst_ctl_rd_A	1447468969	1766	0	0
intr_enable_rd_A	1447468969	1300	0	0
key_intr_ctl_rd_A	1447468969	2198	0	0
key_intr_debounce_ctl_rd_A	1447468969	721	0	0
key_invert_ctl_rd_A	1447468969	3517	0	0
pin_allowed_ctl_rd_A	1447468969	3733	0	0
pin_out_ctl_rd_A	1447468969	3192	0	0
pin_out_value_rd_A	1447468969	3130	0	0
regwen_rd_A	1447468969	884	0	0
ulp_ac_debounce_ctl_rd_A	1447468969	703	0	0
ulp_ctl_rd_A	1447468969	820	0	0
ulp_lid_debounce_ctl_rd_A	1447468969	853	0	0
ulp_pwrb_debounce_ctl_rd_A	1447468969	741	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	10331	0	0
T2	55248	0	0	0
T5	185520	7	0	0
T6	193079	0	0	0
T13	253372	0	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T22	0	23	0	0
T25	0	17	0	0
T28	0	10	0	0
T39	0	7	0	0
T41	0	25	0	0
T46	0	12	0	0
T48	60578	0	0	0
T81	0	8	0	0
T140	0	7	0	0
T170	0	12	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1007	0	0
T2	55248	0	0	0
T5	185520	17	0	0
T6	193079	0	0	0
T13	253372	0	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	14	0	0
T27	0	6	0	0
T28	0	51	0	0
T44	0	6	0	0
T47	0	20	0	0
T48	60578	0	0	0
T117	0	11	0	0
T118	0	18	0	0
T289	0	9	0	0
T290	0	6	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1273	0	0
T2	55248	0	0	0
T5	185520	27	0	0
T6	193079	0	0	0
T13	253372	0	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	12	0	0
T27	0	6	0	0
T28	0	30	0	0
T44	0	8	0	0
T47	0	6	0	0
T48	60578	0	0	0
T117	0	9	0	0
T118	0	12	0	0
T289	0	7	0	0
T290	0	12	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	2856	0	0
T2	55248	0	0	0
T5	185520	31	0	0
T6	193079	0	0	0
T11	0	49	0	0
T13	253372	63	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	5	0	0
T28	0	26	0	0
T36	0	26	0	0
T48	60578	0	0	0
T107	0	63	0	0
T190	0	43	0	0
T266	0	56	0	0
T291	0	58	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	3056	0	0
T2	55248	0	0	0
T5	185520	20	0	0
T6	193079	0	0	0
T11	0	47	0	0
T13	253372	85	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	15	0	0
T28	0	38	0	0
T36	0	26	0	0
T48	60578	0	0	0
T107	0	55	0	0
T190	0	54	0	0
T266	0	44	0	0
T291	0	54	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	3094	0	0
T2	55248	0	0	0
T5	185520	26	0	0
T6	193079	0	0	0
T11	0	35	0	0
T13	253372	58	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	17	0	0
T28	0	18	0	0
T36	0	42	0	0
T48	60578	0	0	0
T107	0	63	0	0
T190	0	70	0	0
T266	0	61	0	0
T291	0	69	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	3073	0	0
T2	55248	0	0	0
T5	185520	17	0	0
T6	193079	0	0	0
T11	0	48	0	0
T13	253372	47	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	19	0	0
T28	0	33	0	0
T36	0	52	0	0
T48	60578	0	0	0
T107	0	62	0	0
T190	0	74	0	0
T266	0	52	0	0
T291	0	60	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	3472	0	0
T2	55248	0	0	0
T5	185520	16	0	0
T6	193079	0	0	0
T11	0	41	0	0
T13	253372	65	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	10	0	0
T28	0	53	0	0
T36	0	25	0	0
T48	60578	0	0	0
T107	0	55	0	0
T190	0	71	0	0
T266	0	46	0	0
T291	0	76	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	3213	0	0
T2	55248	0	0	0
T5	185520	14	0	0
T6	193079	0	0	0
T11	0	23	0	0
T13	253372	57	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	6	0	0
T28	0	15	0	0
T36	0	29	0	0
T48	60578	0	0	0
T107	0	62	0	0
T190	0	88	0	0
T266	0	52	0	0
T291	0	75	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	3404	0	0
T2	55248	0	0	0
T5	185520	21	0	0
T6	193079	0	0	0
T11	0	24	0	0
T13	253372	94	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	12	0	0
T28	0	48	0	0
T36	0	17	0	0
T48	60578	0	0	0
T107	0	78	0	0
T190	0	63	0	0
T266	0	34	0	0
T291	0	77	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	3462	0	0
T2	55248	0	0	0
T5	185520	14	0	0
T6	193079	0	0	0
T11	0	37	0	0
T13	253372	72	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	5	0	0
T28	0	45	0	0
T36	0	21	0	0
T48	60578	0	0	0
T107	0	75	0	0
T190	0	57	0	0
T266	0	34	0	0
T291	0	85	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	689	0	0
T2	55248	0	0	0
T5	185520	16	0	0
T6	193079	0	0	0
T13	253372	0	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	10	0	0
T28	0	36	0	0
T34	0	62	0	0
T48	60578	0	0	0
T144	0	5	0	0
T292	0	14	0	0
T293	0	21	0	0
T294	0	28	0	0
T295	0	14	0	0
T296	0	12	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	691	0	0
T2	55248	0	0	0
T5	185520	19	0	0
T6	193079	0	0	0
T13	253372	0	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	3	0	0
T28	0	15	0	0
T34	0	104	0	0
T48	60578	0	0	0
T144	0	9	0	0
T292	0	15	0	0
T293	0	16	0	0
T294	0	9	0	0
T295	0	7	0	0
T296	0	9	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	634	0	0
T2	55248	0	0	0
T5	185520	19	0	0
T6	193079	0	0	0
T13	253372	0	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	10	0	0
T28	0	27	0	0
T34	0	94	0	0
T48	60578	0	0	0
T144	0	9	0	0
T292	0	15	0	0
T293	0	8	0	0
T294	0	9	0	0
T295	0	12	0	0
T296	0	4	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	610	0	0
T2	55248	0	0	0
T5	185520	23	0	0
T6	193079	0	0	0
T13	253372	0	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	10	0	0
T28	0	25	0	0
T34	0	39	0	0
T48	60578	0	0	0
T144	0	3	0	0
T292	0	16	0	0
T293	0	22	0	0
T294	0	10	0	0
T295	0	3	0	0
T296	0	11	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	3594	0	0
T2	55248	0	0	0
T5	185520	18	0	0
T6	193079	0	0	0
T11	0	25	0	0
T13	253372	67	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	12	0	0
T28	0	34	0	0
T36	0	61	0	0
T48	60578	0	0	0
T107	0	61	0	0
T190	0	69	0	0
T266	0	69	0	0
T291	0	73	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	3539	0	0
T2	55248	0	0	0
T5	185520	10	0	0
T6	193079	0	0	0
T11	0	43	0	0
T13	253372	66	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	3	0	0
T28	0	31	0	0
T36	0	24	0	0
T48	60578	0	0	0
T107	0	51	0	0
T190	0	61	0	0
T266	0	44	0	0
T291	0	109	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	3549	0	0
T2	55248	0	0	0
T5	185520	14	0	0
T6	193079	0	0	0
T11	0	47	0	0
T13	253372	57	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	11	0	0
T28	0	33	0	0
T36	0	27	0	0
T48	60578	0	0	0
T107	0	51	0	0
T190	0	63	0	0
T266	0	28	0	0
T291	0	81	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	3420	0	0
T2	55248	0	0	0
T5	185520	7	0	0
T6	193079	0	0	0
T11	0	32	0	0
T13	253372	70	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	4	0	0
T28	0	27	0	0
T36	0	38	0	0
T48	60578	0	0	0
T107	0	70	0	0
T190	0	47	0	0
T266	0	47	0	0
T291	0	69	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	3618	0	0
T2	55248	0	0	0
T5	185520	24	0	0
T6	193079	0	0	0
T11	0	61	0	0
T13	253372	70	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	11	0	0
T28	0	25	0	0
T36	0	36	0	0
T48	60578	0	0	0
T107	0	52	0	0
T190	0	67	0	0
T266	0	66	0	0
T291	0	89	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	3444	0	0
T2	55248	0	0	0
T5	185520	22	0	0
T6	193079	0	0	0
T11	0	30	0	0
T13	253372	77	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	9	0	0
T28	0	41	0	0
T36	0	22	0	0
T48	60578	0	0	0
T107	0	50	0	0
T190	0	59	0	0
T266	0	31	0	0
T291	0	58	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	3524	0	0
T2	55248	0	0	0
T5	185520	24	0	0
T6	193079	0	0	0
T11	0	50	0	0
T13	253372	80	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	11	0	0
T28	0	29	0	0
T36	0	29	0	0
T48	60578	0	0	0
T107	0	70	0	0
T190	0	53	0	0
T266	0	64	0	0
T291	0	48	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	3580	0	0
T2	55248	0	0	0
T5	185520	9	0	0
T6	193079	0	0	0
T11	0	23	0	0
T13	253372	79	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	16	0	0
T28	0	44	0	0
T36	0	54	0	0
T48	60578	0	0	0
T107	0	58	0	0
T190	0	75	0	0
T266	0	35	0	0
T291	0	63	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1766	0	0
T2	55248	0	0	0
T5	185520	19	0	0
T6	193079	0	0	0
T11	0	12	0	0
T13	253372	6	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	21	0	0
T28	0	47	0	0
T36	0	23	0	0
T48	60578	0	0	0
T56	0	1	0	0
T61	0	5	0	0
T107	0	54	0	0
T190	0	30	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1300	0	0
T2	55248	0	0	0
T5	185520	11	0	0
T6	193079	0	0	0
T13	253372	0	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	61	0	0
T28	0	41	0	0
T48	60578	0	0	0
T144	0	8	0	0
T219	0	23	0	0
T292	0	15	0	0
T293	0	14	0	0
T297	0	13	0	0
T298	0	28	0	0
T299	0	19	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	2198	0	0
T2	55248	0	0	0
T5	185520	25	0	0
T6	193079	0	0	0
T8	0	5	0	0
T13	253372	0	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	19	0	0
T28	0	35	0	0
T48	60578	0	0	0
T108	0	97	0	0
T123	0	5	0	0
T176	0	7	0	0
T178	0	3	0	0
T219	0	3	0	0
T292	0	18	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	721	0	0
T2	55248	0	0	0
T5	185520	8	0	0
T6	193079	0	0	0
T13	253372	0	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	13	0	0
T28	0	33	0	0
T34	0	117	0	0
T48	60578	0	0	0
T292	0	12	0	0
T293	0	19	0	0
T294	0	19	0	0
T295	0	7	0	0
T296	0	11	0	0
T300	0	2	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	3517	0	0
T2	55248	0	0	0
T5	185520	19	0	0
T6	193079	0	0	0
T13	253372	0	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T23	0	60	0	0
T25	0	157	0	0
T28	0	31	0	0
T48	60578	0	0	0
T61	0	75	0	0
T63	0	72	0	0
T275	0	73	0	0
T301	0	71	0	0
T302	0	31	0	0
T303	0	52	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	3733	0	0
T2	55248	0	0	0
T5	185520	14	0	0
T6	193079	0	0	0
T13	253372	0	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	204	0	0
T28	0	241	0	0
T48	60578	0	0	0
T61	0	136	0	0
T71	0	57	0	0
T131	0	71	0	0
T201	0	93	0	0
T304	0	77	0	0
T305	0	74	0	0
T306	0	72	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	3192	0	0
T2	55248	0	0	0
T5	185520	20	0	0
T6	193079	0	0	0
T13	253372	0	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	228	0	0
T28	0	238	0	0
T48	60578	0	0	0
T61	0	125	0	0
T71	0	81	0	0
T131	0	59	0	0
T201	0	63	0	0
T304	0	68	0	0
T305	0	70	0	0
T306	0	60	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	3130	0	0
T2	55248	0	0	0
T5	185520	19	0	0
T6	193079	0	0	0
T13	253372	0	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	202	0	0
T28	0	270	0	0
T48	60578	0	0	0
T61	0	121	0	0
T71	0	73	0	0
T131	0	62	0	0
T201	0	71	0	0
T304	0	75	0	0
T305	0	63	0	0
T306	0	87	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	884	0	0
T2	55248	0	0	0
T5	185520	15	0	0
T6	193079	0	0	0
T13	253372	0	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	13	0	0
T28	0	19	0	0
T34	0	66	0	0
T48	60578	0	0	0
T144	0	3	0	0
T292	0	11	0	0
T293	0	15	0	0
T294	0	14	0	0
T295	0	5	0	0
T296	0	16	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	703	0	0
T2	55248	5	0	0
T5	185520	18	0	0
T6	193079	0	0	0
T13	253372	0	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	16	0	0
T28	0	45	0	0
T48	60578	0	0	0
T61	0	2	0	0
T114	0	4	0	0
T123	0	1	0	0
T164	0	5	0	0
T297	0	1	0	0
T307	0	8	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	820	0	0
T2	55248	9	0	0
T5	185520	37	0	0
T6	193079	4	0	0
T13	253372	0	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	20	0	0
T28	0	34	0	0
T48	60578	0	0	0
T51	0	5	0	0
T114	0	1	0	0
T123	0	2	0	0
T164	0	1	0	0
T307	0	8	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	853	0	0
T2	55248	3	0	0
T5	185520	30	0	0
T6	193079	4	0	0
T13	253372	0	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	16	0	0
T28	0	35	0	0
T48	60578	0	0	0
T51	0	2	0	0
T61	0	1	0	0
T114	0	9	0	0
T123	0	5	0	0
T307	0	11	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	741	0	0
T2	55248	14	0	0
T5	185520	18	0	0
T6	193079	2	0	0
T13	253372	0	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	21	0	0
T28	0	32	0	0
T48	60578	0	0	0
T51	0	1	0	0
T61	0	2	0	0
T164	0	1	0	0
T292	0	14	0	0
T307	0	6	0	0