Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	89.20			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_wkup_status_cdc	96.88	100.00	87.50			100.00	100.00
tb.dut.u_reg.u_ec_rst_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_invert_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_value_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ctl_cdc	98.08	100.00	92.31			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.79	96.99	84.93			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_value_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ec_rst_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_allowed_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_invert_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_value_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
98.08	92.31

tb.dut.u_reg.u_ulp_ctl_cdc

SCORE	COND
96.88	87.50

tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T2,T4,T22
1	-	Covered	T1,T2,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	106621011	0	0
DstReqKnown_A	277465228	248607422	0	0
SrcAckBusyChk_A	2147483647	112855	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	106621011	0	0
T1	981640	32128	0	0
T2	441984	0	0	0
T5	1484160	1688	0	0
T6	1544632	0	0	0
T11	0	9601	0	0
T12	0	27122	0	0
T13	2026976	2875	0	0
T14	205456	0	0	0
T15	244176	0	0	0
T16	1928544	0	0	0
T17	1159506	1418	0	0
T18	2192355	0	0	0
T22	0	17920	0	0
T25	0	2167	0	0
T27	176220	3385	0	0
T28	1084178	16992	0	0
T29	0	5270	0	0
T30	0	5453	0	0
T31	452284	1880	0	0
T32	325934	1688	0	0
T37	1493270	6984	0	0
T41	0	35679	0	0
T43	1028316	13584	0	0
T44	0	2577	0	0
T45	0	12490	0	0
T46	0	23343	0	0
T47	0	3772	0	0
T48	60578	0	0	0
T49	605966	0	0	0
T50	401924	0	0	0
T51	169218	0	0	0
T52	405284	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	277465228	248607422	0	0
T1	878254	862682	0	0
T2	37366	23766	0	0
T5	150178	22440	0	0
T6	22134	8534	0	0
T13	172278	158678	0	0
T14	14518	918	0	0
T15	17272	3672	0	0
T16	17068	3468	0	0
T17	182478	168878	0	0
T18	17068	3468	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	112855	0	0
T1	981640	20	0	0
T2	441984	0	0	0
T5	1484160	1	0	0
T6	1544632	0	0	0
T11	0	6	0	0
T12	0	18	0	0
T13	2026976	2	0	0
T14	205456	0	0	0
T15	244176	0	0	0
T16	1928544	0	0	0
T17	1159506	2	0	0
T18	2192355	0	0	0
T22	0	41	0	0
T25	0	6	0	0
T27	176220	8	0	0
T28	1084178	10	0	0
T29	0	6	0	0
T30	0	14	0	0
T31	452284	1	0	0
T32	325934	4	0	0
T37	1493270	4	0	0
T41	0	42	0	0
T43	1028316	16	0	0
T44	0	7	0	0
T45	0	7	0	0
T46	0	16	0	0
T47	0	9	0	0
T48	60578	0	0	0
T49	605966	0	0	0
T50	401924	0	0	0
T51	169218	0	0	0
T52	405284	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4171970	4162586	0	0
T2	1878432	1875372	0	0
T5	6307680	6271844	0	0
T6	6564686	6562578	0	0
T13	8614648	8614478	0	0
T14	873188	870604	0	0
T15	1037748	1035912	0	0
T16	8196312	8193558	0	0
T17	4380356	4380118	0	0
T18	8282230	8279000	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T53,T19,T35
1	-	Covered	T1,T2,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1447468969	1037897	0	0
DstReqKnown_A	8160742	7311983	0	0
SrcAckBusyChk_A	1447468969	1089	0	0
SrcBusyKnown_A	1447468969	1445613214	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1037897	0	0
T1	122705	5216	0	0
T2	55248	434	0	0
T4	0	1492	0	0
T5	185520	0	0	0
T6	193079	0	0	0
T11	0	2913	0	0
T12	0	21510	0	0
T13	253372	0	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T30	0	1597	0	0
T32	0	496	0	0
T37	0	1906	0	0
T43	0	977	0	0
T54	0	705	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8160742	7311983	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1089	0	0
T1	122705	3	0	0
T2	55248	1	0	0
T4	0	1	0	0
T5	185520	0	0	0
T6	193079	0	0	0
T11	0	2	0	0
T12	0	14	0	0
T13	253372	0	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T30	0	4	0	0
T32	0	1	0	0
T37	0	1	0	0
T43	0	1	0	0
T54	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1445613214	0	0
T1	122705	122429	0	0
T2	55248	55158	0	0
T5	185520	184466	0	0
T6	193079	193017	0	0
T13	253372	253367	0	0
T14	25682	25606	0	0
T15	30522	30468	0	0
T16	241068	240987	0	0
T17	128834	128827	0	0
T18	243595	243500	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T13

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T13

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T13
0	0	1	Covered	T1,T5,T13
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T13
0	0	1	Covered	T1,T5,T13
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1447468969	1711312	0	0
DstReqKnown_A	8160742	7311983	0	0
SrcAckBusyChk_A	1447468969	1894	0	0
SrcBusyKnown_A	1447468969	1445613214	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1711312	0	0
T1	122705	15914	0	0
T2	55248	0	0	0
T5	185520	2923	0	0
T6	193079	0	0	0
T11	0	4583	0	0
T12	0	13426	0	0
T13	253372	1353	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	680	0	0
T18	243595	0	0	0
T55	0	61	0	0
T56	0	744	0	0
T57	0	71	0	0
T58	0	597	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8160742	7311983	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1894	0	0
T1	122705	10	0	0
T2	55248	0	0	0
T5	185520	2	0	0
T6	193079	0	0	0
T11	0	3	0	0
T12	0	9	0	0
T13	253372	1	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	1	0	0
T18	243595	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1445613214	0	0
T1	122705	122429	0	0
T2	55248	55158	0	0
T5	185520	184466	0	0
T6	193079	193017	0	0
T13	253372	253367	0	0
T14	25682	25606	0	0
T15	30522	30468	0	0
T16	241068	240987	0	0
T17	128834	128827	0	0
T18	243595	243500	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T5,T6,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T5,T6,T2
1	1	Covered	T5,T6,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T5,T6,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T2
1	1	Covered	T5,T6,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T5,T6,T2
0	0	1	Covered	T5,T6,T2
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T5,T6,T2
0	0	1	Covered	T5,T6,T2
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1447468969	897150	0	0
DstReqKnown_A	8160742	7311983	0	0
SrcAckBusyChk_A	1447468969	978	0	0
SrcBusyKnown_A	1447468969	1445613214	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	897150	0	0
T2	55248	940	0	0
T4	0	4998	0	0
T5	185520	1739	0	0
T6	193079	1850	0	0
T13	253372	0	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	730	0	0
T28	0	3297	0	0
T48	60578	0	0	0
T50	0	3395	0	0
T51	0	1585	0	0
T59	0	3430	0	0
T60	0	3918	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8160742	7311983	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	978	0	0
T2	55248	2	0	0
T4	0	3	0	0
T5	185520	1	0	0
T6	193079	1	0	0
T13	253372	0	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	2	0	0
T28	0	2	0	0
T48	60578	0	0	0
T50	0	2	0	0
T51	0	2	0	0
T59	0	2	0	0
T60	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1445613214	0	0
T1	122705	122429	0	0
T2	55248	55158	0	0
T5	185520	184466	0	0
T6	193079	193017	0	0
T13	253372	253367	0	0
T14	25682	25606	0	0
T15	30522	30468	0	0
T16	241068	240987	0	0
T17	128834	128827	0	0
T18	243595	243500	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T5,T6,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T5,T6,T2
1	1	Covered	T5,T6,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T5,T6,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T2
1	1	Covered	T5,T6,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T5,T6,T2
0	0	1	Covered	T5,T6,T2
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T5,T6,T2
0	0	1	Covered	T5,T6,T2
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1447468969	928555	0	0
DstReqKnown_A	8160742	7311983	0	0
SrcAckBusyChk_A	1447468969	1008	0	0
SrcBusyKnown_A	1447468969	1445613214	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	928555	0	0
T2	55248	920	0	0
T4	0	4992	0	0
T5	185520	1734	0	0
T6	193079	1837	0	0
T13	253372	0	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	698	0	0
T28	0	3285	0	0
T48	60578	0	0	0
T50	0	3391	0	0
T51	0	1571	0	0
T59	0	3426	0	0
T60	0	3914	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8160742	7311983	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1008	0	0
T2	55248	2	0	0
T4	0	3	0	0
T5	185520	1	0	0
T6	193079	1	0	0
T13	253372	0	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	2	0	0
T28	0	2	0	0
T48	60578	0	0	0
T50	0	2	0	0
T51	0	2	0	0
T59	0	2	0	0
T60	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1445613214	0	0
T1	122705	122429	0	0
T2	55248	55158	0	0
T5	185520	184466	0	0
T6	193079	193017	0	0
T13	253372	253367	0	0
T14	25682	25606	0	0
T15	30522	30468	0	0
T16	241068	240987	0	0
T17	128834	128827	0	0
T18	243595	243500	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T5,T6,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T5,T6,T2
1	1	Covered	T5,T6,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T5,T6,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T2
1	1	Covered	T5,T6,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T5,T6,T2
0	0	1	Covered	T5,T6,T2
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T5,T6,T2
0	0	1	Covered	T5,T6,T2
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1447468969	921696	0	0
DstReqKnown_A	8160742	7311983	0	0
SrcAckBusyChk_A	1447468969	995	0	0
SrcBusyKnown_A	1447468969	1445613214	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	921696	0	0
T2	55248	893	0	0
T4	0	4986	0	0
T5	185520	1725	0	0
T6	193079	1826	0	0
T13	253372	0	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	686	0	0
T28	0	3257	0	0
T48	60578	0	0	0
T50	0	3387	0	0
T51	0	1547	0	0
T59	0	3422	0	0
T60	0	3910	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8160742	7311983	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	995	0	0
T2	55248	2	0	0
T4	0	3	0	0
T5	185520	1	0	0
T6	193079	1	0	0
T13	253372	0	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T25	0	2	0	0
T28	0	2	0	0
T48	60578	0	0	0
T50	0	2	0	0
T51	0	2	0	0
T59	0	2	0	0
T60	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1445613214	0	0
T1	122705	122429	0	0
T2	55248	55158	0	0
T5	185520	184466	0	0
T6	193079	193017	0	0
T13	253372	253367	0	0
T14	25682	25606	0	0
T15	30522	30468	0	0
T16	241068	240987	0	0
T17	128834	128827	0	0
T18	243595	243500	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T23,T24,T25

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T23,T24,T25
1	1	Covered	T23,T24,T25

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T23,T24,T25

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T23,T24,T25
1	1	Covered	T23,T24,T25

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T23,T24,T25
0	0	1	Covered	T23,T24,T25
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T23,T24,T25
0	0	1	Covered	T23,T24,T25
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1447468969	2447191	0	0
DstReqKnown_A	8160742	7311983	0	0
SrcAckBusyChk_A	1447468969	2926	0	0
SrcBusyKnown_A	1447468969	1445613214	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	2447191	0	0
T10	445159	0	0	0
T11	617492	0	0	0
T12	997746	0	0	0
T22	0	8500	0	0
T23	229904	33359	0	0
T24	0	2308	0	0
T25	0	17490	0	0
T27	88110	0	0	0
T30	245833	0	0	0
T46	0	57820	0	0
T61	0	8034	0	0
T62	0	35005	0	0
T63	0	15751	0	0
T64	0	7707	0	0
T65	0	7352	0	0
T66	42962	0	0	0
T67	177307	0	0	0
T68	65832	0	0	0
T69	202568	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8160742	7311983	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	2926	0	0
T10	445159	0	0	0
T11	617492	0	0	0
T12	997746	0	0	0
T22	0	20	0	0
T23	229904	20	0	0
T24	0	20	0	0
T25	0	40	0	0
T27	88110	0	0	0
T30	245833	0	0	0
T46	0	40	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	0	20	0	0
T65	0	20	0	0
T66	42962	0	0	0
T67	177307	0	0	0
T68	65832	0	0	0
T69	202568	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1445613214	0	0
T1	122705	122429	0	0
T2	55248	55158	0	0
T5	185520	184466	0	0
T6	193079	193017	0	0
T13	253372	253367	0	0
T14	25682	25606	0	0
T15	30522	30468	0	0
T16	241068	240987	0	0
T17	128834	128827	0	0
T18	243595	243500	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T5,T15,T16

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T5,T15,T16
1	1	Covered	T5,T15,T16

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T5,T15,T16

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T15,T16
1	1	Covered	T5,T15,T16

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T5,T15,T16
0	0	1	Covered	T5,T15,T16
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T5,T15,T16
0	0	1	Covered	T5,T15,T16
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1447468969	5660853	0	0
DstReqKnown_A	8160742	7311983	0	0
SrcAckBusyChk_A	1447468969	6294	0	0
SrcBusyKnown_A	1447468969	1445613214	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	5660853	0	0
T2	55248	0	0	0
T5	185520	28670	0	0
T6	193079	0	0	0
T13	253372	0	0	0
T14	25682	0	0	0
T15	30522	4190	0	0
T16	241068	32267	0	0
T17	128834	0	0	0
T18	243595	36504	0	0
T23	0	1845	0	0
T26	0	3171	0	0
T48	60578	8284	0	0
T68	0	8424	0	0
T70	0	33298	0	0
T71	0	34084	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8160742	7311983	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	6294	0	0
T2	55248	0	0	0
T5	185520	20	0	0
T6	193079	0	0	0
T13	253372	0	0	0
T14	25682	0	0	0
T15	30522	20	0	0
T16	241068	20	0	0
T17	128834	0	0	0
T18	243595	20	0	0
T23	0	1	0	0
T26	0	20	0	0
T48	60578	20	0	0
T68	0	20	0	0
T70	0	20	0	0
T71	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1445613214	0	0
T1	122705	122429	0	0
T2	55248	55158	0	0
T5	185520	184466	0	0
T6	193079	193017	0	0
T13	253372	253367	0	0
T14	25682	25606	0	0
T15	30522	30468	0	0
T16	241068	240987	0	0
T17	128834	128827	0	0
T18	243595	243500	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T13

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T13

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T13
0	0	1	Covered	T1,T5,T13
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T13
0	0	1	Covered	T1,T5,T13
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1447468969	6713248	0	0
DstReqKnown_A	8160742	7311983	0	0
SrcAckBusyChk_A	1447468969	7360	0	0
SrcBusyKnown_A	1447468969	1445613214	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	6713248	0	0
T1	122705	16100	0	0
T2	55248	0	0	0
T5	185520	32056	0	0
T6	193079	0	0	0
T13	253372	1493	0	0
T14	25682	0	0	0
T15	30522	4270	0	0
T16	241068	32546	0	0
T17	128834	719	0	0
T18	243595	36785	0	0
T48	0	8548	0	0
T55	0	73	0	0
T70	0	33378	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8160742	7311983	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	7360	0	0
T1	122705	10	0	0
T2	55248	0	0	0
T5	185520	22	0	0
T6	193079	0	0	0
T13	253372	1	0	0
T14	25682	0	0	0
T15	30522	20	0	0
T16	241068	20	0	0
T17	128834	1	0	0
T18	243595	20	0	0
T48	0	20	0	0
T55	0	1	0	0
T70	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1445613214	0	0
T1	122705	122429	0	0
T2	55248	55158	0	0
T5	185520	184466	0	0
T6	193079	193017	0	0
T13	253372	253367	0	0
T14	25682	25606	0	0
T15	30522	30468	0	0
T16	241068	240987	0	0
T17	128834	128827	0	0
T18	243595	243500	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T5,T15,T16

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T5,T15,T16
1	1	Covered	T5,T15,T16

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T5,T15,T16

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T15,T16
1	1	Covered	T5,T15,T16

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T5,T15,T16
0	0	1	Covered	T5,T15,T16
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T5,T15,T16
0	0	1	Covered	T5,T15,T16
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1447468969	5577055	0	0
DstReqKnown_A	8160742	7311983	0	0
SrcAckBusyChk_A	1447468969	6161	0	0
SrcBusyKnown_A	1447468969	1445613214	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	5577055	0	0
T2	55248	0	0	0
T5	185520	28897	0	0
T6	193079	0	0	0
T13	253372	0	0	0
T14	25682	0	0	0
T15	30522	4230	0	0
T16	241068	32413	0	0
T17	128834	0	0	0
T18	243595	36641	0	0
T26	0	3211	0	0
T28	0	232935	0	0
T48	60578	8418	0	0
T68	0	8464	0	0
T70	0	33338	0	0
T71	0	34268	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8160742	7311983	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	6161	0	0
T2	55248	0	0	0
T5	185520	20	0	0
T6	193079	0	0	0
T13	253372	0	0	0
T14	25682	0	0	0
T15	30522	20	0	0
T16	241068	20	0	0
T17	128834	0	0	0
T18	243595	20	0	0
T26	0	20	0	0
T28	0	140	0	0
T48	60578	20	0	0
T68	0	20	0	0
T70	0	20	0	0
T71	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1445613214	0	0
T1	122705	122429	0	0
T2	55248	55158	0	0
T5	185520	184466	0	0
T6	193079	193017	0	0
T13	253372	253367	0	0
T14	25682	25606	0	0
T15	30522	30468	0	0
T16	241068	240987	0	0
T17	128834	128827	0	0
T18	243595	243500	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T3,T7,T8

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T3,T7,T8
1	1	Covered	T3,T7,T8

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T3,T7,T8

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T7,T8
1	1	Covered	T3,T7,T8

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T3,T7,T8
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T3,T7,T8
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1447468969	941028	0	0
DstReqKnown_A	8160742	7311983	0	0
SrcAckBusyChk_A	1447468969	1038	0	0
SrcBusyKnown_A	1447468969	1445613214	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	941028	0	0
T3	264313	1496	0	0
T4	236593	0	0	0
T7	22055	117	0	0
T8	0	1882	0	0
T9	0	1489	0	0
T10	0	414	0	0
T22	0	874	0	0
T25	0	733	0	0
T38	0	359	0	0
T39	0	1916	0	0
T40	0	240	0	0
T55	15395	0	0	0
T56	185137	0	0	0
T59	209928	0	0	0
T70	236375	0	0	0
T71	241500	0	0	0
T72	193522	0	0	0
T73	211369	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8160742	7311983	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1038	0	0
T3	264313	1	0	0
T4	236593	0	0	0
T7	22055	1	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	0	1	0	0
T22	0	2	0	0
T25	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T55	15395	0	0	0
T56	185137	0	0	0
T59	209928	0	0	0
T70	236375	0	0	0
T71	241500	0	0	0
T72	193522	0	0	0
T73	211369	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1445613214	0	0
T1	122705	122429	0	0
T2	55248	55158	0	0
T5	185520	184466	0	0
T6	193079	193017	0	0
T13	253372	253367	0	0
T14	25682	25606	0	0
T15	30522	30468	0	0
T16	241068	240987	0	0
T17	128834	128827	0	0
T18	243595	243500	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T13

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T13

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T13
0	0	1	Covered	T1,T5,T13
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T13
0	0	1	Covered	T1,T5,T13
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1447468969	1710281	0	0
DstReqKnown_A	8160742	7311983	0	0
SrcAckBusyChk_A	1447468969	1905	0	0
SrcBusyKnown_A	1447468969	1445613214	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1710281	0	0
T1	122705	15894	0	0
T2	55248	0	0	0
T3	0	1494	0	0
T5	185520	1662	0	0
T6	193079	0	0	0
T7	0	115	0	0
T8	0	1869	0	0
T9	0	1484	0	0
T10	0	409	0	0
T11	0	4551	0	0
T13	253372	1344	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	678	0	0
T18	243595	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8160742	7311983	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1905	0	0
T1	122705	10	0	0
T2	55248	0	0	0
T3	0	1	0	0
T5	185520	1	0	0
T6	193079	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	0	1	0	0
T11	0	3	0	0
T13	253372	1	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	1	0	0
T18	243595	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1445613214	0	0
T1	122705	122429	0	0
T2	55248	55158	0	0
T5	185520	184466	0	0
T6	193079	193017	0	0
T13	253372	253367	0	0
T14	25682	25606	0	0
T15	30522	30468	0	0
T16	241068	240987	0	0
T17	128834	128827	0	0
T18	243595	243500	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T27,T28,T29

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T27,T28,T29
1	1	Covered	T27,T28,T29

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T27,T28,T29

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T27,T28,T29
1	1	Covered	T27,T28,T29

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T27,T28,T29
0	0	1	Covered	T27,T28,T29
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T27,T28,T29
0	0	1	Covered	T27,T28,T29
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1447468969	1194905	0	0
DstReqKnown_A	8160742	7311983	0	0
SrcAckBusyChk_A	1447468969	1305	0	0
SrcBusyKnown_A	1447468969	1445613214	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1194905	0	0
T22	0	10850	0	0
T25	0	1101	0	0
T27	88110	2163	0	0
T28	542089	8536	0	0
T29	0	2638	0	0
T31	226142	0	0	0
T32	162967	0	0	0
T37	746635	0	0	0
T41	0	22994	0	0
T43	514158	0	0	0
T44	0	1541	0	0
T45	0	6998	0	0
T46	0	14341	0	0
T47	0	2493	0	0
T49	302983	0	0	0
T50	200962	0	0	0
T51	84609	0	0	0
T52	202642	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8160742	7311983	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1305	0	0
T22	0	25	0	0
T25	0	3	0	0
T27	88110	5	0	0
T28	542089	5	0	0
T29	0	3	0	0
T31	226142	0	0	0
T32	162967	0	0	0
T37	746635	0	0	0
T41	0	27	0	0
T43	514158	0	0	0
T44	0	4	0	0
T45	0	4	0	0
T46	0	10	0	0
T47	0	6	0	0
T49	302983	0	0	0
T50	200962	0	0	0
T51	84609	0	0	0
T52	202642	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1445613214	0	0
T1	122705	122429	0	0
T2	55248	55158	0	0
T5	185520	184466	0	0
T6	193079	193017	0	0
T13	253372	253367	0	0
T14	25682	25606	0	0
T15	30522	30468	0	0
T16	241068	240987	0	0
T17	128834	128827	0	0
T18	243595	243500	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T27,T28,T29

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T27,T28,T29
1	1	Covered	T27,T28,T29

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T27,T28,T29

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T27,T28,T29
1	1	Covered	T27,T28,T29

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T27,T28,T29
0	0	1	Covered	T27,T28,T29
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T27,T28,T29
0	0	1	Covered	T27,T28,T29
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1447468969	1045505	0	0
DstReqKnown_A	8160742	7311983	0	0
SrcAckBusyChk_A	1447468969	1156	0	0
SrcBusyKnown_A	1447468969	1445613214	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1045505	0	0
T22	0	7070	0	0
T25	0	1066	0	0
T27	88110	1222	0	0
T28	542089	5196	0	0
T29	0	2632	0	0
T31	226142	0	0	0
T32	162967	0	0	0
T37	746635	0	0	0
T41	0	12685	0	0
T43	514158	0	0	0
T44	0	1036	0	0
T45	0	5492	0	0
T46	0	9002	0	0
T47	0	1279	0	0
T49	302983	0	0	0
T50	200962	0	0	0
T51	84609	0	0	0
T52	202642	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8160742	7311983	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1156	0	0
T22	0	16	0	0
T25	0	3	0	0
T27	88110	3	0	0
T28	542089	3	0	0
T29	0	3	0	0
T31	226142	0	0	0
T32	162967	0	0	0
T37	746635	0	0	0
T41	0	15	0	0
T43	514158	0	0	0
T44	0	3	0	0
T45	0	3	0	0
T46	0	6	0	0
T47	0	3	0	0
T49	302983	0	0	0
T50	200962	0	0	0
T51	84609	0	0	0
T52	202642	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1445613214	0	0
T1	122705	122429	0	0
T2	55248	55158	0	0
T5	185520	184466	0	0
T6	193079	193017	0	0
T13	253372	253367	0	0
T14	25682	25606	0	0
T15	30522	30468	0	0
T16	241068	240987	0	0
T17	128834	128827	0	0
T18	243595	243500	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T17,T30,T31

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T17,T30,T31
1	1	Covered	T17,T30,T31

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T17,T30,T31

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T17,T30,T31
1	1	Covered	T17,T30,T31

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T17,T30,T31
0	0	1	Covered	T17,T30,T31
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T17,T30,T31
0	0	1	Covered	T17,T30,T31
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1447468969	7155294	0	0
DstReqKnown_A	8160742	7311983	0	0
SrcAckBusyChk_A	1447468969	7181	0	0
SrcBusyKnown_A	1447468969	1445613214	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	7155294	0	0
T3	264313	0	0	0
T4	236593	0	0	0
T7	22055	0	0	0
T17	128834	41681	0	0
T18	243595	0	0	0
T30	0	31967	0	0
T31	0	1914	0	0
T32	0	39189	0	0
T36	0	7531	0	0
T37	0	154018	0	0
T42	0	97815	0	0
T48	60578	0	0	0
T54	0	23445	0	0
T59	209928	0	0	0
T70	236375	0	0	0
T72	193522	0	0	0
T73	211369	0	0	0
T74	0	17937	0	0
T75	0	89073	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8160742	7311983	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	7181	0	0
T3	264313	0	0	0
T4	236593	0	0	0
T7	22055	0	0	0
T17	128834	51	0	0
T18	243595	0	0	0
T30	0	78	0	0
T31	0	1	0	0
T32	0	89	0	0
T36	0	81	0	0
T37	0	93	0	0
T42	0	59	0	0
T48	60578	0	0	0
T54	0	56	0	0
T59	209928	0	0	0
T70	236375	0	0	0
T72	193522	0	0	0
T73	211369	0	0	0
T74	0	51	0	0
T75	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1445613214	0	0
T1	122705	122429	0	0
T2	55248	55158	0	0
T5	185520	184466	0	0
T6	193079	193017	0	0
T13	253372	253367	0	0
T14	25682	25606	0	0
T15	30522	30468	0	0
T16	241068	240987	0	0
T17	128834	128827	0	0
T18	243595	243500	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T17,T30,T32

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T17,T30,T32
1	1	Covered	T17,T30,T32

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T17,T30,T32

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T17,T30,T32
1	1	Covered	T17,T30,T32

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T17,T30,T32
0	0	1	Covered	T17,T30,T32
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T17,T30,T32
0	0	1	Covered	T17,T30,T32
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1447468969	6879398	0	0
DstReqKnown_A	8160742	7311983	0	0
SrcAckBusyChk_A	1447468969	7073	0	0
SrcBusyKnown_A	1447468969	1445613214	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	6879398	0	0
T3	264313	0	0	0
T4	236593	0	0	0
T7	22055	0	0	0
T17	128834	41471	0	0
T18	243595	0	0	0
T30	0	25115	0	0
T32	0	37222	0	0
T36	0	5238	0	0
T37	0	109686	0	0
T42	0	128912	0	0
T48	60578	0	0	0
T54	0	22784	0	0
T59	209928	0	0	0
T70	236375	0	0	0
T72	193522	0	0	0
T73	211369	0	0	0
T74	0	17272	0	0
T75	0	88289	0	0
T76	0	151872	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8160742	7311983	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	7073	0	0
T3	264313	0	0	0
T4	236593	0	0	0
T7	22055	0	0	0
T17	128834	51	0	0
T18	243595	0	0	0
T30	0	64	0	0
T32	0	85	0	0
T36	0	56	0	0
T37	0	67	0	0
T42	0	77	0	0
T48	60578	0	0	0
T54	0	56	0	0
T59	209928	0	0	0
T70	236375	0	0	0
T72	193522	0	0	0
T73	211369	0	0	0
T74	0	51	0	0
T75	0	51	0	0
T76	0	92	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1445613214	0	0
T1	122705	122429	0	0
T2	55248	55158	0	0
T5	185520	184466	0	0
T6	193079	193017	0	0
T13	253372	253367	0	0
T14	25682	25606	0	0
T15	30522	30468	0	0
T16	241068	240987	0	0
T17	128834	128827	0	0
T18	243595	243500	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T17,T30,T32

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T17,T30,T32
1	1	Covered	T17,T30,T32

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T17,T30,T32

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T17,T30,T32
1	1	Covered	T17,T30,T32

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T17,T30,T32
0	0	1	Covered	T17,T30,T32
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T17,T30,T32
0	0	1	Covered	T17,T30,T32
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1447468969	6825546	0	0
DstReqKnown_A	8160742	7311983	0	0
SrcAckBusyChk_A	1447468969	6982	0	0
SrcBusyKnown_A	1447468969	1445613214	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	6825546	0	0
T3	264313	0	0	0
T4	236593	0	0	0
T7	22055	0	0	0
T17	128834	41261	0	0
T18	243595	0	0	0
T30	0	27543	0	0
T32	0	25357	0	0
T36	0	7512	0	0
T37	0	102818	0	0
T42	0	117375	0	0
T48	60578	0	0	0
T54	0	19933	0	0
T59	209928	0	0	0
T70	236375	0	0	0
T72	193522	0	0	0
T73	211369	0	0	0
T74	0	16513	0	0
T75	0	87581	0	0
T76	0	116262	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8160742	7311983	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	6982	0	0
T3	264313	0	0	0
T4	236593	0	0	0
T7	22055	0	0	0
T17	128834	51	0	0
T18	243595	0	0	0
T30	0	72	0	0
T32	0	60	0	0
T36	0	83	0	0
T37	0	63	0	0
T42	0	70	0	0
T48	60578	0	0	0
T54	0	51	0	0
T59	209928	0	0	0
T70	236375	0	0	0
T72	193522	0	0	0
T73	211369	0	0	0
T74	0	51	0	0
T75	0	51	0	0
T76	0	71	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1445613214	0	0
T1	122705	122429	0	0
T2	55248	55158	0	0
T5	185520	184466	0	0
T6	193079	193017	0	0
T13	253372	253367	0	0
T14	25682	25606	0	0
T15	30522	30468	0	0
T16	241068	240987	0	0
T17	128834	128827	0	0
T18	243595	243500	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T17,T30,T32

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T17,T30,T32
1	1	Covered	T17,T30,T32

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T17,T30,T32

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T17,T30,T32
1	1	Covered	T17,T30,T32

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T17,T30,T32
0	0	1	Covered	T17,T30,T32
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T17,T30,T32
0	0	1	Covered	T17,T30,T32
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1447468969	6950566	0	0
DstReqKnown_A	8160742	7311983	0	0
SrcAckBusyChk_A	1447468969	7124	0	0
SrcBusyKnown_A	1447468969	1445613214	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	6950566	0	0
T3	264313	0	0	0
T4	236593	0	0	0
T7	22055	0	0	0
T17	128834	41051	0	0
T18	243595	0	0	0
T30	0	25932	0	0
T32	0	35824	0	0
T36	0	8053	0	0
T37	0	150848	0	0
T42	0	137148	0	0
T48	60578	0	0	0
T54	0	21240	0	0
T59	209928	0	0	0
T70	236375	0	0	0
T72	193522	0	0	0
T73	211369	0	0	0
T74	0	15818	0	0
T75	0	86888	0	0
T76	0	119978	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8160742	7311983	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	7124	0	0
T3	264313	0	0	0
T4	236593	0	0	0
T7	22055	0	0	0
T17	128834	51	0	0
T18	243595	0	0	0
T30	0	70	0	0
T32	0	83	0	0
T36	0	88	0	0
T37	0	93	0	0
T42	0	82	0	0
T48	60578	0	0	0
T54	0	56	0	0
T59	209928	0	0	0
T70	236375	0	0	0
T72	193522	0	0	0
T73	211369	0	0	0
T74	0	51	0	0
T75	0	51	0	0
T76	0	74	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1445613214	0	0
T1	122705	122429	0	0
T2	55248	55158	0	0
T5	185520	184466	0	0
T6	193079	193017	0	0
T13	253372	253367	0	0
T14	25682	25606	0	0
T15	30522	30468	0	0
T16	241068	240987	0	0
T17	128834	128827	0	0
T18	243595	243500	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T17,T30,T31

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T17,T30,T31
1	1	Covered	T17,T30,T31

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T17,T30,T31

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T17,T30,T31
1	1	Covered	T17,T30,T31

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T17,T30,T31
0	0	1	Covered	T17,T30,T31
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T17,T30,T31
0	0	1	Covered	T17,T30,T31
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1447468969	1119288	0	0
DstReqKnown_A	8160742	7311983	0	0
SrcAckBusyChk_A	1447468969	1208	0	0
SrcBusyKnown_A	1447468969	1445613214	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1119288	0	0
T3	264313	0	0	0
T4	236593	0	0	0
T7	22055	0	0	0
T17	128834	718	0	0
T18	243595	0	0	0
T30	0	2922	0	0
T31	0	1902	0	0
T32	0	1744	0	0
T36	0	476	0	0
T37	0	7145	0	0
T42	0	7345	0	0
T48	60578	0	0	0
T54	0	359	0	0
T59	209928	0	0	0
T70	236375	0	0	0
T72	193522	0	0	0
T73	211369	0	0	0
T74	0	307	0	0
T75	0	1978	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8160742	7311983	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1208	0	0
T3	264313	0	0	0
T4	236593	0	0	0
T7	22055	0	0	0
T17	128834	1	0	0
T18	243595	0	0	0
T30	0	7	0	0
T31	0	1	0	0
T32	0	4	0	0
T36	0	5	0	0
T37	0	4	0	0
T42	0	4	0	0
T48	60578	0	0	0
T54	0	1	0	0
T59	209928	0	0	0
T70	236375	0	0	0
T72	193522	0	0	0
T73	211369	0	0	0
T74	0	1	0	0
T75	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1445613214	0	0
T1	122705	122429	0	0
T2	55248	55158	0	0
T5	185520	184466	0	0
T6	193079	193017	0	0
T13	253372	253367	0	0
T14	25682	25606	0	0
T15	30522	30468	0	0
T16	241068	240987	0	0
T17	128834	128827	0	0
T18	243595	243500	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T17,T30,T32

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T17,T30,T32
1	1	Covered	T17,T30,T32

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T17,T30,T32

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T17,T30,T32
1	1	Covered	T17,T30,T32

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T17,T30,T32
0	0	1	Covered	T17,T30,T32
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T17,T30,T32
0	0	1	Covered	T17,T30,T32
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1447468969	1114041	0	0
DstReqKnown_A	8160742	7311983	0	0
SrcAckBusyChk_A	1447468969	1219	0	0
SrcBusyKnown_A	1447468969	1445613214	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1114041	0	0
T3	264313	0	0	0
T4	236593	0	0	0
T7	22055	0	0	0
T17	128834	708	0	0
T18	243595	0	0	0
T30	0	2710	0	0
T32	0	1704	0	0
T36	0	483	0	0
T37	0	7027	0	0
T42	0	7305	0	0
T48	60578	0	0	0
T54	0	329	0	0
T59	209928	0	0	0
T70	236375	0	0	0
T72	193522	0	0	0
T73	211369	0	0	0
T74	0	274	0	0
T75	0	1928	0	0
T76	0	13082	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8160742	7311983	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1219	0	0
T3	264313	0	0	0
T4	236593	0	0	0
T7	22055	0	0	0
T17	128834	1	0	0
T18	243595	0	0	0
T30	0	7	0	0
T32	0	4	0	0
T36	0	5	0	0
T37	0	4	0	0
T42	0	4	0	0
T48	60578	0	0	0
T54	0	1	0	0
T59	209928	0	0	0
T70	236375	0	0	0
T72	193522	0	0	0
T73	211369	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1445613214	0	0
T1	122705	122429	0	0
T2	55248	55158	0	0
T5	185520	184466	0	0
T6	193079	193017	0	0
T13	253372	253367	0	0
T14	25682	25606	0	0
T15	30522	30468	0	0
T16	241068	240987	0	0
T17	128834	128827	0	0
T18	243595	243500	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T17,T30,T32

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T17,T30,T32
1	1	Covered	T17,T30,T32

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T17,T30,T32

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T17,T30,T32
1	1	Covered	T17,T30,T32

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T17,T30,T32
0	0	1	Covered	T17,T30,T32
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T17,T30,T32
0	0	1	Covered	T17,T30,T32
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1447468969	1135946	0	0
DstReqKnown_A	8160742	7311983	0	0
SrcAckBusyChk_A	1447468969	1229	0	0
SrcBusyKnown_A	1447468969	1445613214	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1135946	0	0
T3	264313	0	0	0
T4	236593	0	0	0
T7	22055	0	0	0
T17	128834	698	0	0
T18	243595	0	0	0
T30	0	2443	0	0
T32	0	1664	0	0
T36	0	488	0	0
T37	0	6904	0	0
T42	0	7265	0	0
T48	60578	0	0	0
T54	0	286	0	0
T59	209928	0	0	0
T70	236375	0	0	0
T72	193522	0	0	0
T73	211369	0	0	0
T74	0	248	0	0
T75	0	1893	0	0
T76	0	12771	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8160742	7311983	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1229	0	0
T3	264313	0	0	0
T4	236593	0	0	0
T7	22055	0	0	0
T17	128834	1	0	0
T18	243595	0	0	0
T30	0	7	0	0
T32	0	4	0	0
T36	0	5	0	0
T37	0	4	0	0
T42	0	4	0	0
T48	60578	0	0	0
T54	0	1	0	0
T59	209928	0	0	0
T70	236375	0	0	0
T72	193522	0	0	0
T73	211369	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1445613214	0	0
T1	122705	122429	0	0
T2	55248	55158	0	0
T5	185520	184466	0	0
T6	193079	193017	0	0
T13	253372	253367	0	0
T14	25682	25606	0	0
T15	30522	30468	0	0
T16	241068	240987	0	0
T17	128834	128827	0	0
T18	243595	243500	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T17,T30,T32

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T17,T30,T32
1	1	Covered	T17,T30,T32

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T17,T30,T32

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T17,T30,T32
1	1	Covered	T17,T30,T32

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T17,T30,T32
0	0	1	Covered	T17,T30,T32
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T17,T30,T32
0	0	1	Covered	T17,T30,T32
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1447468969	1078797	0	0
DstReqKnown_A	8160742	7311983	0	0
SrcAckBusyChk_A	1447468969	1197	0	0
SrcBusyKnown_A	1447468969	1445613214	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1078797	0	0
T3	264313	0	0	0
T4	236593	0	0	0
T7	22055	0	0	0
T17	128834	688	0	0
T18	243595	0	0	0
T30	0	2667	0	0
T32	0	1624	0	0
T36	0	460	0	0
T37	0	6788	0	0
T42	0	7225	0	0
T48	60578	0	0	0
T54	0	255	0	0
T59	209928	0	0	0
T70	236375	0	0	0
T72	193522	0	0	0
T73	211369	0	0	0
T74	0	316	0	0
T75	0	1853	0	0
T76	0	12521	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8160742	7311983	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1197	0	0
T3	264313	0	0	0
T4	236593	0	0	0
T7	22055	0	0	0
T17	128834	1	0	0
T18	243595	0	0	0
T30	0	7	0	0
T32	0	4	0	0
T36	0	5	0	0
T37	0	4	0	0
T42	0	4	0	0
T48	60578	0	0	0
T54	0	1	0	0
T59	209928	0	0	0
T70	236375	0	0	0
T72	193522	0	0	0
T73	211369	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1445613214	0	0
T1	122705	122429	0	0
T2	55248	55158	0	0
T5	185520	184466	0	0
T6	193079	193017	0	0
T13	253372	253367	0	0
T14	25682	25606	0	0
T15	30522	30468	0	0
T16	241068	240987	0	0
T17	128834	128827	0	0
T18	243595	243500	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T13

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T13

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T13
0	0	1	Covered	T1,T5,T13
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T13
0	0	1	Covered	T1,T5,T13
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1447468969	7742931	0	0
DstReqKnown_A	8160742	7311983	0	0
SrcAckBusyChk_A	1447468969	7793	0	0
SrcBusyKnown_A	1447468969	1445613214	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	7742931	0	0
T1	122705	16154	0	0
T2	55248	0	0	0
T5	185520	1699	0	0
T6	193079	0	0	0
T11	0	4944	0	0
T12	0	13642	0	0
T13	253372	1490	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	41777	0	0
T18	243595	0	0	0
T28	0	3279	0	0
T30	0	32245	0	0
T31	0	1890	0	0
T43	0	6864	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8160742	7311983	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	7793	0	0
T1	122705	10	0	0
T2	55248	0	0	0
T5	185520	1	0	0
T6	193079	0	0	0
T11	0	3	0	0
T12	0	9	0	0
T13	253372	1	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	51	0	0
T18	243595	0	0	0
T28	0	2	0	0
T30	0	78	0	0
T31	0	1	0	0
T43	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1445613214	0	0
T1	122705	122429	0	0
T2	55248	55158	0	0
T5	185520	184466	0	0
T6	193079	193017	0	0
T13	253372	253367	0	0
T14	25682	25606	0	0
T15	30522	30468	0	0
T16	241068	240987	0	0
T17	128834	128827	0	0
T18	243595	243500	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T13,T17

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T13,T17
1	1	Covered	T1,T13,T17

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T13,T17

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T13,T17
1	1	Covered	T1,T13,T17

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T13,T17
0	0	1	Covered	T1,T13,T17
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T13,T17
0	0	1	Covered	T1,T13,T17
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1447468969	7408889	0	0
DstReqKnown_A	8160742	7311983	0	0
SrcAckBusyChk_A	1447468969	7631	0	0
SrcBusyKnown_A	1447468969	1445613214	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	7408889	0	0
T1	122705	16134	0	0
T2	55248	0	0	0
T5	185520	0	0	0
T6	193079	0	0	0
T11	0	4925	0	0
T12	0	13624	0	0
T13	253372	1483	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	41567	0	0
T18	243595	0	0	0
T30	0	25390	0	0
T32	0	37368	0	0
T37	0	110068	0	0
T43	0	6848	0	0
T54	0	23177	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8160742	7311983	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	7631	0	0
T1	122705	10	0	0
T2	55248	0	0	0
T5	185520	0	0	0
T6	193079	0	0	0
T11	0	3	0	0
T12	0	9	0	0
T13	253372	1	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	51	0	0
T18	243595	0	0	0
T30	0	64	0	0
T32	0	85	0	0
T37	0	67	0	0
T43	0	8	0	0
T54	0	56	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1445613214	0	0
T1	122705	122429	0	0
T2	55248	55158	0	0
T5	185520	184466	0	0
T6	193079	193017	0	0
T13	253372	253367	0	0
T14	25682	25606	0	0
T15	30522	30468	0	0
T16	241068	240987	0	0
T17	128834	128827	0	0
T18	243595	243500	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T13,T17

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T13,T17
1	1	Covered	T1,T13,T17

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T13,T17

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T13,T17
1	1	Covered	T1,T13,T17

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T13,T17
0	0	1	Covered	T1,T13,T17
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T13,T17
0	0	1	Covered	T1,T13,T17
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1447468969	7385372	0	0
DstReqKnown_A	8160742	7311983	0	0
SrcAckBusyChk_A	1447468969	7536	0	0
SrcBusyKnown_A	1447468969	1445613214	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	7385372	0	0
T1	122705	16114	0	0
T2	55248	0	0	0
T5	185520	0	0	0
T6	193079	0	0	0
T11	0	4886	0	0
T12	0	13606	0	0
T13	253372	1480	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	41357	0	0
T18	243595	0	0	0
T30	0	27857	0	0
T32	0	25453	0	0
T37	0	103152	0	0
T43	0	6832	0	0
T54	0	20257	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8160742	7311983	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	7536	0	0
T1	122705	10	0	0
T2	55248	0	0	0
T5	185520	0	0	0
T6	193079	0	0	0
T11	0	3	0	0
T12	0	9	0	0
T13	253372	1	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	51	0	0
T18	243595	0	0	0
T30	0	72	0	0
T32	0	60	0	0
T37	0	63	0	0
T43	0	8	0	0
T54	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1445613214	0	0
T1	122705	122429	0	0
T2	55248	55158	0	0
T5	185520	184466	0	0
T6	193079	193017	0	0
T13	253372	253367	0	0
T14	25682	25606	0	0
T15	30522	30468	0	0
T16	241068	240987	0	0
T17	128834	128827	0	0
T18	243595	243500	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T13,T17

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T13,T17
1	1	Covered	T1,T13,T17

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T13,T17

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T13,T17
1	1	Covered	T1,T13,T17

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T13,T17
0	0	1	Covered	T1,T13,T17
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T13,T17
0	0	1	Covered	T1,T13,T17
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1447468969	7460736	0	0
DstReqKnown_A	8160742	7311983	0	0
SrcAckBusyChk_A	1447468969	7635	0	0
SrcBusyKnown_A	1447468969	1445613214	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	7460736	0	0
T1	122705	16094	0	0
T2	55248	0	0	0
T5	185520	0	0	0
T6	193079	0	0	0
T11	0	4854	0	0
T12	0	13588	0	0
T13	253372	1462	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	41147	0	0
T18	243595	0	0	0
T30	0	26514	0	0
T32	0	35966	0	0
T37	0	151403	0	0
T43	0	6816	0	0
T54	0	21730	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8160742	7311983	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	7635	0	0
T1	122705	10	0	0
T2	55248	0	0	0
T5	185520	0	0	0
T6	193079	0	0	0
T11	0	3	0	0
T12	0	9	0	0
T13	253372	1	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	51	0	0
T18	243595	0	0	0
T30	0	70	0	0
T32	0	83	0	0
T37	0	93	0	0
T43	0	8	0	0
T54	0	56	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1445613214	0	0
T1	122705	122429	0	0
T2	55248	55158	0	0
T5	185520	184466	0	0
T6	193079	193017	0	0
T13	253372	253367	0	0
T14	25682	25606	0	0
T15	30522	30468	0	0
T16	241068	240987	0	0
T17	128834	128827	0	0
T18	243595	243500	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T13

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T13

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T13
0	0	1	Covered	T1,T5,T13
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T13
0	0	1	Covered	T1,T5,T13
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1447468969	1666911	0	0
DstReqKnown_A	8160742	7311983	0	0
SrcAckBusyChk_A	1447468969	1804	0	0
SrcBusyKnown_A	1447468969	1445613214	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1666911	0	0
T1	122705	16074	0	0
T2	55248	0	0	0
T5	185520	1688	0	0
T6	193079	0	0	0
T11	0	4813	0	0
T12	0	13570	0	0
T13	253372	1443	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	714	0	0
T18	243595	0	0	0
T28	0	3260	0	0
T30	0	2841	0	0
T31	0	1880	0	0
T43	0	6800	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8160742	7311983	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1804	0	0
T1	122705	10	0	0
T2	55248	0	0	0
T5	185520	1	0	0
T6	193079	0	0	0
T11	0	3	0	0
T12	0	9	0	0
T13	253372	1	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	1	0	0
T18	243595	0	0	0
T28	0	2	0	0
T30	0	7	0	0
T31	0	1	0	0
T43	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1445613214	0	0
T1	122705	122429	0	0
T2	55248	55158	0	0
T5	185520	184466	0	0
T6	193079	193017	0	0
T13	253372	253367	0	0
T14	25682	25606	0	0
T15	30522	30468	0	0
T16	241068	240987	0	0
T17	128834	128827	0	0
T18	243595	243500	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T13,T17

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T13,T17
1	1	Covered	T1,T13,T17

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T13,T17

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T13,T17
1	1	Covered	T1,T13,T17

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T13,T17
0	0	1	Covered	T1,T13,T17
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T13,T17
0	0	1	Covered	T1,T13,T17
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1447468969	1582088	0	0
DstReqKnown_A	8160742	7311983	0	0
SrcAckBusyChk_A	1447468969	1751	0	0
SrcBusyKnown_A	1447468969	1445613214	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1582088	0	0
T1	122705	16054	0	0
T2	55248	0	0	0
T5	185520	0	0	0
T6	193079	0	0	0
T11	0	4788	0	0
T12	0	13552	0	0
T13	253372	1432	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	704	0	0
T18	243595	0	0	0
T30	0	2612	0	0
T32	0	1688	0	0
T37	0	6984	0	0
T43	0	6784	0	0
T54	0	314	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8160742	7311983	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1751	0	0
T1	122705	10	0	0
T2	55248	0	0	0
T5	185520	0	0	0
T6	193079	0	0	0
T11	0	3	0	0
T12	0	9	0	0
T13	253372	1	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	1	0	0
T18	243595	0	0	0
T30	0	7	0	0
T32	0	4	0	0
T37	0	4	0	0
T43	0	8	0	0
T54	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1445613214	0	0
T1	122705	122429	0	0
T2	55248	55158	0	0
T5	185520	184466	0	0
T6	193079	193017	0	0
T13	253372	253367	0	0
T14	25682	25606	0	0
T15	30522	30468	0	0
T16	241068	240987	0	0
T17	128834	128827	0	0
T18	243595	243500	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T13,T17

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T13,T17
1	1	Covered	T1,T13,T17

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T13,T17

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T13,T17
1	1	Covered	T1,T13,T17

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T13,T17
0	0	1	Covered	T1,T13,T17
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T13,T17
0	0	1	Covered	T1,T13,T17
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1447468969	1583077	0	0
DstReqKnown_A	8160742	7311983	0	0
SrcAckBusyChk_A	1447468969	1744	0	0
SrcBusyKnown_A	1447468969	1445613214	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1583077	0	0
T1	122705	16034	0	0
T2	55248	0	0	0
T5	185520	0	0	0
T6	193079	0	0	0
T11	0	4761	0	0
T12	0	13534	0	0
T13	253372	1422	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	694	0	0
T18	243595	0	0	0
T30	0	2338	0	0
T32	0	1648	0	0
T37	0	6851	0	0
T43	0	6768	0	0
T54	0	272	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8160742	7311983	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1744	0	0
T1	122705	10	0	0
T2	55248	0	0	0
T5	185520	0	0	0
T6	193079	0	0	0
T11	0	3	0	0
T12	0	9	0	0
T13	253372	1	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	1	0	0
T18	243595	0	0	0
T30	0	7	0	0
T32	0	4	0	0
T37	0	4	0	0
T43	0	8	0	0
T54	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1445613214	0	0
T1	122705	122429	0	0
T2	55248	55158	0	0
T5	185520	184466	0	0
T6	193079	193017	0	0
T13	253372	253367	0	0
T14	25682	25606	0	0
T15	30522	30468	0	0
T16	241068	240987	0	0
T17	128834	128827	0	0
T18	243595	243500	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T13,T17

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T13,T17
1	1	Covered	T1,T13,T17

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T13,T17

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T13,T17
1	1	Covered	T1,T13,T17

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T13,T17
0	0	1	Covered	T1,T13,T17
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T13,T17
0	0	1	Covered	T1,T13,T17
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1447468969	1577770	0	0
DstReqKnown_A	8160742	7311983	0	0
SrcAckBusyChk_A	1447468969	1738	0	0
SrcBusyKnown_A	1447468969	1445613214	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1577770	0	0
T1	122705	16014	0	0
T2	55248	0	0	0
T5	185520	0	0	0
T6	193079	0	0	0
T11	0	4734	0	0
T12	0	13516	0	0
T13	253372	1418	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	684	0	0
T18	243595	0	0	0
T30	0	2689	0	0
T32	0	1608	0	0
T37	0	6754	0	0
T43	0	6752	0	0
T54	0	363	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8160742	7311983	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1738	0	0
T1	122705	10	0	0
T2	55248	0	0	0
T5	185520	0	0	0
T6	193079	0	0	0
T11	0	3	0	0
T12	0	9	0	0
T13	253372	1	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	1	0	0
T18	243595	0	0	0
T30	0	7	0	0
T32	0	4	0	0
T37	0	4	0	0
T43	0	8	0	0
T54	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1445613214	0	0
T1	122705	122429	0	0
T2	55248	55158	0	0
T5	185520	184466	0	0
T6	193079	193017	0	0
T13	253372	253367	0	0
T14	25682	25606	0	0
T15	30522	30468	0	0
T16	241068	240987	0	0
T17	128834	128827	0	0
T18	243595	243500	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T13

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T13

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T13
0	0	1	Covered	T1,T5,T13
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T5,T13
0	0	1	Covered	T1,T5,T13
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1447468969	1668542	0	0
DstReqKnown_A	8160742	7311983	0	0
SrcAckBusyChk_A	1447468969	1800	0	0
SrcBusyKnown_A	1447468969	1445613214	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1668542	0	0
T1	122705	15994	0	0
T2	55248	0	0	0
T5	185520	1681	0	0
T6	193079	0	0	0
T11	0	4716	0	0
T12	0	13498	0	0
T13	253372	1405	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	712	0	0
T18	243595	0	0	0
T28	0	3240	0	0
T30	0	2805	0	0
T31	0	1874	0	0
T43	0	6736	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8160742	7311983	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1800	0	0
T1	122705	10	0	0
T2	55248	0	0	0
T5	185520	1	0	0
T6	193079	0	0	0
T11	0	3	0	0
T12	0	9	0	0
T13	253372	1	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	1	0	0
T18	243595	0	0	0
T28	0	2	0	0
T30	0	7	0	0
T31	0	1	0	0
T43	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1445613214	0	0
T1	122705	122429	0	0
T2	55248	55158	0	0
T5	185520	184466	0	0
T6	193079	193017	0	0
T13	253372	253367	0	0
T14	25682	25606	0	0
T15	30522	30468	0	0
T16	241068	240987	0	0
T17	128834	128827	0	0
T18	243595	243500	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T13,T17

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T13,T17
1	1	Covered	T1,T13,T17

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T13,T17

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T13,T17
1	1	Covered	T1,T13,T17

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T13,T17
0	0	1	Covered	T1,T13,T17
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T13,T17
0	0	1	Covered	T1,T13,T17
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1447468969	1591569	0	0
DstReqKnown_A	8160742	7311983	0	0
SrcAckBusyChk_A	1447468969	1743	0	0
SrcBusyKnown_A	1447468969	1445613214	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1591569	0	0
T1	122705	15974	0	0
T2	55248	0	0	0
T5	185520	0	0	0
T6	193079	0	0	0
T11	0	4682	0	0
T12	0	13480	0	0
T13	253372	1399	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	702	0	0
T18	243595	0	0	0
T30	0	2559	0	0
T32	0	1680	0	0
T37	0	6957	0	0
T43	0	6720	0	0
T54	0	302	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8160742	7311983	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1743	0	0
T1	122705	10	0	0
T2	55248	0	0	0
T5	185520	0	0	0
T6	193079	0	0	0
T11	0	3	0	0
T12	0	9	0	0
T13	253372	1	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	1	0	0
T18	243595	0	0	0
T30	0	7	0	0
T32	0	4	0	0
T37	0	4	0	0
T43	0	8	0	0
T54	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1445613214	0	0
T1	122705	122429	0	0
T2	55248	55158	0	0
T5	185520	184466	0	0
T6	193079	193017	0	0
T13	253372	253367	0	0
T14	25682	25606	0	0
T15	30522	30468	0	0
T16	241068	240987	0	0
T17	128834	128827	0	0
T18	243595	243500	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T13,T17

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T13,T17
1	1	Covered	T1,T13,T17

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T13,T17

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T13,T17
1	1	Covered	T1,T13,T17

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T13,T17
0	0	1	Covered	T1,T13,T17
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T13,T17
0	0	1	Covered	T1,T13,T17
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1447468969	1567172	0	0
DstReqKnown_A	8160742	7311983	0	0
SrcAckBusyChk_A	1447468969	1744	0	0
SrcBusyKnown_A	1447468969	1445613214	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1567172	0	0
T1	122705	15954	0	0
T2	55248	0	0	0
T5	185520	0	0	0
T6	193079	0	0	0
T11	0	4638	0	0
T12	0	13462	0	0
T13	253372	1384	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	692	0	0
T18	243595	0	0	0
T30	0	2405	0	0
T32	0	1640	0	0
T37	0	6833	0	0
T43	0	6704	0	0
T54	0	270	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8160742	7311983	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1744	0	0
T1	122705	10	0	0
T2	55248	0	0	0
T5	185520	0	0	0
T6	193079	0	0	0
T11	0	3	0	0
T12	0	9	0	0
T13	253372	1	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	1	0	0
T18	243595	0	0	0
T30	0	7	0	0
T32	0	4	0	0
T37	0	4	0	0
T43	0	8	0	0
T54	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1445613214	0	0
T1	122705	122429	0	0
T2	55248	55158	0	0
T5	185520	184466	0	0
T6	193079	193017	0	0
T13	253372	253367	0	0
T14	25682	25606	0	0
T15	30522	30468	0	0
T16	241068	240987	0	0
T17	128834	128827	0	0
T18	243595	243500	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T13,T17

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T13,T17
1	1	Covered	T1,T13,T17

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T13,T17

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T13,T17
1	1	Covered	T1,T13,T17

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T13,T17
0	0	1	Covered	T1,T13,T17
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T13,T17
0	0	1	Covered	T1,T13,T17
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1447468969	1521594	0	0
DstReqKnown_A	8160742	7311983	0	0
SrcAckBusyChk_A	1447468969	1691	0	0
SrcBusyKnown_A	1447468969	1445613214	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1521594	0	0
T1	122705	15934	0	0
T2	55248	0	0	0
T5	185520	0	0	0
T6	193079	0	0	0
T11	0	4620	0	0
T12	0	13444	0	0
T13	253372	1367	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	682	0	0
T18	243595	0	0	0
T30	0	2755	0	0
T32	0	1600	0	0
T37	0	6718	0	0
T43	0	6688	0	0
T54	0	351	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8160742	7311983	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1691	0	0
T1	122705	10	0	0
T2	55248	0	0	0
T5	185520	0	0	0
T6	193079	0	0	0
T11	0	3	0	0
T12	0	9	0	0
T13	253372	1	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	1	0	0
T18	243595	0	0	0
T30	0	7	0	0
T32	0	4	0	0
T37	0	4	0	0
T43	0	8	0	0
T54	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1445613214	0	0
T1	122705	122429	0	0
T2	55248	55158	0	0
T5	185520	184466	0	0
T6	193079	193017	0	0
T13	253372	253367	0	0
T14	25682	25606	0	0
T15	30522	30468	0	0
T16	241068	240987	0	0
T17	128834	128827	0	0
T18	243595	243500	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T2,T4,T22

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T2,T4,T22
1	1	Covered	T2,T4,T22

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T2,T4,T22
1	-	Covered	T2,T4,T22

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T2,T4,T22

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T22
1	1	Covered	T2,T4,T22

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T2,T4,T22
0	0	1	Covered	T2,T4,T22
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T2,T4,T22
0	0	1	Covered	T2,T4,T22
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1447468969	818808	0	0
DstReqKnown_A	8160742	7311983	0	0
SrcAckBusyChk_A	1447468969	923	0	0
SrcBusyKnown_A	1447468969	1445613214	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	818808	0	0
T2	55248	918	0	0
T3	264313	0	0	0
T4	0	2994	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T22	0	3218	0	0
T41	0	1706	0	0
T48	60578	0	0	0
T61	0	669	0	0
T70	236375	0	0	0
T72	193522	0	0	0
T77	0	4079	0	0
T78	0	159	0	0
T79	0	3416	0	0
T80	0	399	0	0
T81	0	740	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8160742	7311983	0	0
T1	25831	25373	0	0
T2	1099	699	0	0
T5	4417	660	0	0
T6	651	251	0	0
T13	5067	4667	0	0
T14	427	27	0	0
T15	508	108	0	0
T16	502	102	0	0
T17	5367	4967	0	0
T18	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	923	0	0
T2	55248	2	0	0
T3	264313	0	0	0
T4	0	2	0	0
T14	25682	0	0	0
T15	30522	0	0	0
T16	241068	0	0	0
T17	128834	0	0	0
T18	243595	0	0	0
T22	0	8	0	0
T41	0	2	0	0
T48	60578	0	0	0
T61	0	2	0	0
T70	236375	0	0	0
T72	193522	0	0	0
T77	0	6	0	0
T78	0	2	0	0
T79	0	2	0	0
T80	0	2	0	0
T81	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447468969	1445613214	0	0
T1	122705	122429	0	0
T2	55248	55158	0	0
T5	185520	184466	0	0
T6	193079	193017	0	0
T13	253372	253367	0	0
T14	25682	25606	0	0
T15	30522	30468	0	0
T16	241068	240987	0	0
T17	128834	128827	0	0
T18	243595	243500	0	0