Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
87.80	87.80	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	87.80	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
87.80	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	10	52	83.87

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	10	21	67.74	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1872

1

T1

3

T3

73

T9

5

auto[1]

547

1

T1

1

T2

9

T3

3

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1877

1

T1

4

T2

4

T3

63

auto[1]

542

1

T2

5

T3

13

T7

3

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1927

1

T1

3

T2

7

T3

76

auto[1]

492

1

T1

1

T2

2

T7

3

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1782

1

T1

3

T2

3

T3

40

auto[1]

637

1

T1

1

T2

6

T3

36

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2198

1

T1

4

T2

9

T3

53

auto[1]

221

1

T3

23

T10

3

T50

2

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2219

1

T1

3

T2

9

T3

73

auto[1]

200

1

T1

1

T3

3

T10

1

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2169

1

T1

4

T2

9

T3

53

auto[1]

250

1

T3

23

T10

2

T50

2

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2255

1

T1

4

T2

9

T3

73

auto[1]

164

1

T3

3

T10

4

T36

22

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2249

1

T1

4

T2

9

T3

50

auto[1]

170

1

T3

26

T10

1

T35

2

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1820

1

T1

3

T3

63

T7

3

auto[1]

599

1

T1

1

T2

9

T3

13

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	10	21	67.74	10
Automatically Generated Cross Bins	31	10	21	67.74	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	*	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[0]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[0]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	768	1			T2	9		T7	3		T9	8
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	67	1			T37	8		T127	1		T216	10
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	43	1			T35	2		T141	12		T369	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	46	1			T3	13		T38	12		T370	4
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	67	1			T10	4		T36	22		T310	1
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	10	1			T121	2		T371	8		-	-
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	13	1			T372	3		T373	1		T374	4
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	64	1			T375	1		T216	11		T271	3
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	29	1			T3	10		T10	2		T50	2
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	37	1			T3	13		T375	1		T355	6
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	9	1			T376	2		T377	7		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	26	1			T98	1		T355	6		T216	5
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	97	1			T1	1		T127	2		T98	1
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	9	1			T216	6		T378	3		-	-
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	1	1			T10	1		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	17	1			T3	3		T379	5		T380	8
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	11	1			T83	3		T371	8		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	3	1			T38	3		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	15	1			T35	2		T38	4		T381	8
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	9	1			T368	2		T268	1		T377	6
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	4	1			T382	4		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

74

1

T13

3

T194

11

T205

11

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

105

1

T98

1

T355

6

T214

7

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

75

1

T3

3

T13

1

T36

11

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

111

1

T3

13

T38

4

T114

9

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

51

1

T135

1

T179

6

T104

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

90

1

T3

10

T37

4

T375

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

38

1

T2

4

T35

2

T194

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

81

1

T10

5

T179

3

T370

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

40

1

T127

2

T38

3

T94

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

49

1

T127

1

T216

6

T354

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

16

1

T159

1

T135

3

T100

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

35

1

T9

5

T37

4

T94

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

36

1

T11

2

T13

1

T96

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

23

1

T99

7

T179

2

T383

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

11

1

T1

1

T13

1

T96

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

126

1

T38

12

T141

12

T269

6

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

61

1

T36

11

T79

6

T355

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

42

1

T50

2

T114

4

T216

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

24

1

T2

3

T214

3

T130

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

62

1

T3

13

T10

2

T35

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

17

1

T111

2

T99

3

T179

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

12

1

T79

5

T111

2

T355

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

13

1

T78

3

T365

4

T384

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

50

1

T114

6

T99

4

T181

7

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

27

1

T7

3

T9

3

T11

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

15

1

T270

3

T89

1

T385

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

8

1

T130

1

T386

1

T357

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

21

1

T216

10

T179

1

T104

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

6

1

T11

1

T130

3

T369

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

18

1

T159

1

T273

2

T280

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

8

1

T2

2

T199

2

T90

2

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded