Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

991

1

T4

12

T6

13

T15

6

auto[1]

989

1

T4

8

T6

7

T15

14

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

490

1

T4

5

T6

3

T15

6

from_0to1

488

1

T4

5

T6

3

T15

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

998

1

T4

13

T6

11

T15

10

auto[1]

982

1

T4

7

T6

9

T15

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

956

1

T4

16

T6

10

T15

15

auto[1]

1024

1

T4

4

T6

10

T15

5

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

68

1

T4

2

T15

2

T12

2

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T6

1

T162

2

T402

1

auto[0]

from_1to0

auto[1]

auto[0]

53

1

T4

1

T6

1

T13

1

auto[0]

from_1to0

auto[1]

auto[1]

72

1

T6

1

T15

1

T13

2

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T4

2

T13

1

T198

3

auto[0]

from_0to1

auto[0]

auto[1]

64

1

T4

2

T12

1

T13

1

auto[0]

from_0to1

auto[1]

auto[0]

60

1

T6

1

T13

2

T321

1

auto[0]

from_0to1

auto[1]

auto[1]

64

1

T13

2

T162

2

T402

1

auto[1]

from_1to0

auto[0]

auto[0]

48

1

T4

1

T15

1

T13

2

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T15

1

T12

1

T13

2

auto[1]

from_1to0

auto[1]

auto[0]

49

1

T13

2

T162

1

T321

1

auto[1]

from_1to0

auto[1]

auto[1]

74

1

T4

1

T15

1

T13

3

auto[1]

from_0to1

auto[0]

auto[0]

58

1

T4

1

T6

1

T15

3

auto[1]

from_0to1

auto[0]

auto[1]

52

1

T15

1

T12

1

T162

1

auto[1]

from_0to1

auto[1]

auto[0]

68

1

T15

1

T13

1

T162

2

auto[1]

from_0to1

auto[1]

auto[1]

57

1

T6

1

T13

2

T335

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1021

1

T4

11

T6

10

T15

10

auto[1]

959

1

T4

9

T6

10

T15

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

464

1

T4

5

T6

3

T15

4

from_0to1

468

1

T4

5

T6

3

T15

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

971

1

T4

14

T6

10

T15

11

auto[1]

1009

1

T4

6

T6

10

T15

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

996

1

T4

9

T6

12

T15

10

auto[1]

984

1

T4

11

T6

8

T15

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

58

1

T4

1

T6

1

T15

1

auto[0]

from_1to0

auto[0]

auto[1]

73

1

T12

2

T13

1

T162

1

auto[0]

from_1to0

auto[1]

auto[0]

58

1

T12

1

T402

1

T321

1

auto[0]

from_1to0

auto[1]

auto[1]

60

1

T6

1

T12

1

T162

1

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T4

1

T6

2

T12

1

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T4

1

T15

1

T12

2

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T4

1

T15

2

T12

2

auto[0]

from_0to1

auto[1]

auto[1]

68

1

T4

1

T6

1

T12

1

auto[1]

from_1to0

auto[0]

auto[0]

66

1

T4

2

T6

1

T15

1

auto[1]

from_1to0

auto[0]

auto[1]

51

1

T4

1

T15

1

T13

3

auto[1]

from_1to0

auto[1]

auto[0]

50

1

T12

1

T13

1

T162

1

auto[1]

from_1to0

auto[1]

auto[1]

48

1

T4

1

T15

1

T162

1

auto[1]

from_0to1

auto[0]

auto[0]

45

1

T402

1

T198

1

T403

2

auto[1]

from_0to1

auto[0]

auto[1]

55

1

T13

2

T321

1

T335

1

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T4

1

T15

1

T200

1

auto[1]

from_0to1

auto[1]

auto[1]

54

1

T15

1

T162

1

T198

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1006

1

T4

9

T6

7

T15

12

auto[1]

974

1

T4

11

T6

13

T15

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

469

1

T4

3

T6

4

T15

5

from_0to1

466

1

T4

3

T6

3

T15

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1004

1

T4

15

T6

10

T15

11

auto[1]

976

1

T4

5

T6

10

T15

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

996

1

T4

9

T6

9

T15

11

auto[1]

984

1

T4

11

T6

11

T15

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

56

1

T15

1

T13

2

T402

1

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T15

1

T402

2

T143

1

auto[0]

from_1to0

auto[1]

auto[0]

52

1

T13

1

T162

1

T321

2

auto[0]

from_1to0

auto[1]

auto[1]

56

1

T15

1

T402

1

T143

2

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T4

2

T15

1

T13

3

auto[0]

from_0to1

auto[0]

auto[1]

47

1

T13

1

T162

1

T321

1

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T162

1

T335

1

T198

1

auto[0]

from_0to1

auto[1]

auto[1]

52

1

T12

1

T13

1

T162

1

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T4

1

T6

1

T15

2

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T4

2

T6

2

T12

4

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T6

1

T13

3

T162

1

auto[1]

from_1to0

auto[1]

auto[1]

44

1

T12

2

T13

2

T321

1

auto[1]

from_0to1

auto[0]

auto[0]

61

1

T15

1

T12

2

T13

1

auto[1]

from_0to1

auto[0]

auto[1]

63

1

T4

1

T6

1

T15

1

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T6

1

T12

2

T13

1

auto[1]

from_0to1

auto[1]

auto[1]

50

1

T6

1

T15

1

T12

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1019

1

T4

10

T6

11

T15

8

auto[1]

961

1

T4

10

T6

9

T15

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

484

1

T4

4

T6

5

T15

4

from_0to1

491

1

T4

4

T6

5

T15

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1034

1

T4

11

T6

9

T15

10

auto[1]

946

1

T4

9

T6

11

T15

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

931

1

T4

10

T6

11

T15

9

auto[1]

1049

1

T4

10

T6

9

T15

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

79

1

T4

2

T6

2

T12

1

auto[0]

from_1to0

auto[0]

auto[1]

58

1

T4

1

T6

2

T12

2

auto[0]

from_1to0

auto[1]

auto[0]

55

1

T6

1

T15

1

T162

1

auto[0]

from_1to0

auto[1]

auto[1]

61

1

T4

1

T13

1

T162

2

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T15

1

T13

3

T162

1

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T12

1

T13

1

T402

2

auto[0]

from_0to1

auto[1]

auto[0]

56

1

T6

1

T12

1

T162

1

auto[0]

from_0to1

auto[1]

auto[1]

56

1

T6

1

T15

1

T12

2

auto[1]

from_1to0

auto[0]

auto[0]

54

1

T15

2

T13

5

T335

1

auto[1]

from_1to0

auto[0]

auto[1]

55

1

T13

1

T335

1

T200

1

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T15

1

T162

1

T402

3

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T202

2

T404

1

T405

2

auto[1]

from_0to1

auto[0]

auto[0]

52

1

T6

1

T13

1

T162

1

auto[1]

from_0to1

auto[0]

auto[1]

82

1

T4

1

T6

1

T15

2

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T4

3

T13

2

T162

2

auto[1]

from_0to1

auto[1]

auto[1]

53

1

T6

1

T15

1

T13

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

978

1

T4

11

T6

9

T15

8

auto[1]

1002

1

T4

9

T6

11

T15

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

474

1

T4

4

T6

5

T15

6

from_0to1

472

1

T4

5

T6

5

T15

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1021

1

T4

11

T6

10

T15

13

auto[1]

959

1

T4

9

T6

10

T15

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

977

1

T4

11

T6

7

T15

10

auto[1]

1003

1

T4

9

T6

13

T15

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T4

1

T13

3

T402

1

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T6

1

T15

2

T13

1

auto[0]

from_1to0

auto[1]

auto[0]

51

1

T12

1

T321

1

T198

1

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T4

2

T6

1

T15

2

auto[0]

from_0to1

auto[0]

auto[0]

76

1

T4

1

T6

1

T15

2

auto[0]

from_0to1

auto[0]

auto[1]

55

1

T12

1

T13

2

T162

1

auto[0]

from_0to1

auto[1]

auto[0]

63

1

T12

2

T13

2

T335

1

auto[0]

from_0to1

auto[1]

auto[1]

40

1

T6

1

T12

1

T402

1

auto[1]

from_1to0

auto[0]

auto[0]

54

1

T4

1

T13

1

T402

1

auto[1]

from_1to0

auto[0]

auto[1]

71

1

T6

1

T15

2

T12

1

auto[1]

from_1to0

auto[1]

auto[0]

54

1

T6

1

T402

1

T198

1

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T6

1

T12

1

T13

1

auto[1]

from_0to1

auto[0]

auto[0]

65

1

T4

1

T15

1

T13

1

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T4

1

T6

1

T402

1

auto[1]

from_0to1

auto[1]

auto[0]

57

1

T4

1

T6

1

T15

1

auto[1]

from_0to1

auto[1]

auto[1]

54

1

T4

1

T6

1

T15

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

978

1

T4

13

T6

11

T15

10

auto[1]

1002

1

T4

7

T6

9

T15

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

473

1

T4

5

T6

6

T15

5

from_0to1

474

1

T4

4

T6

6

T15

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

967

1

T4

11

T6

13

T15

10

auto[1]

1013

1

T4

9

T6

7

T15

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

984

1

T4

12

T6

12

T15

11

auto[1]

996

1

T4

8

T6

8

T15

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T4

2

T6

1

T15

1

auto[0]

from_1to0

auto[0]

auto[1]

69

1

T15

1

T12

2

T13

1

auto[0]

from_1to0

auto[1]

auto[0]

48

1

T4

1

T15

2

T13

1

auto[0]

from_1to0

auto[1]

auto[1]

60

1

T4

1

T6

3

T13

2

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T4

2

T6

3

T15

1

auto[0]

from_0to1

auto[0]

auto[1]

47

1

T4

2

T15

1

T13

1

auto[0]

from_0to1

auto[1]

auto[0]

57

1

T6

1

T12

1

T13

1

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T13

1

T321

1

T335

2

auto[1]

from_1to0

auto[0]

auto[0]

51

1

T12

2

T13

1

T162

1

auto[1]

from_1to0

auto[0]

auto[1]

63

1

T13

2

T162

1

T321

2

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T4

1

T6

2

T13

1

auto[1]

from_1to0

auto[1]

auto[1]

52

1

T15

1

T12

1

T13

3

auto[1]

from_0to1

auto[0]

auto[0]

57

1

T15

1

T13

1

T200

1

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T6

2

T12

1

T13

1

auto[1]

from_0to1

auto[1]

auto[0]

53

1

T15

2

T13

4

T402

1

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T12

1

T13

1

T162

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1020

1

T4

6

T6

13

T15

13

auto[1]

960

1

T4

14

T6

7

T15

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

469

1

T4

5

T6

5

T15

6

from_0to1

478

1

T4

4

T6

6

T15

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

978

1

T4

7

T6

8

T15

8

auto[1]

1002

1

T4

13

T6

12

T15

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1003

1

T4

12

T6

9

T15

11

auto[1]

977

1

T4

8

T6

11

T15

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

68

1

T6

1

T13

4

T335

1

auto[0]

from_1to0

auto[0]

auto[1]

51

1

T4

1

T6

1

T402

1

auto[0]

from_1to0

auto[1]

auto[0]

51

1

T4

2

T15

1

T198

1

auto[0]

from_1to0

auto[1]

auto[1]

70

1

T6

2

T15

2

T12

1

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T12

1

T13

3

T162

1

auto[0]

from_0to1

auto[0]

auto[1]

54

1

T6

1

T12

1

T13

1

auto[0]

from_0to1

auto[1]

auto[0]

77

1

T15

1

T13

1

T162

1

auto[0]

from_0to1

auto[1]

auto[1]

64

1

T6

1

T15

2

T13

1

auto[1]

from_1to0

auto[0]

auto[0]

47

1

T15

1

T162

1

T402

1

auto[1]

from_1to0

auto[0]

auto[1]

57

1

T4

1

T12

2

T13

2

auto[1]

from_1to0

auto[1]

auto[0]

69

1

T4

1

T6

1

T12

1

auto[1]

from_1to0

auto[1]

auto[1]

56

1

T15

2

T198

3

T202

1

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T4

1

T6

2

T15

2

auto[1]

from_0to1

auto[0]

auto[1]

46

1

T13

2

T162

1

T402

2

auto[1]

from_0to1

auto[1]

auto[0]

55

1

T4

1

T6

2

T12

1

auto[1]

from_0to1

auto[1]

auto[1]

57

1

T4

2

T12

2

T321

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

969

1

T4

8

T6

13

T15

8

auto[1]

1011

1

T4

12

T6

7

T15

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

476

1

T4

4

T6

4

T15

4

from_0to1

477

1

T4

4

T6

4

T15

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

981

1

T4

7

T6

11

T15

13

auto[1]

999

1

T4

13

T6

9

T15

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1020

1

T4

14

T6

11

T15

11

auto[1]

960

1

T4

6

T6

9

T15

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

47

1

T4

1

T6

1

T15

1

auto[0]

from_1to0

auto[0]

auto[1]

46

1

T4

1

T6

1

T13

1

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T13

2

T402

1

T321

1

auto[0]

from_1to0

auto[1]

auto[1]

55

1

T6

1

T15

1

T162

1

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T6

2

T15

1

T13

3

auto[0]

from_0to1

auto[0]

auto[1]

44

1

T12

2

T402

1

T200

1

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T4

3

T6

1

T15

1

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T12

1

T162

1

T402

1

auto[1]

from_1to0

auto[0]

auto[0]

69

1

T6

1

T15

2

T13

2

auto[1]

from_1to0

auto[0]

auto[1]

71

1

T12

3

T13

2

T162

1

auto[1]

from_1to0

auto[1]

auto[0]

59

1

T4

1

T12

1

T13

3

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T4

1

T321

1

T335

1

auto[1]

from_0to1

auto[0]

auto[0]

68

1

T15

1

T13

4

T162

1

auto[1]

from_0to1

auto[0]

auto[1]

55

1

T15

1

T12

1

T13

1

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T4

1

T13

1

T162

1

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T6

1

T13

2

T402

2