Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	154018	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

119913

1

T4

357

T5

6

T6

34

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	139633	1			T4	282		T5	8		T6	62
values[0x0]	66624	1			T4	302		T5	4		T6	31
values[0x1]	67674	1			T4	305		T5	4		T6	30

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	125039	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

148892

1

T4

432

T5

9

T6

44

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1063	1			T1	3		T19	3		T48	3
valid_sources[0x01]	1164	1			T19	3		T3	1		T48	2
valid_sources[0x02]	1645	1			T6	2		T48	3		T9	1
valid_sources[0x03]	789	1			T1	16		T19	2		T48	2
valid_sources[0x04]	811	1			T19	1		T48	2		T9	3
valid_sources[0x05]	945	1			T1	4		T19	1		T48	1
valid_sources[0x06]	882	1			T19	1		T48	6		T9	2
valid_sources[0x07]	792	1			T1	3		T3	7		T48	2
valid_sources[0x08]	739	1			T48	4		T9	1		T10	2
valid_sources[0x09]	895	1			T1	4		T19	4		T48	1
valid_sources[0x0a]	913	1			T1	8		T19	4		T3	62
valid_sources[0x0b]	1293	1			T18	2		T19	3		T3	8
valid_sources[0x0c]	1861	1			T6	2		T1	5		T19	2
valid_sources[0x0d]	779	1			T1	12		T19	2		T48	2
valid_sources[0x0e]	1425	1			T6	1		T19	2		T3	3
valid_sources[0x0f]	1538	1			T6	1		T1	12		T19	1
valid_sources[0x10]	1667	1			T6	2		T19	6		T3	3
valid_sources[0x11]	819	1			T19	2		T48	2		T9	2
valid_sources[0x12]	1331	1			T3	5		T48	1		T10	5
valid_sources[0x13]	872	1			T4	3		T19	2		T3	5
valid_sources[0x14]	1091	1			T1	1		T19	1		T3	31
valid_sources[0x15]	871	1			T6	3		T1	5		T19	1
valid_sources[0x16]	1001	1			T1	7		T19	4		T3	2
valid_sources[0x17]	1636	1			T4	279		T1	7		T3	6
valid_sources[0x18]	818	1			T5	1		T6	1		T19	4
valid_sources[0x19]	831	1			T6	2		T1	11		T48	3
valid_sources[0x1a]	1499	1			T19	2		T3	30		T48	3
valid_sources[0x1b]	1081	1			T6	3		T1	4		T19	1
valid_sources[0x1c]	910	1			T1	1		T19	1		T21	6
valid_sources[0x1d]	1077	1			T1	2		T19	2		T48	5
valid_sources[0x1e]	834	1			T1	6		T19	1		T3	10
valid_sources[0x1f]	886	1			T6	1		T1	5		T14	4
valid_sources[0x20]	811	1			T1	3		T19	1		T48	4
valid_sources[0x21]	962	1			T1	7		T19	1		T3	12
valid_sources[0x22]	1523	1			T14	1		T19	2		T3	44
valid_sources[0x23]	1087	1			T6	1		T19	3		T48	2
valid_sources[0x24]	999	1			T1	20		T19	3		T48	5
valid_sources[0x25]	1417	1			T19	2		T48	4		T9	1
valid_sources[0x26]	786	1			T6	1		T1	7		T19	3
valid_sources[0x27]	1532	1			T4	380		T1	2		T19	2
valid_sources[0x28]	1260	1			T19	3		T48	1		T9	2
valid_sources[0x29]	910	1			T6	1		T19	4		T48	2
valid_sources[0x2a]	910	1			T1	9		T19	3		T48	3
valid_sources[0x2b]	793	1			T1	10		T19	1		T48	1
valid_sources[0x2c]	991	1			T6	2		T1	6		T19	1
valid_sources[0x2d]	1082	1			T6	1		T19	2		T21	3
valid_sources[0x2e]	956	1			T6	4		T19	1		T20	3
valid_sources[0x2f]	707	1			T6	1		T1	4		T19	1
valid_sources[0x30]	983	1			T6	1		T1	6		T14	7
valid_sources[0x31]	1987	1			T1	2		T3	19		T48	3
valid_sources[0x32]	905	1			T1	1		T19	2		T48	4
valid_sources[0x33]	935	1			T19	1		T34	1		T9	2
valid_sources[0x34]	1120	1			T6	2		T1	12		T14	7
valid_sources[0x35]	950	1			T17	2		T3	16		T48	6
valid_sources[0x36]	1318	1			T1	1		T19	1		T21	4
valid_sources[0x37]	945	1			T1	10		T19	3		T3	6
valid_sources[0x38]	942	1			T1	6		T19	1		T3	2
valid_sources[0x39]	1055	1			T18	3		T48	4		T9	4
valid_sources[0x3a]	2080	1			T1	7		T19	3		T3	33
valid_sources[0x3b]	1495	1			T48	1		T9	3		T13	1
valid_sources[0x3c]	904	1			T6	4		T1	5		T19	2
valid_sources[0x3d]	1222	1			T1	3		T19	1		T9	1
valid_sources[0x3e]	899	1			T1	3		T19	2		T48	4
valid_sources[0x3f]	758	1			T6	2		T19	3		T48	3
valid_sources[0x40]	1254	1			T1	1		T19	1		T48	7
valid_sources[0x41]	1106	1			T6	2		T1	1		T19	1
valid_sources[0x42]	1110	1			T6	1		T1	5		T48	5
valid_sources[0x43]	1031	1			T1	3		T19	1		T48	6
valid_sources[0x44]	888	1			T1	3		T3	3		T48	2
valid_sources[0x45]	1391	1			T1	8		T19	2		T20	5
valid_sources[0x46]	1067	1			T1	4		T19	3		T3	7
valid_sources[0x47]	834	1			T1	3		T19	5		T48	1
valid_sources[0x48]	751	1			T1	3		T19	2		T3	9
valid_sources[0x49]	875	1			T48	4		T34	1		T9	3
valid_sources[0x4a]	2341	1			T19	1		T48	4		T66	2
valid_sources[0x4b]	1001	1			T6	1		T1	1		T48	4
valid_sources[0x4c]	1288	1			T1	2		T19	1		T3	2
valid_sources[0x4d]	1107	1			T1	2		T19	2		T20	3
valid_sources[0x4e]	2341	1			T19	2		T3	16		T48	4
valid_sources[0x4f]	991	1			T19	1		T3	40		T48	3
valid_sources[0x50]	848	1			T19	3		T3	6		T48	6
valid_sources[0x51]	981	1			T6	3		T1	1		T19	3
valid_sources[0x52]	1301	1			T4	3		T20	2		T48	3
valid_sources[0x53]	1017	1			T1	6		T19	3		T48	1
valid_sources[0x54]	2106	1			T18	2		T19	2		T3	38
valid_sources[0x55]	1029	1			T1	2		T48	4		T9	1
valid_sources[0x56]	1359	1			T1	23		T19	1		T3	20
valid_sources[0x57]	818	1			T6	5		T19	1		T3	12
valid_sources[0x58]	912	1			T1	11		T48	3		T9	2
valid_sources[0x59]	1047	1			T1	7		T19	5		T3	22
valid_sources[0x5a]	733	1			T1	6		T19	1		T3	3
valid_sources[0x5b]	834	1			T1	3		T48	2		T10	9
valid_sources[0x5c]	2306	1			T1	2		T19	2		T3	2
valid_sources[0x5d]	1195	1			T1	9		T19	2		T48	2
valid_sources[0x5e]	1901	1			T19	1		T21	1		T3	7
valid_sources[0x5f]	949	1			T1	1		T19	1		T48	4
valid_sources[0x60]	1229	1			T19	1		T48	3		T9	1
valid_sources[0x61]	899	1			T1	4		T19	1		T21	9
valid_sources[0x62]	1189	1			T1	5		T3	8		T48	2
valid_sources[0x63]	851	1			T1	6		T3	9		T48	3
valid_sources[0x64]	852	1			T6	1		T1	1		T19	4
valid_sources[0x65]	961	1			T6	1		T1	8		T19	2
valid_sources[0x66]	1045	1			T1	4		T19	4		T3	1
valid_sources[0x67]	871	1			T6	2		T1	6		T20	1
valid_sources[0x68]	971	1			T6	2		T1	1		T19	4
valid_sources[0x69]	815	1			T4	20		T19	2		T48	3
valid_sources[0x6a]	1188	1			T1	9		T3	4		T48	5
valid_sources[0x6b]	953	1			T6	1		T1	2		T3	15
valid_sources[0x6c]	986	1			T48	8		T66	2		T9	2
valid_sources[0x6d]	1189	1			T21	3		T9	2		T10	6
valid_sources[0x6e]	934	1			T6	3		T1	2		T19	4
valid_sources[0x6f]	1185	1			T6	1		T1	5		T18	2
valid_sources[0x70]	1567	1			T1	6		T19	2		T3	5
valid_sources[0x71]	898	1			T1	3		T19	4		T48	4
valid_sources[0x72]	1048	1			T19	4		T48	3		T9	1
valid_sources[0x73]	1166	1			T4	16		T1	5		T48	7
valid_sources[0x74]	843	1			T1	2		T19	3		T20	6
valid_sources[0x75]	1482	1			T6	1		T1	2		T19	1
valid_sources[0x76]	1026	1			T6	1		T14	10		T18	14
valid_sources[0x77]	899	1			T1	3		T18	1		T19	3
valid_sources[0x78]	969	1			T1	1		T21	1		T3	42
valid_sources[0x79]	1023	1			T6	1		T1	2		T14	4
valid_sources[0x7a]	842	1			T1	8		T19	2		T48	3
valid_sources[0x7b]	1119	1			T4	172		T1	1		T19	1
valid_sources[0x7c]	898	1			T48	2		T34	1		T9	1
valid_sources[0x7d]	785	1			T1	6		T19	3		T3	9
valid_sources[0x7e]	708	1			T6	1		T19	1		T48	2
valid_sources[0x7f]	937	1			T19	3		T48	2		T9	4
valid_sources[0x80]	1100	1			T1	13		T20	5		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

64315

1

T4

151

T5

3

T6

24

values[0x0]

all_enables

biggest_size

32632

1

T4

130

T5

1

T6

8

values[0x1]

all_enables

biggest_size

22966

1

T4

76

T5

2

T6

2