Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T4,T5,T13

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T13
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T5,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T13
0	1	Covered	T105,T106,T107
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T13
0	1	Covered	T4,T5,T13
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T5,T13
1	-	Covered	T4,T5,T13

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T5,T13
DetectSt	168	Covered	T4,T5,T13
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T4,T5,T13

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T5,T13
DebounceSt->IdleSt	163	Covered	T4,T13,T54
DetectSt->IdleSt	186	Covered	T105,T106,T107
DetectSt->StableSt	191	Covered	T4,T5,T13
IdleSt->DebounceSt	148	Covered	T4,T5,T13
StableSt->IdleSt	206	Covered	T4,T5,T13

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T5,T13
0	1	Covered	T4,T5,T13
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T13
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T5,T13
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T5,T13
DebounceSt	-	0	1	0	-	-	-	Covered	T13,T54,T94
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T5,T13
DetectSt	-	-	-	-	1	-	-	Covered	T105,T106,T107
DetectSt	-	-	-	-	0	1	-	Covered	T4,T5,T13
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T5,T13
StableSt	-	-	-	-	-	-	0	Covered	T4,T5,T13
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6727276	291	0	0
CntIncr_A	6727276	180602	0	0
CntNoWrap_A	6727276	6055374	0	0
DetectStDropOut_A	6727276	4	0	0
DetectedOut_A	6727276	770	0	0
DetectedPulseOut_A	6727276	125	0	0
DisabledIdleSt_A	6727276	5868255	0	0
DisabledNoDetection_A	6727276	5870537	0	0
EnterDebounceSt_A	6727276	169	0	0
EnterDetectSt_A	6727276	129	0	0
EnterStableSt_A	6727276	125	0	0
PulseIsPulse_A	6727276	125	0	0
StayInStableSt	6727276	645	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6727276	7076	0	0
gen_low_level_sva.LowLevelEvent_A	6727276	6058011	0	0
gen_not_sticky_sva.StableStDropOut_A	6727276	125	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	291	0	0
T1	7230	0	0	0
T4	26326	2	0	0
T5	652	6	0	0
T6	507	0	0	0
T13	0	9	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	0	0	0
T44	0	4	0	0
T52	0	4	0	0
T54	0	5	0	0
T55	0	4	0	0
T56	0	2	0	0
T57	0	4	0	0
T94	0	7	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	180602	0	0
T1	7230	0	0	0
T4	26326	13340	0	0
T5	652	112	0	0
T6	507	0	0	0
T13	0	260	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	0	0	0
T44	0	1945	0	0
T52	0	63	0	0
T54	0	172	0	0
T55	0	118	0	0
T56	0	29	0	0
T57	0	114	0	0
T94	0	229	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6055374	0	0
T1	7230	6829	0	0
T4	26326	17887	0	0
T5	652	245	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	4815	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	4	0	0
T105	643	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T109	0	1	0	0
T117	410	0	0	0
T118	525	0	0	0
T119	495	0	0	0
T120	426	0	0	0
T121	29589	0	0	0
T122	410	0	0	0
T123	536	0	0	0
T124	913	0	0	0
T125	666	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	770	0	0
T1	7230	0	0	0
T4	26326	2	0	0
T5	652	29	0	0
T6	507	0	0	0
T13	0	35	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	0	0	0
T44	0	8	0	0
T52	0	12	0	0
T54	0	15	0	0
T55	0	5	0	0
T56	0	1	0	0
T57	0	16	0	0
T94	0	14	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	125	0	0
T1	7230	0	0	0
T4	26326	1	0	0
T5	652	3	0	0
T6	507	0	0	0
T13	0	4	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	0	0	0
T44	0	2	0	0
T52	0	2	0	0
T54	0	2	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	2	0	0
T94	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5868255	0	0
T1	7230	6829	0	0
T4	26326	4504	0	0
T5	652	3	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	4815	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5870537	0	0
T1	7230	6830	0	0
T4	26326	4525	0	0
T5	652	3	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	169	0	0
T1	7230	0	0	0
T4	26326	2	0	0
T5	652	3	0	0
T6	507	0	0	0
T13	0	5	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	0	0	0
T44	0	3	0	0
T52	0	2	0	0
T54	0	3	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	2	0	0
T94	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	129	0	0
T1	7230	0	0	0
T4	26326	1	0	0
T5	652	3	0	0
T6	507	0	0	0
T13	0	4	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	0	0	0
T44	0	2	0	0
T52	0	2	0	0
T54	0	2	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	2	0	0
T94	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	125	0	0
T1	7230	0	0	0
T4	26326	1	0	0
T5	652	3	0	0
T6	507	0	0	0
T13	0	4	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	0	0	0
T44	0	2	0	0
T52	0	2	0	0
T54	0	2	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	2	0	0
T94	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	125	0	0
T1	7230	0	0	0
T4	26326	1	0	0
T5	652	3	0	0
T6	507	0	0	0
T13	0	4	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	0	0	0
T44	0	2	0	0
T52	0	2	0	0
T54	0	2	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	2	0	0
T94	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	645	0	0
T1	7230	0	0	0
T4	26326	1	0	0
T5	652	26	0	0
T6	507	0	0	0
T13	0	31	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	0	0	0
T44	0	6	0	0
T52	0	10	0	0
T54	0	13	0	0
T55	0	3	0	0
T57	0	14	0	0
T94	0	11	0	0
T128	0	4	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	7076	0	0
T1	7230	28	0	0
T4	26326	49	0	0
T5	652	3	0	0
T6	507	3	0	0
T14	539	4	0	0
T15	501	5	0	0
T16	742	0	0	0
T17	428	2	0	0
T18	493	7	0	0
T19	5216	30	0	0
T20	0	9	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6058011	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	125	0	0
T1	7230	0	0	0
T4	26326	1	0	0
T5	652	3	0	0
T6	507	0	0	0
T13	0	4	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	0	0	0
T44	0	2	0	0
T52	0	2	0	0
T54	0	2	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	2	0	0
T94	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T12,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T12,T26

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T12,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T26
1	0	Covered	T4,T5,T6
1	1	Covered	T8,T12,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T12,T26
0	1	Covered	T41,T92,T87
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T12,T26
0	1	Unreachable
1	0	Covered	T8,T12,T26

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T12,T26
DetectSt	168	Covered	T8,T12,T26
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T12,T26

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T12,T26
DebounceSt->IdleSt	163	Covered	T74,T80,T87
DetectSt->IdleSt	186	Covered	T41,T92,T87
DetectSt->StableSt	191	Covered	T8,T12,T26
IdleSt->DebounceSt	148	Covered	T8,T12,T26
StableSt->IdleSt	206	Covered	T8,T12,T26

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T12,T26
0	1	Covered	T8,T12,T26
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T12,T26
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T12,T26
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T12,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T74,T87,T90
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T12,T26
DetectSt	-	-	-	-	1	-	-	Covered	T41,T92,T87
DetectSt	-	-	-	-	0	1	-	Covered	T8,T12,T26
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T12,T26
StableSt	-	-	-	-	-	-	0	Covered	T8,T12,T26
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6727276	141	0	0
CntIncr_A	6727276	4721	0	0
CntNoWrap_A	6727276	6055524	0	0
DetectStDropOut_A	6727276	7	0	0
DetectedOut_A	6727276	10385	0	0
DetectedPulseOut_A	6727276	45	0	0
DisabledIdleSt_A	6727276	5251527	0	0
DisabledNoDetection_A	6727276	5253872	0	0
EnterDebounceSt_A	6727276	89	0	0
EnterDetectSt_A	6727276	52	0	0
EnterStableSt_A	6727276	45	0	0
PulseIsPulse_A	6727276	45	0	0
StayInStableSt	6727276	10340	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6727276	7076	0	0
gen_low_level_sva.LowLevelEvent_A	6727276	6058011	0	0
gen_sticky_sva.StableStDropOut_A	6727276	407093	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	141	0	0
T8	424352	2	0	0
T9	6991	0	0	0
T10	20595	0	0	0
T11	13539	0	0	0
T12	2950	2	0	0
T13	17737	0	0	0
T26	0	2	0	0
T41	0	2	0	0
T44	0	2	0	0
T49	5368	0	0	0
T50	6864	0	0	0
T63	0	2	0	0
T66	406	0	0	0
T67	523	0	0	0
T74	0	3	0	0
T75	0	2	0	0
T76	0	2	0	0
T77	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	4721	0	0
T8	424352	80	0	0
T9	6991	0	0	0
T10	20595	0	0	0
T11	13539	0	0	0
T12	2950	27	0	0
T13	17737	0	0	0
T26	0	71	0	0
T41	0	96	0	0
T44	0	40	0	0
T49	5368	0	0	0
T50	6864	0	0	0
T63	0	49	0	0
T66	406	0	0	0
T67	523	0	0	0
T74	0	102	0	0
T75	0	70	0	0
T76	0	27	0	0
T77	0	83	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6055524	0	0
T1	7230	6829	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	4815	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	7	0	0
T41	96399	1	0	0
T87	0	1	0	0
T92	0	1	0	0
T133	0	2	0	0
T134	0	2	0	0
T135	11980	0	0	0
T136	1197	0	0	0
T137	8449	0	0	0
T138	670	0	0	0
T139	522	0	0	0
T140	489	0	0	0
T141	33910	0	0	0
T142	490	0	0	0
T143	506	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	10385	0	0
T8	424352	354	0	0
T9	6991	0	0	0
T10	20595	0	0	0
T11	13539	0	0	0
T12	2950	228	0	0
T13	17737	0	0	0
T26	0	227	0	0
T44	0	44	0	0
T49	5368	0	0	0
T50	6864	0	0	0
T63	0	120	0	0
T66	406	0	0	0
T67	523	0	0	0
T75	0	48	0	0
T76	0	92	0	0
T77	0	171	0	0
T87	0	129	0	0
T129	0	483	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	45	0	0
T8	424352	1	0	0
T9	6991	0	0	0
T10	20595	0	0	0
T11	13539	0	0	0
T12	2950	1	0	0
T13	17737	0	0	0
T26	0	1	0	0
T44	0	1	0	0
T49	5368	0	0	0
T50	6864	0	0	0
T63	0	1	0	0
T66	406	0	0	0
T67	523	0	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T87	0	1	0	0
T129	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5251527	0	0
T1	7230	6829	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	4815	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5253872	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	89	0	0
T8	424352	1	0	0
T9	6991	0	0	0
T10	20595	0	0	0
T11	13539	0	0	0
T12	2950	1	0	0
T13	17737	0	0	0
T26	0	1	0	0
T41	0	1	0	0
T44	0	1	0	0
T49	5368	0	0	0
T50	6864	0	0	0
T63	0	1	0	0
T66	406	0	0	0
T67	523	0	0	0
T74	0	3	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	52	0	0
T8	424352	1	0	0
T9	6991	0	0	0
T10	20595	0	0	0
T11	13539	0	0	0
T12	2950	1	0	0
T13	17737	0	0	0
T26	0	1	0	0
T41	0	1	0	0
T44	0	1	0	0
T49	5368	0	0	0
T50	6864	0	0	0
T63	0	1	0	0
T66	406	0	0	0
T67	523	0	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T129	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	45	0	0
T8	424352	1	0	0
T9	6991	0	0	0
T10	20595	0	0	0
T11	13539	0	0	0
T12	2950	1	0	0
T13	17737	0	0	0
T26	0	1	0	0
T44	0	1	0	0
T49	5368	0	0	0
T50	6864	0	0	0
T63	0	1	0	0
T66	406	0	0	0
T67	523	0	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T87	0	1	0	0
T129	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	45	0	0
T8	424352	1	0	0
T9	6991	0	0	0
T10	20595	0	0	0
T11	13539	0	0	0
T12	2950	1	0	0
T13	17737	0	0	0
T26	0	1	0	0
T44	0	1	0	0
T49	5368	0	0	0
T50	6864	0	0	0
T63	0	1	0	0
T66	406	0	0	0
T67	523	0	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T87	0	1	0	0
T129	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	10340	0	0
T8	424352	353	0	0
T9	6991	0	0	0
T10	20595	0	0	0
T11	13539	0	0	0
T12	2950	227	0	0
T13	17737	0	0	0
T26	0	226	0	0
T44	0	43	0	0
T49	5368	0	0	0
T50	6864	0	0	0
T63	0	119	0	0
T66	406	0	0	0
T67	523	0	0	0
T75	0	47	0	0
T76	0	91	0	0
T77	0	170	0	0
T87	0	128	0	0
T129	0	481	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	7076	0	0
T1	7230	28	0	0
T4	26326	49	0	0
T5	652	3	0	0
T6	507	3	0	0
T14	539	4	0	0
T15	501	5	0	0
T16	742	0	0	0
T17	428	2	0	0
T18	493	7	0	0
T19	5216	30	0	0
T20	0	9	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6058011	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	407093	0	0
T8	424352	302354	0	0
T9	6991	0	0	0
T10	20595	0	0	0
T11	13539	0	0	0
T12	2950	457	0	0
T13	17737	0	0	0
T26	0	86	0	0
T44	0	106	0	0
T49	5368	0	0	0
T50	6864	0	0	0
T63	0	63	0	0
T66	406	0	0	0
T67	523	0	0	0
T75	0	32	0	0
T76	0	216	0	0
T77	0	283	0	0
T87	0	123	0	0
T129	0	117	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T14
1	1	Covered	T4,T6,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T12,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T12,T26

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T12,T63,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T26
1	0	Covered	T4,T6,T14
1	1	Covered	T8,T12,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T63,T44
0	1	Covered	T41,T92,T93
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T63,T44
0	1	Unreachable
1	0	Covered	T12,T63,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T12,T26
DetectSt	168	Covered	T12,T63,T41
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T12,T63,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T63,T41
DebounceSt->IdleSt	163	Covered	T8,T26,T74
DetectSt->IdleSt	186	Covered	T41,T92,T93
DetectSt->StableSt	191	Covered	T12,T63,T44
IdleSt->DebounceSt	148	Covered	T8,T12,T26
StableSt->IdleSt	206	Covered	T12,T63,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T12,T26
0	1	Covered	T8,T12,T26
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T63,T41
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T12,T26
IdleSt	0	-	-	-	-	-	-	Covered	T4,T6,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T63,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T26,T74
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T12,T26
DetectSt	-	-	-	-	1	-	-	Covered	T41,T92,T93
DetectSt	-	-	-	-	0	1	-	Covered	T12,T63,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T63,T44
StableSt	-	-	-	-	-	-	0	Covered	T12,T63,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6727276	158	0	0
CntIncr_A	6727276	76281	0	0
CntNoWrap_A	6727276	6055507	0	0
DetectStDropOut_A	6727276	12	0	0
DetectedOut_A	6727276	256262	0	0
DetectedPulseOut_A	6727276	41	0	0
DisabledIdleSt_A	6727276	5251527	0	0
DisabledNoDetection_A	6727276	5253872	0	0
EnterDebounceSt_A	6727276	105	0	0
EnterDetectSt_A	6727276	53	0	0
EnterStableSt_A	6727276	41	0	0
PulseIsPulse_A	6727276	41	0	0
StayInStableSt	6727276	256221	0	0
gen_high_level_sva.HighLevelEvent_A	6727276	6058011	0	0
gen_sticky_sva.StableStDropOut_A	6727276	9046	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	158	0	0
T8	424352	5	0	0
T9	6991	0	0	0
T10	20595	0	0	0
T11	13539	0	0	0
T12	2950	2	0	0
T13	17737	0	0	0
T26	0	4	0	0
T41	0	2	0	0
T44	0	2	0	0
T49	5368	0	0	0
T50	6864	0	0	0
T63	0	2	0	0
T66	406	0	0	0
T67	523	0	0	0
T74	0	3	0	0
T75	0	1	0	0
T76	0	4	0	0
T77	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	76281	0	0
T8	424352	250	0	0
T9	6991	0	0	0
T10	20595	0	0	0
T11	13539	0	0	0
T12	2950	10	0	0
T13	17737	0	0	0
T26	0	108	0	0
T41	0	54	0	0
T44	0	31	0	0
T49	5368	0	0	0
T50	6864	0	0	0
T63	0	28	0	0
T66	406	0	0	0
T67	523	0	0	0
T74	0	117	0	0
T75	0	74	0	0
T76	0	244	0	0
T77	0	255	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6055507	0	0
T1	7230	6829	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	4815	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	12	0	0
T41	96399	1	0	0
T90	0	1	0	0
T92	0	1	0	0
T93	0	2	0	0
T133	0	1	0	0
T135	11980	0	0	0
T136	1197	0	0	0
T137	8449	0	0	0
T138	670	0	0	0
T139	522	0	0	0
T140	489	0	0	0
T141	33910	0	0	0
T142	490	0	0	0
T143	506	0	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	3	0	0
T147	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	256262	0	0
T12	2950	67	0	0
T13	17737	0	0	0
T26	223679	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T44	0	139	0	0
T49	5368	0	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T63	0	62	0	0
T87	0	33284	0	0
T88	0	123	0	0
T93	0	1	0	0
T129	0	283	0	0
T130	0	90	0	0
T131	0	243	0	0
T132	0	109	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	41	0	0
T12	2950	1	0	0
T13	17737	0	0	0
T26	223679	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T44	0	1	0	0
T49	5368	0	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T63	0	1	0	0
T87	0	2	0	0
T88	0	2	0	0
T93	0	1	0	0
T129	0	2	0	0
T130	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5251527	0	0
T1	7230	6829	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	4815	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5253872	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	105	0	0
T8	424352	5	0	0
T9	6991	0	0	0
T10	20595	0	0	0
T11	13539	0	0	0
T12	2950	1	0	0
T13	17737	0	0	0
T26	0	4	0	0
T41	0	1	0	0
T44	0	1	0	0
T49	5368	0	0	0
T50	6864	0	0	0
T63	0	1	0	0
T66	406	0	0	0
T67	523	0	0	0
T74	0	3	0	0
T75	0	1	0	0
T76	0	4	0	0
T77	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	53	0	0
T12	2950	1	0	0
T13	17737	0	0	0
T26	223679	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T41	0	1	0	0
T44	0	1	0	0
T49	5368	0	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T63	0	1	0	0
T87	0	2	0	0
T92	0	1	0	0
T129	0	2	0	0
T130	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	41	0	0
T12	2950	1	0	0
T13	17737	0	0	0
T26	223679	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T44	0	1	0	0
T49	5368	0	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T63	0	1	0	0
T87	0	2	0	0
T88	0	2	0	0
T93	0	1	0	0
T129	0	2	0	0
T130	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	41	0	0
T12	2950	1	0	0
T13	17737	0	0	0
T26	223679	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T44	0	1	0	0
T49	5368	0	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T63	0	1	0	0
T87	0	2	0	0
T88	0	2	0	0
T93	0	1	0	0
T129	0	2	0	0
T130	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	256221	0	0
T12	2950	66	0	0
T13	17737	0	0	0
T26	223679	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T44	0	138	0	0
T49	5368	0	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T63	0	61	0	0
T87	0	33282	0	0
T88	0	121	0	0
T129	0	281	0	0
T130	0	89	0	0
T131	0	242	0	0
T132	0	108	0	0
T148	0	164	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6058011	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	9046	0	0
T12	2950	632	0	0
T13	17737	0	0	0
T26	223679	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T44	0	96	0	0
T49	5368	0	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T63	0	134	0	0
T87	0	98	0	0
T88	0	133	0	0
T93	0	76	0	0
T129	0	352	0	0
T130	0	334	0	0
T131	0	216	0	0
T132	0	533	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T12,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T12,T26

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T12,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T26
1	0	Covered	T4,T6,T1
1	1	Covered	T8,T12,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T12,T26
0	1	Covered	T44,T87,T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T12,T26
0	1	Unreachable
1	0	Covered	T8,T12,T26

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T12,T26
DetectSt	168	Covered	T8,T12,T26
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T12,T26

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T12,T26
DebounceSt->IdleSt	163	Covered	T63,T77,T80
DetectSt->IdleSt	186	Covered	T44,T87,T88
DetectSt->StableSt	191	Covered	T8,T12,T26
IdleSt->DebounceSt	148	Covered	T8,T12,T26
StableSt->IdleSt	206	Covered	T8,T12,T26

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T12,T26
0	1	Covered	T8,T12,T26
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T12,T26
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T12,T26
IdleSt	0	-	-	-	-	-	-	Covered	T4,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T12,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T63,T77,T87
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T12,T26
DetectSt	-	-	-	-	1	-	-	Covered	T44,T87,T88
DetectSt	-	-	-	-	0	1	-	Covered	T8,T12,T26
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T12,T26
StableSt	-	-	-	-	-	-	0	Covered	T8,T12,T26
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6727276	153	0	0
CntIncr_A	6727276	232667	0	0
CntNoWrap_A	6727276	6055512	0	0
DetectStDropOut_A	6727276	11	0	0
DetectedOut_A	6727276	308805	0	0
DetectedPulseOut_A	6727276	51	0	0
DisabledIdleSt_A	6727276	5251527	0	0
DisabledNoDetection_A	6727276	5253872	0	0
EnterDebounceSt_A	6727276	91	0	0
EnterDetectSt_A	6727276	62	0	0
EnterStableSt_A	6727276	51	0	0
PulseIsPulse_A	6727276	51	0	0
StayInStableSt	6727276	308754	0	0
gen_high_event_sva.HighLevelEvent_A	6727276	6058011	0	0
gen_high_level_sva.HighLevelEvent_A	6727276	6058011	0	0
gen_sticky_sva.StableStDropOut_A	6727276	78884	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	153	0	0
T8	424352	2	0	0
T9	6991	0	0	0
T10	20595	0	0	0
T11	13539	0	0	0
T12	2950	2	0	0
T13	17737	0	0	0
T26	0	2	0	0
T41	0	2	0	0
T44	0	4	0	0
T49	5368	0	0	0
T50	6864	0	0	0
T63	0	3	0	0
T66	406	0	0	0
T67	523	0	0	0
T74	0	4	0	0
T75	0	2	0	0
T76	0	2	0	0
T77	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	232667	0	0
T8	424352	50306	0	0
T9	6991	0	0	0
T10	20595	0	0	0
T11	13539	0	0	0
T12	2950	90	0	0
T13	17737	0	0	0
T26	0	48	0	0
T41	0	52	0	0
T44	0	164	0	0
T49	5368	0	0	0
T50	6864	0	0	0
T63	0	168	0	0
T66	406	0	0	0
T67	523	0	0	0
T74	0	78	0	0
T75	0	47	0	0
T76	0	18	0	0
T77	0	288	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6055512	0	0
T1	7230	6829	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	4815	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	11	0	0
T44	272590	1	0	0
T74	701	0	0	0
T87	0	1	0	0
T88	0	2	0	0
T90	0	1	0	0
T110	2388	0	0	0
T111	29996	0	0	0
T112	519	0	0	0
T113	402	0	0	0
T114	33810	0	0	0
T115	521	0	0	0
T116	501	0	0	0
T134	0	2	0	0
T149	0	1	0	0
T150	0	2	0	0
T151	0	1	0	0
T152	425	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	308805	0	0
T8	424352	252349	0	0
T9	6991	0	0	0
T10	20595	0	0	0
T11	13539	0	0	0
T12	2950	573	0	0
T13	17737	0	0	0
T26	0	271	0	0
T41	0	15	0	0
T44	0	85	0	0
T49	5368	0	0	0
T50	6864	0	0	0
T66	406	0	0	0
T67	523	0	0	0
T74	0	56	0	0
T75	0	42	0	0
T76	0	74	0	0
T92	0	82	0	0
T129	0	358	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	51	0	0
T8	424352	1	0	0
T9	6991	0	0	0
T10	20595	0	0	0
T11	13539	0	0	0
T12	2950	1	0	0
T13	17737	0	0	0
T26	0	1	0	0
T41	0	1	0	0
T44	0	1	0	0
T49	5368	0	0	0
T50	6864	0	0	0
T66	406	0	0	0
T67	523	0	0	0
T74	0	2	0	0
T75	0	1	0	0
T76	0	1	0	0
T92	0	1	0	0
T129	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5251527	0	0
T1	7230	6829	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	4815	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5253872	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	91	0	0
T8	424352	1	0	0
T9	6991	0	0	0
T10	20595	0	0	0
T11	13539	0	0	0
T12	2950	1	0	0
T13	17737	0	0	0
T26	0	1	0	0
T41	0	1	0	0
T44	0	2	0	0
T49	5368	0	0	0
T50	6864	0	0	0
T63	0	3	0	0
T66	406	0	0	0
T67	523	0	0	0
T74	0	2	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	62	0	0
T8	424352	1	0	0
T9	6991	0	0	0
T10	20595	0	0	0
T11	13539	0	0	0
T12	2950	1	0	0
T13	17737	0	0	0
T26	0	1	0	0
T41	0	1	0	0
T44	0	2	0	0
T49	5368	0	0	0
T50	6864	0	0	0
T66	406	0	0	0
T67	523	0	0	0
T74	0	2	0	0
T75	0	1	0	0
T76	0	1	0	0
T92	0	1	0	0
T129	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	51	0	0
T8	424352	1	0	0
T9	6991	0	0	0
T10	20595	0	0	0
T11	13539	0	0	0
T12	2950	1	0	0
T13	17737	0	0	0
T26	0	1	0	0
T41	0	1	0	0
T44	0	1	0	0
T49	5368	0	0	0
T50	6864	0	0	0
T66	406	0	0	0
T67	523	0	0	0
T74	0	2	0	0
T75	0	1	0	0
T76	0	1	0	0
T92	0	1	0	0
T129	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	51	0	0
T8	424352	1	0	0
T9	6991	0	0	0
T10	20595	0	0	0
T11	13539	0	0	0
T12	2950	1	0	0
T13	17737	0	0	0
T26	0	1	0	0
T41	0	1	0	0
T44	0	1	0	0
T49	5368	0	0	0
T50	6864	0	0	0
T66	406	0	0	0
T67	523	0	0	0
T74	0	2	0	0
T75	0	1	0	0
T76	0	1	0	0
T92	0	1	0	0
T129	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	308754	0	0
T8	424352	252348	0	0
T9	6991	0	0	0
T10	20595	0	0	0
T11	13539	0	0	0
T12	2950	572	0	0
T13	17737	0	0	0
T26	0	270	0	0
T41	0	14	0	0
T44	0	84	0	0
T49	5368	0	0	0
T50	6864	0	0	0
T66	406	0	0	0
T67	523	0	0	0
T74	0	54	0	0
T75	0	41	0	0
T76	0	73	0	0
T92	0	81	0	0
T129	0	356	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6058011	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6058011	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	78884	0	0
T8	424352	142	0	0
T9	6991	0	0	0
T10	20595	0	0	0
T11	13539	0	0	0
T12	2950	53	0	0
T13	17737	0	0	0
T26	0	77	0	0
T41	0	66	0	0
T44	0	29	0	0
T49	5368	0	0	0
T50	6864	0	0	0
T66	406	0	0	0
T67	523	0	0	0
T74	0	98	0	0
T75	0	77	0	0
T76	0	255	0	0
T92	0	30	0	0
T129	0	274	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T39,T43,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T39,T43,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T39,T43,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T28,T39,T43
1	0	Covered	T4,T5,T6
1	1	Covered	T39,T43,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T39,T43,T46
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T39,T43,T46
0	1	Covered	T89,T153,T133
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T39,T43,T46
1	-	Covered	T89,T153,T133

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T39,T43,T46
DetectSt	168	Covered	T39,T43,T46
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T39,T43,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T39,T43,T46
DebounceSt->IdleSt	163	Covered	T80,T104,T81
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T39,T43,T46
IdleSt->DebounceSt	148	Covered	T39,T43,T46
StableSt->IdleSt	206	Covered	T39,T89,T84

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T39,T43,T46
0	1	Covered	T39,T43,T46
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T39,T43,T46
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T39,T43,T46
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T39,T43,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T104,T154
DebounceSt	-	0	0	-	-	-	-	Covered	T39,T43,T46
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T39,T43,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T89,T153,T133
StableSt	-	-	-	-	-	-	0	Covered	T39,T43,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6727276	86	0	0
CntIncr_A	6727276	61044	0	0
CntNoWrap_A	6727276	6055579	0	0
DetectStDropOut_A	6727276	0	0	0
DetectedOut_A	6727276	97036	0	0
DetectedPulseOut_A	6727276	41	0	0
DisabledIdleSt_A	6727276	5483696	0	0
DisabledNoDetection_A	6727276	5485988	0	0
EnterDebounceSt_A	6727276	45	0	0
EnterDetectSt_A	6727276	41	0	0
EnterStableSt_A	6727276	41	0	0
PulseIsPulse_A	6727276	41	0	0
StayInStableSt	6727276	96970	0	0
gen_high_level_sva.HighLevelEvent_A	6727276	6058011	0	0
gen_not_sticky_sva.StableStDropOut_A	6727276	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	86	0	0
T39	104582	2	0	0
T40	2115	0	0	0
T43	0	2	0	0
T46	0	2	0	0
T52	652	0	0	0
T61	991	0	0	0
T73	6302	0	0	0
T80	0	1	0	0
T84	0	2	0	0
T89	0	4	0	0
T95	4866	0	0	0
T155	0	2	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	11218	0	0	0
T160	404	0	0	0
T161	422	0	0	0
T162	512	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	61044	0	0
T39	104582	18862	0	0
T40	2115	0	0	0
T43	0	69	0	0
T46	0	29	0	0
T52	652	0	0	0
T61	991	0	0	0
T73	6302	0	0	0
T80	0	34	0	0
T84	0	77	0	0
T89	0	178	0	0
T95	4866	0	0	0
T155	0	40	0	0
T156	0	78	0	0
T157	0	51	0	0
T158	0	16	0	0
T159	11218	0	0	0
T160	404	0	0	0
T161	422	0	0	0
T162	512	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6055579	0	0
T1	7230	6829	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	4815	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	97036	0	0
T39	104582	53655	0	0
T40	2115	0	0	0
T43	0	42	0	0
T46	0	46	0	0
T52	652	0	0	0
T61	991	0	0	0
T73	6302	0	0	0
T84	0	43	0	0
T89	0	252	0	0
T95	4866	0	0	0
T155	0	41	0	0
T156	0	39	0	0
T157	0	49	0	0
T158	0	53	0	0
T159	11218	0	0	0
T160	404	0	0	0
T161	422	0	0	0
T162	512	0	0	0
T163	0	115	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	41	0	0
T39	104582	1	0	0
T40	2115	0	0	0
T43	0	1	0	0
T46	0	1	0	0
T52	652	0	0	0
T61	991	0	0	0
T73	6302	0	0	0
T84	0	1	0	0
T89	0	2	0	0
T95	4866	0	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	11218	0	0	0
T160	404	0	0	0
T161	422	0	0	0
T162	512	0	0	0
T163	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5483696	0	0
T1	7230	6829	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	4815	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5485988	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	45	0	0
T39	104582	1	0	0
T40	2115	0	0	0
T43	0	1	0	0
T46	0	1	0	0
T52	652	0	0	0
T61	991	0	0	0
T73	6302	0	0	0
T80	0	1	0	0
T84	0	1	0	0
T89	0	2	0	0
T95	4866	0	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	11218	0	0	0
T160	404	0	0	0
T161	422	0	0	0
T162	512	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	41	0	0
T39	104582	1	0	0
T40	2115	0	0	0
T43	0	1	0	0
T46	0	1	0	0
T52	652	0	0	0
T61	991	0	0	0
T73	6302	0	0	0
T84	0	1	0	0
T89	0	2	0	0
T95	4866	0	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	11218	0	0	0
T160	404	0	0	0
T161	422	0	0	0
T162	512	0	0	0
T163	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	41	0	0
T39	104582	1	0	0
T40	2115	0	0	0
T43	0	1	0	0
T46	0	1	0	0
T52	652	0	0	0
T61	991	0	0	0
T73	6302	0	0	0
T84	0	1	0	0
T89	0	2	0	0
T95	4866	0	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	11218	0	0	0
T160	404	0	0	0
T161	422	0	0	0
T162	512	0	0	0
T163	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	41	0	0
T39	104582	1	0	0
T40	2115	0	0	0
T43	0	1	0	0
T46	0	1	0	0
T52	652	0	0	0
T61	991	0	0	0
T73	6302	0	0	0
T84	0	1	0	0
T89	0	2	0	0
T95	4866	0	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	11218	0	0	0
T160	404	0	0	0
T161	422	0	0	0
T162	512	0	0	0
T163	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	96970	0	0
T39	104582	53653	0	0
T40	2115	0	0	0
T43	0	40	0	0
T46	0	44	0	0
T52	652	0	0	0
T61	991	0	0	0
T73	6302	0	0	0
T84	0	41	0	0
T89	0	249	0	0
T95	4866	0	0	0
T155	0	39	0	0
T156	0	37	0	0
T157	0	47	0	0
T158	0	51	0	0
T159	11218	0	0	0
T160	404	0	0	0
T161	422	0	0	0
T162	512	0	0	0
T163	0	113	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6058011	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	16	0	0
T89	21846	1	0	0
T133	0	1	0	0
T145	0	1	0	0
T153	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	2	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	526	0	0	0
T171	508	0	0	0
T172	8402	0	0	0
T173	928	0	0	0
T174	460	0	0	0
T175	408	0	0	0
T176	492	0	0	0
T177	1294	0	0	0
T178	4405	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T13,T43,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T13,T43,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T13,T43,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T43,T41
1	0	Covered	T4,T6,T14
1	1	Covered	T13,T43,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T43,T41
0	1	Covered	T84
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T43,T41
0	1	Covered	T13,T43,T46
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T43,T41
1	-	Covered	T13,T43,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T13,T43,T41
DetectSt	168	Covered	T13,T43,T41
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T13,T43,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T13,T43,T41
DebounceSt->IdleSt	163	Covered	T80,T89,T179
DetectSt->IdleSt	186	Covered	T84
DetectSt->StableSt	191	Covered	T13,T43,T41
IdleSt->DebounceSt	148	Covered	T13,T43,T41
StableSt->IdleSt	206	Covered	T13,T43,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T43,T41
0	1	Covered	T13,T43,T41
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T43,T41
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T43,T41
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T43,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T89,T179,T130
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T43,T41
DetectSt	-	-	-	-	1	-	-	Covered	T84
DetectSt	-	-	-	-	0	1	-	Covered	T13,T43,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T13,T43,T46
StableSt	-	-	-	-	-	-	0	Covered	T13,T43,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6727276	122	0	0
CntIncr_A	6727276	148371	0	0
CntNoWrap_A	6727276	6055543	0	0
DetectStDropOut_A	6727276	1	0	0
DetectedOut_A	6727276	102834	0	0
DetectedPulseOut_A	6727276	56	0	0
DisabledIdleSt_A	6727276	5585061	0	0
DisabledNoDetection_A	6727276	5587358	0	0
EnterDebounceSt_A	6727276	65	0	0
EnterDetectSt_A	6727276	57	0	0
EnterStableSt_A	6727276	56	0	0
PulseIsPulse_A	6727276	56	0	0
StayInStableSt	6727276	102759	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6727276	2779	0	0
gen_low_level_sva.LowLevelEvent_A	6727276	6058011	0	0
gen_not_sticky_sva.StableStDropOut_A	6727276	37	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	122	0	0
T13	17737	2	0	0
T26	223679	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T41	0	2	0	0
T42	0	4	0	0
T43	0	2	0	0
T44	0	4	0	0
T46	0	2	0	0
T47	0	6	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T80	0	1	0	0
T89	0	3	0	0
T180	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	148371	0	0
T13	17737	64	0	0
T26	223679	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T41	0	77	0	0
T42	0	74	0	0
T43	0	69	0	0
T44	0	64832	0	0
T46	0	29	0	0
T47	0	226	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T80	0	35	0	0
T89	0	178	0	0
T180	0	146	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6055543	0	0
T1	7230	6829	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	4815	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	1	0	0
T84	26244	1	0	0
T158	569	0	0	0
T181	17628	0	0	0
T182	678	0	0	0
T183	417	0	0	0
T184	402	0	0	0
T185	404	0	0	0
T186	950	0	0	0
T187	422	0	0	0
T188	406	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	102834	0	0
T13	17737	40	0	0
T26	223679	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T41	0	186	0	0
T42	0	60	0	0
T43	0	37	0	0
T44	0	67560	0	0
T46	0	91	0	0
T47	0	203	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T89	0	85	0	0
T177	0	243	0	0
T180	0	225	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	56	0	0
T13	17737	1	0	0
T26	223679	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	2	0	0
T46	0	1	0	0
T47	0	3	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T89	0	1	0	0
T177	0	2	0	0
T180	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5585061	0	0
T1	7230	6829	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	4815	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5587358	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	65	0	0
T13	17737	1	0	0
T26	223679	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	2	0	0
T46	0	1	0	0
T47	0	3	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T80	0	1	0	0
T89	0	2	0	0
T180	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	57	0	0
T13	17737	1	0	0
T26	223679	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	2	0	0
T46	0	1	0	0
T47	0	3	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T89	0	1	0	0
T177	0	2	0	0
T180	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	56	0	0
T13	17737	1	0	0
T26	223679	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	2	0	0
T46	0	1	0	0
T47	0	3	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T89	0	1	0	0
T177	0	2	0	0
T180	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	56	0	0
T13	17737	1	0	0
T26	223679	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	2	0	0
T46	0	1	0	0
T47	0	3	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T89	0	1	0	0
T177	0	2	0	0
T180	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	102759	0	0
T13	17737	39	0	0
T26	223679	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T41	0	184	0	0
T42	0	57	0	0
T43	0	36	0	0
T44	0	67557	0	0
T46	0	90	0	0
T47	0	200	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T89	0	84	0	0
T177	0	240	0	0
T180	0	223	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	2779	0	0
T1	7230	0	0	0
T4	26326	52	0	0
T5	652	0	0	0
T6	507	2	0	0
T14	539	5	0	0
T15	501	5	0	0
T16	742	0	0	0
T17	428	2	0	0
T18	493	5	0	0
T19	5216	0	0	0
T20	0	5	0	0
T21	0	6	0	0
T65	0	2	0	0
T68	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6058011	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	37	0	0
T13	17737	1	0	0
T26	223679	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T47	0	3	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T89	0	1	0	0
T177	0	1	0	0
T180	0	2	0	0
T189	0	2	0	0