Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T13,T27,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T13,T27,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T13,T27,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T27,T28
1	0	Covered	T4,T6,T1
1	1	Covered	T13,T27,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T27,T28
0	1	Covered	T245
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T27,T28
0	1	Covered	T13,T27,T39
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T27,T28
1	-	Covered	T13,T27,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T13,T27,T28
DetectSt	168	Covered	T13,T27,T28
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T13,T27,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T13,T27,T28
DebounceSt->IdleSt	163	Covered	T46,T80,T179
DetectSt->IdleSt	186	Covered	T245
DetectSt->StableSt	191	Covered	T13,T27,T28
IdleSt->DebounceSt	148	Covered	T13,T27,T28
StableSt->IdleSt	206	Covered	T13,T27,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T27,T28
0	1	Covered	T13,T27,T28
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T27,T28
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T27,T28
IdleSt	0	-	-	-	-	-	-	Covered	T4,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T27,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T46,T179,T191
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T27,T28
DetectSt	-	-	-	-	1	-	-	Covered	T245
DetectSt	-	-	-	-	0	1	-	Covered	T13,T27,T28
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T13,T27,T39
StableSt	-	-	-	-	-	-	0	Covered	T13,T27,T28
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6727276	135	0	0
CntIncr_A	6727276	103216	0	0
CntNoWrap_A	6727276	6055530	0	0
DetectStDropOut_A	6727276	1	0	0
DetectedOut_A	6727276	39813	0	0
DetectedPulseOut_A	6727276	62	0	0
DisabledIdleSt_A	6727276	5742274	0	0
DisabledNoDetection_A	6727276	5744561	0	0
EnterDebounceSt_A	6727276	73	0	0
EnterDetectSt_A	6727276	63	0	0
EnterStableSt_A	6727276	62	0	0
PulseIsPulse_A	6727276	62	0	0
StayInStableSt	6727276	39720	0	0
gen_high_level_sva.HighLevelEvent_A	6727276	6058011	0	0
gen_not_sticky_sva.StableStDropOut_A	6727276	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	135	0	0
T13	17737	4	0	0
T26	223679	0	0	0
T27	1163	4	0	0
T28	0	2	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T39	0	2	0	0
T43	0	2	0	0
T46	0	3	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T80	0	1	0	0
T156	0	4	0	0
T173	0	4	0	0
T177	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	103216	0	0
T13	17737	128	0	0
T26	223679	0	0	0
T27	1163	172	0	0
T28	0	98	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T39	0	18862	0	0
T43	0	69	0	0
T46	0	58	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T80	0	34	0	0
T156	0	156	0	0
T173	0	168	0	0
T177	0	174	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6055530	0	0
T1	7230	6829	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	4815	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	1	0	0
T245	22948	1	0	0
T246	530	0	0	0
T247	403	0	0	0
T248	864	0	0	0
T249	1499	0	0	0
T250	522	0	0	0
T251	496	0	0	0
T252	786	0	0	0
T253	413	0	0	0
T254	513	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	39813	0	0
T13	17737	113	0	0
T26	223679	0	0	0
T27	1163	241	0	0
T28	0	39	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T39	0	34746	0	0
T43	0	36	0	0
T46	0	167	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T156	0	81	0	0
T173	0	81	0	0
T177	0	159	0	0
T206	0	108	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	62	0	0
T13	17737	2	0	0
T26	223679	0	0	0
T27	1163	2	0	0
T28	0	1	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T46	0	1	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T156	0	2	0	0
T173	0	2	0	0
T177	0	2	0	0
T206	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5742274	0	0
T1	7230	6829	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	4815	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5744561	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	73	0	0
T13	17737	2	0	0
T26	223679	0	0	0
T27	1163	2	0	0
T28	0	1	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T46	0	2	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T80	0	1	0	0
T156	0	2	0	0
T173	0	2	0	0
T177	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	63	0	0
T13	17737	2	0	0
T26	223679	0	0	0
T27	1163	2	0	0
T28	0	1	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T46	0	1	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T156	0	2	0	0
T173	0	2	0	0
T177	0	2	0	0
T206	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	62	0	0
T13	17737	2	0	0
T26	223679	0	0	0
T27	1163	2	0	0
T28	0	1	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T46	0	1	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T156	0	2	0	0
T173	0	2	0	0
T177	0	2	0	0
T206	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	62	0	0
T13	17737	2	0	0
T26	223679	0	0	0
T27	1163	2	0	0
T28	0	1	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T46	0	1	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T156	0	2	0	0
T173	0	2	0	0
T177	0	2	0	0
T206	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	39720	0	0
T13	17737	111	0	0
T26	223679	0	0	0
T27	1163	238	0	0
T28	0	37	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T39	0	34745	0	0
T43	0	35	0	0
T46	0	165	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T156	0	78	0	0
T173	0	78	0	0
T177	0	157	0	0
T206	0	105	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6058011	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	31	0	0
T13	17737	2	0	0
T26	223679	0	0	0
T27	1163	1	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T130	0	1	0	0
T156	0	1	0	0
T173	0	1	0	0
T177	0	2	0	0
T179	0	2	0	0
T206	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T6,T1
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T1
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T13,T39,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T13,T39,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T13,T39,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T28,T39
1	0	Covered	T4,T6,T1
1	1	Covered	T13,T39,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T39,T43
0	1	Covered	T40
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T39,T43
0	1	Covered	T46,T156,T47
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T39,T43
1	-	Covered	T46,T156,T47

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T13,T39,T40
DetectSt	168	Covered	T13,T39,T40
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T13,T39,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T13,T39,T40
DebounceSt->IdleSt	163	Covered	T13,T80,T206
DetectSt->IdleSt	186	Covered	T40
DetectSt->StableSt	191	Covered	T13,T39,T43
IdleSt->DebounceSt	148	Covered	T13,T39,T40
StableSt->IdleSt	206	Covered	T13,T39,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T39,T40
0	1	Covered	T13,T39,T40
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T39,T40
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T39,T40
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T39,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T13,T206,T130
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T39,T40
DetectSt	-	-	-	-	1	-	-	Covered	T40
DetectSt	-	-	-	-	0	1	-	Covered	T13,T39,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T46,T156,T47
StableSt	-	-	-	-	-	-	0	Covered	T13,T39,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6727276	74	0	0
CntIncr_A	6727276	20998	0	0
CntNoWrap_A	6727276	6055591	0	0
DetectStDropOut_A	6727276	1	0	0
DetectedOut_A	6727276	2486	0	0
DetectedPulseOut_A	6727276	32	0	0
DisabledIdleSt_A	6727276	5934540	0	0
DisabledNoDetection_A	6727276	5936832	0	0
EnterDebounceSt_A	6727276	42	0	0
EnterDetectSt_A	6727276	33	0	0
EnterStableSt_A	6727276	32	0	0
PulseIsPulse_A	6727276	32	0	0
StayInStableSt	6727276	2439	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6727276	6406	0	0
gen_low_level_sva.LowLevelEvent_A	6727276	6058011	0	0
gen_not_sticky_sva.StableStDropOut_A	6727276	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	74	0	0
T13	17737	3	0	0
T26	223679	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T39	0	2	0	0
T40	0	2	0	0
T43	0	2	0	0
T46	0	2	0	0
T47	0	4	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T80	0	1	0	0
T156	0	2	0	0
T157	0	2	0	0
T173	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	20998	0	0
T13	17737	128	0	0
T26	223679	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T39	0	18862	0	0
T40	0	92	0	0
T43	0	69	0	0
T46	0	29	0	0
T47	0	150	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T80	0	35	0	0
T156	0	78	0	0
T157	0	51	0	0
T173	0	84	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6055591	0	0
T1	7230	6829	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	4815	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	1	0	0
T40	2115	1	0	0
T52	652	0	0	0
T61	991	0	0	0
T73	6302	0	0	0
T95	4866	0	0	0
T126	8158	0	0	0
T159	11218	0	0	0
T160	404	0	0	0
T161	422	0	0	0
T162	512	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	2486	0	0
T13	17737	42	0	0
T26	223679	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T39	0	45	0	0
T43	0	42	0	0
T46	0	72	0	0
T47	0	7	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T87	0	163	0	0
T156	0	6	0	0
T157	0	50	0	0
T173	0	16	0	0
T179	0	86	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	32	0	0
T13	17737	1	0	0
T26	223679	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T87	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T173	0	1	0	0
T179	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5934540	0	0
T1	7230	6829	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	4815	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5936832	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	42	0	0
T13	17737	2	0	0
T26	223679	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T80	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T173	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	33	0	0
T13	17737	1	0	0
T26	223679	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T156	0	1	0	0
T157	0	1	0	0
T173	0	1	0	0
T179	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	32	0	0
T13	17737	1	0	0
T26	223679	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T87	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T173	0	1	0	0
T179	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	32	0	0
T13	17737	1	0	0
T26	223679	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T87	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T173	0	1	0	0
T179	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	2439	0	0
T13	17737	40	0	0
T26	223679	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T39	0	43	0	0
T43	0	40	0	0
T46	0	71	0	0
T47	0	5	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T87	0	162	0	0
T156	0	5	0	0
T157	0	48	0	0
T173	0	15	0	0
T179	0	83	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6406	0	0
T1	7230	31	0	0
T2	0	13	0	0
T4	26326	52	0	0
T5	652	0	0	0
T6	507	5	0	0
T14	539	3	0	0
T15	501	5	0	0
T16	742	0	0	0
T17	428	2	0	0
T18	493	8	0	0
T19	5216	23	0	0
T20	0	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6058011	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	17	0	0
T44	272590	0	0	0
T46	734	1	0	0
T47	0	2	0	0
T74	701	0	0	0
T87	0	1	0	0
T96	12432	0	0	0
T110	2388	0	0	0
T111	29996	0	0	0
T112	519	0	0	0
T113	402	0	0	0
T156	0	1	0	0
T164	0	1	0	0
T173	0	1	0	0
T179	0	1	0	0
T190	0	1	0	0
T193	437	0	0	0
T194	28135	0	0	0
T221	0	1	0	0
T228	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T27,T28,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T27,T28,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T27,T28,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T28,T40
1	0	Covered	T4,T6,T1
1	1	Covered	T27,T28,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T28,T40
0	1	Covered	T90,T91
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T27,T28,T40
0	1	Covered	T27,T28,T40
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T27,T28,T40
1	-	Covered	T27,T28,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T27,T28,T40
DetectSt	168	Covered	T27,T28,T40
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T27,T28,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T27,T28,T40
DebounceSt->IdleSt	163	Covered	T41,T45,T205
DetectSt->IdleSt	186	Covered	T90,T91
DetectSt->StableSt	191	Covered	T27,T28,T40
IdleSt->DebounceSt	148	Covered	T27,T28,T40
StableSt->IdleSt	206	Covered	T27,T28,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T27,T28,T40
0	1	Covered	T27,T28,T40
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T28,T40
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T27,T28,T40
IdleSt	0	-	-	-	-	-	-	Covered	T4,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T27,T28,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T41,T45,T205
DebounceSt	-	0	0	-	-	-	-	Covered	T27,T28,T40
DetectSt	-	-	-	-	1	-	-	Covered	T90,T91
DetectSt	-	-	-	-	0	1	-	Covered	T27,T28,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T27,T28,T40
StableSt	-	-	-	-	-	-	0	Covered	T27,T28,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6727276	107	0	0
CntIncr_A	6727276	83290	0	0
CntNoWrap_A	6727276	6055558	0	0
DetectStDropOut_A	6727276	2	0	0
DetectedOut_A	6727276	3567	0	0
DetectedPulseOut_A	6727276	48	0	0
DisabledIdleSt_A	6727276	5583494	0	0
DisabledNoDetection_A	6727276	5585787	0	0
EnterDebounceSt_A	6727276	58	0	0
EnterDetectSt_A	6727276	50	0	0
EnterStableSt_A	6727276	48	0	0
PulseIsPulse_A	6727276	48	0	0
StayInStableSt	6727276	3504	0	0
gen_high_level_sva.HighLevelEvent_A	6727276	6058011	0	0
gen_not_sticky_sva.StableStDropOut_A	6727276	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	107	0	0
T26	223679	0	0	0
T27	1163	4	0	0
T28	705	2	0	0
T36	19631	0	0	0
T39	104582	0	0	0
T40	0	4	0	0
T41	0	1	0	0
T45	0	3	0	0
T47	0	4	0	0
T51	65086	0	0	0
T70	522	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T78	8664	0	0	0
T80	0	1	0	0
T157	0	2	0	0
T173	0	4	0	0
T205	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	83290	0	0
T26	223679	0	0	0
T27	1163	172	0	0
T28	705	98	0	0
T36	19631	0	0	0
T39	104582	0	0	0
T40	0	184	0	0
T41	0	77	0	0
T45	0	192	0	0
T47	0	152	0	0
T51	65086	0	0	0
T70	522	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T78	8664	0	0	0
T80	0	35	0	0
T157	0	51	0	0
T173	0	168	0	0
T205	0	83	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6055558	0	0
T1	7230	6829	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	4815	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	2	0	0
T90	152408	1	0	0
T91	0	1	0	0
T103	22611	0	0	0
T148	6592	0	0	0
T195	15573	0	0	0
T255	11193	0	0	0
T256	641	0	0	0
T257	427	0	0	0
T258	417	0	0	0
T259	422	0	0	0
T260	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	3567	0	0
T26	223679	0	0	0
T27	1163	380	0	0
T28	705	60	0	0
T36	19631	0	0	0
T39	104582	0	0	0
T40	0	92	0	0
T45	0	245	0	0
T47	0	322	0	0
T51	65086	0	0	0
T70	522	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T78	8664	0	0	0
T130	0	56	0	0
T157	0	69	0	0
T173	0	100	0	0
T189	0	201	0	0
T206	0	51	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	48	0	0
T26	223679	0	0	0
T27	1163	2	0	0
T28	705	1	0	0
T36	19631	0	0	0
T39	104582	0	0	0
T40	0	2	0	0
T45	0	1	0	0
T47	0	2	0	0
T51	65086	0	0	0
T70	522	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T78	8664	0	0	0
T130	0	1	0	0
T157	0	1	0	0
T173	0	2	0	0
T189	0	2	0	0
T206	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5583494	0	0
T1	7230	6829	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	4815	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5585787	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	58	0	0
T26	223679	0	0	0
T27	1163	2	0	0
T28	705	1	0	0
T36	19631	0	0	0
T39	104582	0	0	0
T40	0	2	0	0
T41	0	1	0	0
T45	0	2	0	0
T47	0	2	0	0
T51	65086	0	0	0
T70	522	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T78	8664	0	0	0
T80	0	1	0	0
T157	0	1	0	0
T173	0	2	0	0
T205	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	50	0	0
T26	223679	0	0	0
T27	1163	2	0	0
T28	705	1	0	0
T36	19631	0	0	0
T39	104582	0	0	0
T40	0	2	0	0
T45	0	1	0	0
T47	0	2	0	0
T51	65086	0	0	0
T70	522	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T78	8664	0	0	0
T130	0	1	0	0
T157	0	1	0	0
T173	0	2	0	0
T189	0	2	0	0
T206	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	48	0	0
T26	223679	0	0	0
T27	1163	2	0	0
T28	705	1	0	0
T36	19631	0	0	0
T39	104582	0	0	0
T40	0	2	0	0
T45	0	1	0	0
T47	0	2	0	0
T51	65086	0	0	0
T70	522	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T78	8664	0	0	0
T130	0	1	0	0
T157	0	1	0	0
T173	0	2	0	0
T189	0	2	0	0
T206	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	48	0	0
T26	223679	0	0	0
T27	1163	2	0	0
T28	705	1	0	0
T36	19631	0	0	0
T39	104582	0	0	0
T40	0	2	0	0
T45	0	1	0	0
T47	0	2	0	0
T51	65086	0	0	0
T70	522	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T78	8664	0	0	0
T130	0	1	0	0
T157	0	1	0	0
T173	0	2	0	0
T189	0	2	0	0
T206	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	3504	0	0
T26	223679	0	0	0
T27	1163	377	0	0
T28	705	59	0	0
T36	19631	0	0	0
T39	104582	0	0	0
T40	0	89	0	0
T45	0	244	0	0
T47	0	319	0	0
T51	65086	0	0	0
T70	522	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T78	8664	0	0	0
T130	0	55	0	0
T157	0	68	0	0
T173	0	98	0	0
T189	0	198	0	0
T206	0	48	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6058011	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	33	0	0
T26	223679	0	0	0
T27	1163	1	0	0
T28	705	1	0	0
T36	19631	0	0	0
T39	104582	0	0	0
T40	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T51	65086	0	0	0
T70	522	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T78	8664	0	0	0
T130	0	1	0	0
T157	0	1	0	0
T173	0	2	0	0
T189	0	1	0	0
T206	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T6,T1
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T1
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T27,T40,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T27,T40,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T27,T41,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T40,T41
1	0	Covered	T4,T6,T1
1	1	Covered	T27,T40,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T41,T42
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T41,T42,T45
0	1	Covered	T27,T42,T45
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T41,T42,T45
1	-	Covered	T27,T42,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T27,T40,T41
DetectSt	168	Covered	T27,T41,T42
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T27,T41,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T27,T41,T42
DebounceSt->IdleSt	163	Covered	T40,T80,T81
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T27,T41,T42
IdleSt->DebounceSt	148	Covered	T27,T40,T41
StableSt->IdleSt	206	Covered	T27,T42,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T27,T40,T41
0	1	Covered	T27,T40,T41
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T41,T42
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T27,T40,T41
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T27,T41,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T40
DebounceSt	-	0	0	-	-	-	-	Covered	T27,T40,T41
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T27,T41,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T27,T42,T45
StableSt	-	-	-	-	-	-	0	Covered	T41,T42,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6727276	89	0	0
CntIncr_A	6727276	2835	0	0
CntNoWrap_A	6727276	6055576	0	0
DetectStDropOut_A	6727276	0	0	0
DetectedOut_A	6727276	2799	0	0
DetectedPulseOut_A	6727276	43	0	0
DisabledIdleSt_A	6727276	6036010	0	0
DisabledNoDetection_A	6727276	6038301	0	0
EnterDebounceSt_A	6727276	46	0	0
EnterDetectSt_A	6727276	43	0	0
EnterStableSt_A	6727276	43	0	0
PulseIsPulse_A	6727276	43	0	0
StayInStableSt	6727276	2732	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6727276	6372	0	0
gen_low_level_sva.LowLevelEvent_A	6727276	6058011	0	0
gen_not_sticky_sva.StableStDropOut_A	6727276	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	89	0	0
T26	223679	0	0	0
T27	1163	2	0	0
T28	705	0	0	0
T36	19631	0	0	0
T39	104582	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	2	0	0
T45	0	4	0	0
T47	0	4	0	0
T51	65086	0	0	0
T70	522	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T78	8664	0	0	0
T80	0	1	0	0
T173	0	4	0	0
T177	0	4	0	0
T205	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	2835	0	0
T26	223679	0	0	0
T27	1163	86	0	0
T28	705	0	0	0
T36	19631	0	0	0
T39	104582	0	0	0
T40	0	92	0	0
T41	0	77	0	0
T42	0	37	0	0
T45	0	192	0	0
T47	0	150	0	0
T51	65086	0	0	0
T70	522	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T78	8664	0	0	0
T80	0	34	0	0
T173	0	168	0	0
T177	0	174	0	0
T205	0	83	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6055576	0	0
T1	7230	6829	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	4815	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	2799	0	0
T26	223679	0	0	0
T27	1163	1	0	0
T28	705	0	0	0
T36	19631	0	0	0
T39	104582	0	0	0
T41	0	108	0	0
T42	0	42	0	0
T45	0	78	0	0
T47	0	92	0	0
T51	65086	0	0	0
T70	522	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T78	8664	0	0	0
T87	0	40	0	0
T173	0	80	0	0
T177	0	257	0	0
T179	0	365	0	0
T205	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	43	0	0
T26	223679	0	0	0
T27	1163	1	0	0
T28	705	0	0	0
T36	19631	0	0	0
T39	104582	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	2	0	0
T47	0	2	0	0
T51	65086	0	0	0
T70	522	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T78	8664	0	0	0
T87	0	1	0	0
T173	0	2	0	0
T177	0	2	0	0
T179	0	4	0	0
T205	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6036010	0	0
T1	7230	6829	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	4815	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6038301	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	46	0	0
T26	223679	0	0	0
T27	1163	1	0	0
T28	705	0	0	0
T36	19631	0	0	0
T39	104582	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	2	0	0
T47	0	2	0	0
T51	65086	0	0	0
T70	522	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T78	8664	0	0	0
T80	0	1	0	0
T173	0	2	0	0
T177	0	2	0	0
T205	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	43	0	0
T26	223679	0	0	0
T27	1163	1	0	0
T28	705	0	0	0
T36	19631	0	0	0
T39	104582	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	2	0	0
T47	0	2	0	0
T51	65086	0	0	0
T70	522	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T78	8664	0	0	0
T87	0	1	0	0
T173	0	2	0	0
T177	0	2	0	0
T179	0	4	0	0
T205	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	43	0	0
T26	223679	0	0	0
T27	1163	1	0	0
T28	705	0	0	0
T36	19631	0	0	0
T39	104582	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	2	0	0
T47	0	2	0	0
T51	65086	0	0	0
T70	522	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T78	8664	0	0	0
T87	0	1	0	0
T173	0	2	0	0
T177	0	2	0	0
T179	0	4	0	0
T205	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	43	0	0
T26	223679	0	0	0
T27	1163	1	0	0
T28	705	0	0	0
T36	19631	0	0	0
T39	104582	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	2	0	0
T47	0	2	0	0
T51	65086	0	0	0
T70	522	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T78	8664	0	0	0
T87	0	1	0	0
T173	0	2	0	0
T177	0	2	0	0
T179	0	4	0	0
T205	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	2732	0	0
T41	96399	106	0	0
T42	0	41	0	0
T45	0	75	0	0
T47	0	89	0	0
T87	0	38	0	0
T135	11980	0	0	0
T136	1197	0	0	0
T137	8449	0	0	0
T138	670	0	0	0
T139	522	0	0	0
T140	489	0	0	0
T141	33910	0	0	0
T142	490	0	0	0
T143	506	0	0	0
T173	0	77	0	0
T177	0	255	0	0
T179	0	358	0	0
T189	0	147	0	0
T205	0	41	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6372	0	0
T1	7230	23	0	0
T2	0	11	0	0
T4	26326	48	0	0
T5	652	0	0	0
T6	507	6	0	0
T14	539	5	0	0
T15	501	3	0	0
T16	742	0	0	0
T17	428	2	0	0
T18	493	9	0	0
T19	5216	25	0	0
T20	0	9	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6058011	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	19	0	0
T26	223679	0	0	0
T27	1163	1	0	0
T28	705	0	0	0
T36	19631	0	0	0
T39	104582	0	0	0
T42	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T51	65086	0	0	0
T70	522	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T78	8664	0	0	0
T104	0	1	0	0
T133	0	1	0	0
T173	0	1	0	0
T177	0	2	0	0
T179	0	1	0	0
T189	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T13,T39,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T13,T39,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T13,T39,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T39,T46
1	0	Covered	T4,T5,T6
1	1	Covered	T13,T39,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T39,T46
0	1	Covered	T89
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T39,T46
0	1	Covered	T13,T39,T44
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T39,T46
1	-	Covered	T13,T39,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T13,T39,T46
DetectSt	168	Covered	T13,T39,T46
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T13,T39,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T13,T39,T46
DebounceSt->IdleSt	163	Covered	T42,T80,T232
DetectSt->IdleSt	186	Covered	T89
DetectSt->StableSt	191	Covered	T13,T39,T46
IdleSt->DebounceSt	148	Covered	T13,T39,T46
StableSt->IdleSt	206	Covered	T13,T39,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T39,T46
0	1	Covered	T13,T39,T46
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T39,T46
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T39,T46
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T39,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T42,T232,T261
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T39,T46
DetectSt	-	-	-	-	1	-	-	Covered	T89
DetectSt	-	-	-	-	0	1	-	Covered	T13,T39,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T13,T39,T44
StableSt	-	-	-	-	-	-	0	Covered	T13,T39,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6727276	124	0	0
CntIncr_A	6727276	87335	0	0
CntNoWrap_A	6727276	6055541	0	0
DetectStDropOut_A	6727276	1	0	0
DetectedOut_A	6727276	151896	0	0
DetectedPulseOut_A	6727276	58	0	0
DisabledIdleSt_A	6727276	5672439	0	0
DisabledNoDetection_A	6727276	5674730	0	0
EnterDebounceSt_A	6727276	66	0	0
EnterDetectSt_A	6727276	59	0	0
EnterStableSt_A	6727276	58	0	0
PulseIsPulse_A	6727276	58	0	0
StayInStableSt	6727276	151811	0	0
gen_high_level_sva.HighLevelEvent_A	6727276	6058011	0	0
gen_not_sticky_sva.StableStDropOut_A	6727276	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	124	0	0
T13	17737	4	0	0
T26	223679	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T39	0	2	0	0
T42	0	3	0	0
T44	0	6	0	0
T46	0	2	0	0
T47	0	2	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T80	0	1	0	0
T89	0	4	0	0
T156	0	4	0	0
T157	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	87335	0	0
T13	17737	128	0	0
T26	223679	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T39	0	18862	0	0
T42	0	74	0	0
T44	0	64899	0	0
T46	0	29	0	0
T47	0	76	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T80	0	34	0	0
T89	0	178	0	0
T156	0	156	0	0
T157	0	51	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6055541	0	0
T1	7230	6829	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	4815	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	1	0	0
T89	21846	1	0	0
T170	526	0	0	0
T171	508	0	0	0
T172	8402	0	0	0
T173	928	0	0	0
T174	460	0	0	0
T175	408	0	0	0
T176	492	0	0	0
T177	1294	0	0	0
T178	4405	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	151896	0	0
T13	17737	234	0	0
T26	223679	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T39	0	15845	0	0
T42	0	59	0	0
T44	0	130679	0	0
T46	0	269	0	0
T47	0	400	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T89	0	42	0	0
T156	0	82	0	0
T157	0	74	0	0
T177	0	372	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	58	0	0
T13	17737	2	0	0
T26	223679	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T39	0	1	0	0
T42	0	1	0	0
T44	0	3	0	0
T46	0	1	0	0
T47	0	1	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T89	0	1	0	0
T156	0	2	0	0
T157	0	1	0	0
T177	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5672439	0	0
T1	7230	6829	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	4815	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5674730	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	66	0	0
T13	17737	2	0	0
T26	223679	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T39	0	1	0	0
T42	0	2	0	0
T44	0	3	0	0
T46	0	1	0	0
T47	0	1	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T80	0	1	0	0
T89	0	2	0	0
T156	0	2	0	0
T157	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	59	0	0
T13	17737	2	0	0
T26	223679	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T39	0	1	0	0
T42	0	1	0	0
T44	0	3	0	0
T46	0	1	0	0
T47	0	1	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T89	0	2	0	0
T156	0	2	0	0
T157	0	1	0	0
T177	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	58	0	0
T13	17737	2	0	0
T26	223679	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T39	0	1	0	0
T42	0	1	0	0
T44	0	3	0	0
T46	0	1	0	0
T47	0	1	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T89	0	1	0	0
T156	0	2	0	0
T157	0	1	0	0
T177	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	58	0	0
T13	17737	2	0	0
T26	223679	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T39	0	1	0	0
T42	0	1	0	0
T44	0	3	0	0
T46	0	1	0	0
T47	0	1	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T89	0	1	0	0
T156	0	2	0	0
T157	0	1	0	0
T177	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	151811	0	0
T13	17737	231	0	0
T26	223679	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T39	0	15844	0	0
T42	0	57	0	0
T44	0	130675	0	0
T46	0	267	0	0
T47	0	398	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T89	0	40	0	0
T156	0	79	0	0
T157	0	72	0	0
T177	0	369	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6058011	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	31	0	0
T13	17737	1	0	0
T26	223679	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T36	19631	0	0	0
T39	0	1	0	0
T44	0	2	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T156	0	1	0	0
T158	0	1	0	0
T163	0	1	0	0
T177	0	1	0	0
T189	0	1	0	0
T190	0	1	0	0
T228	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T27,T39,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T27,T39,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T27,T39,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T28,T39
1	0	Covered	T4,T5,T6
1	1	Covered	T27,T39,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T39,T40
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T27,T39,T40
0	1	Covered	T40,T180,T173
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T27,T39,T40
1	-	Covered	T40,T180,T173

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T27,T39,T40
DetectSt	168	Covered	T27,T39,T40
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T27,T39,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T27,T39,T40
DebounceSt->IdleSt	163	Covered	T27,T80,T81
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T27,T39,T40
IdleSt->DebounceSt	148	Covered	T27,T39,T40
StableSt->IdleSt	206	Covered	T39,T40,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T27,T39,T40
0	1	Covered	T27,T39,T40
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T39,T40
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T27,T39,T40
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T27,T39,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T27,T262
DebounceSt	-	0	0	-	-	-	-	Covered	T27,T39,T40
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T27,T39,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T180,T173
StableSt	-	-	-	-	-	-	0	Covered	T27,T39,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6727276	62	0	0
CntIncr_A	6727276	125412	0	0
CntNoWrap_A	6727276	6055603	0	0
DetectStDropOut_A	6727276	0	0	0
DetectedOut_A	6727276	28129	0	0
DetectedPulseOut_A	6727276	29	0	0
DisabledIdleSt_A	6727276	5481135	0	0
DisabledNoDetection_A	6727276	5483427	0	0
EnterDebounceSt_A	6727276	34	0	0
EnterDetectSt_A	6727276	29	0	0
EnterStableSt_A	6727276	29	0	0
PulseIsPulse_A	6727276	29	0	0
StayInStableSt	6727276	28084	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6727276	7076	0	0
gen_low_level_sva.LowLevelEvent_A	6727276	6058011	0	0
gen_not_sticky_sva.StableStDropOut_A	6727276	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	62	0	0
T26	223679	0	0	0
T27	1163	3	0	0
T28	705	0	0	0
T36	19631	0	0	0
T39	104582	2	0	0
T40	0	4	0	0
T44	0	2	0	0
T51	65086	0	0	0
T70	522	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T78	8664	0	0	0
T80	0	1	0	0
T163	0	2	0	0
T173	0	2	0	0
T177	0	2	0	0
T180	0	2	0	0
T190	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	125412	0	0
T26	223679	0	0	0
T27	1163	172	0	0
T28	705	0	0	0
T36	19631	0	0	0
T39	104582	18862	0	0
T40	0	184	0	0
T44	0	64765	0	0
T51	65086	0	0	0
T70	522	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T78	8664	0	0	0
T80	0	33	0	0
T163	0	12	0	0
T173	0	84	0	0
T177	0	87	0	0
T180	0	73	0	0
T190	0	33	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6055603	0	0
T1	7230	6829	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	4815	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	28129	0	0
T26	223679	0	0	0
T27	1163	41	0	0
T28	705	0	0	0
T36	19631	0	0	0
T39	104582	44	0	0
T40	0	321	0	0
T44	0	2250	0	0
T51	65086	0	0	0
T70	522	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T78	8664	0	0	0
T163	0	55	0	0
T173	0	40	0	0
T177	0	85	0	0
T180	0	41	0	0
T190	0	90	0	0
T228	0	35	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	29	0	0
T26	223679	0	0	0
T27	1163	1	0	0
T28	705	0	0	0
T36	19631	0	0	0
T39	104582	1	0	0
T40	0	2	0	0
T44	0	1	0	0
T51	65086	0	0	0
T70	522	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T78	8664	0	0	0
T163	0	1	0	0
T173	0	1	0	0
T177	0	1	0	0
T180	0	1	0	0
T190	0	1	0	0
T228	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5481135	0	0
T1	7230	6829	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	4815	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5483427	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	34	0	0
T26	223679	0	0	0
T27	1163	2	0	0
T28	705	0	0	0
T36	19631	0	0	0
T39	104582	1	0	0
T40	0	2	0	0
T44	0	1	0	0
T51	65086	0	0	0
T70	522	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T78	8664	0	0	0
T80	0	1	0	0
T163	0	1	0	0
T173	0	1	0	0
T177	0	1	0	0
T180	0	1	0	0
T190	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	29	0	0
T26	223679	0	0	0
T27	1163	1	0	0
T28	705	0	0	0
T36	19631	0	0	0
T39	104582	1	0	0
T40	0	2	0	0
T44	0	1	0	0
T51	65086	0	0	0
T70	522	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T78	8664	0	0	0
T163	0	1	0	0
T173	0	1	0	0
T177	0	1	0	0
T180	0	1	0	0
T190	0	1	0	0
T228	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	29	0	0
T26	223679	0	0	0
T27	1163	1	0	0
T28	705	0	0	0
T36	19631	0	0	0
T39	104582	1	0	0
T40	0	2	0	0
T44	0	1	0	0
T51	65086	0	0	0
T70	522	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T78	8664	0	0	0
T163	0	1	0	0
T173	0	1	0	0
T177	0	1	0	0
T180	0	1	0	0
T190	0	1	0	0
T228	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	29	0	0
T26	223679	0	0	0
T27	1163	1	0	0
T28	705	0	0	0
T36	19631	0	0	0
T39	104582	1	0	0
T40	0	2	0	0
T44	0	1	0	0
T51	65086	0	0	0
T70	522	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T78	8664	0	0	0
T163	0	1	0	0
T173	0	1	0	0
T177	0	1	0	0
T180	0	1	0	0
T190	0	1	0	0
T228	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	28084	0	0
T26	223679	0	0	0
T27	1163	39	0	0
T28	705	0	0	0
T36	19631	0	0	0
T39	104582	42	0	0
T40	0	318	0	0
T44	0	2248	0	0
T51	65086	0	0	0
T70	522	0	0	0
T71	408	0	0	0
T72	442	0	0	0
T78	8664	0	0	0
T163	0	54	0	0
T173	0	39	0	0
T177	0	84	0	0
T180	0	40	0	0
T190	0	89	0	0
T228	0	34	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	7076	0	0
T1	7230	28	0	0
T4	26326	49	0	0
T5	652	3	0	0
T6	507	3	0	0
T14	539	4	0	0
T15	501	5	0	0
T16	742	0	0	0
T17	428	2	0	0
T18	493	7	0	0
T19	5216	30	0	0
T20	0	9	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6058011	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	13	0	0
T40	2115	1	0	0
T52	652	0	0	0
T61	991	0	0	0
T73	6302	0	0	0
T95	4866	0	0	0
T126	8158	0	0	0
T159	11218	0	0	0
T160	404	0	0	0
T161	422	0	0	0
T162	512	0	0	0
T163	0	1	0	0
T168	0	1	0	0
T173	0	1	0	0
T177	0	1	0	0
T180	0	1	0	0
T190	0	1	0	0
T195	0	2	0	0
T228	0	1	0	0
T233	0	1	0	0