Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T19,T3
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T19,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T19,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T19,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T3
1	0	Covered	T1,T3,T48
1	1	Covered	T1,T19,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T3
0	1	Covered	T19,T49,T50
1	0	Covered	T48,T50,T73

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T10
0	1	Covered	T1,T3,T10
1	0	Covered	T80,T85,T263

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T10
1	-	Covered	T1,T3,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T19,T3
DetectSt	168	Covered	T1,T19,T3
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T3,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T19,T3
DebounceSt->IdleSt	163	Covered	T80,T81,T264
DetectSt->IdleSt	186	Covered	T19,T48,T49
DetectSt->StableSt	191	Covered	T1,T3,T10
IdleSt->DebounceSt	148	Covered	T1,T19,T3
StableSt->IdleSt	206	Covered	T1,T3,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T19,T3
0	1	Covered	T1,T19,T3
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T19,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T19,T3
IdleSt	0	-	-	-	-	-	-	Covered	T1,T19,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T19,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T80,T81,T264
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T19,T3
DetectSt	-	-	-	-	1	-	-	Covered	T19,T48,T49
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T10
DetectSt	-	-	-	-	0	0	-	Covered	T1,T19,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T10
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T10
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6727276	3491	0	0
CntIncr_A	6727276	135761	0	0
CntNoWrap_A	6727276	6052174	0	0
DetectStDropOut_A	6727276	527	0	0
DetectedOut_A	6727276	86652	0	0
DetectedPulseOut_A	6727276	960	0	0
DisabledIdleSt_A	6727276	5569512	0	0
DisabledNoDetection_A	6727276	5571644	0	0
EnterDebounceSt_A	6727276	1751	0	0
EnterDetectSt_A	6727276	1740	0	0
EnterStableSt_A	6727276	960	0	0
PulseIsPulse_A	6727276	960	0	0
StayInStableSt	6727276	85571	0	0
gen_high_event_sva.HighLevelEvent_A	6727276	6058011	0	0
gen_high_level_sva.HighLevelEvent_A	6727276	6058011	0	0
gen_not_sticky_sva.StableStDropOut_A	6727276	818	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	3491	0	0
T1	7230	46	0	0
T2	11153	0	0	0
T3	0	28	0	0
T10	0	52	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	46	0	0
T20	490	0	0	0
T21	490	0	0	0
T35	0	34	0	0
T36	0	50	0	0
T48	0	8	0	0
T49	0	26	0	0
T50	0	42	0	0
T73	0	52	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	135761	0	0
T1	7230	851	0	0
T2	11153	0	0	0
T3	0	1246	0	0
T10	0	2262	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	1199	0	0
T20	490	0	0	0
T21	490	0	0	0
T35	0	1258	0	0
T36	0	1125	0	0
T48	0	498	0	0
T49	0	708	0	0
T50	0	1310	0	0
T73	0	1302	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6052174	0	0
T1	7230	6783	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	4769	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	527	0	0
T2	11153	0	0	0
T3	37660	0	0	0
T7	11771	0	0	0
T19	5216	23	0	0
T20	490	0	0	0
T21	490	0	0	0
T34	946	0	0	0
T48	10437	0	0	0
T49	0	13	0	0
T50	0	11	0	0
T60	560	0	0	0
T68	491	0	0	0
T73	0	23	0	0
T95	0	13	0	0
T97	0	13	0	0
T98	0	3	0	0
T265	0	13	0	0
T266	0	2	0	0
T267	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	86652	0	0
T1	7230	2087	0	0
T2	11153	0	0	0
T3	0	1773	0	0
T10	0	3231	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	0	0	0
T20	490	0	0	0
T21	490	0	0	0
T35	0	1400	0	0
T36	0	2437	0	0
T38	0	795	0	0
T126	0	1372	0	0
T127	0	368	0	0
T137	0	2090	0	0
T141	0	3689	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	960	0	0
T1	7230	23	0	0
T2	11153	0	0	0
T3	0	14	0	0
T10	0	26	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	0	0	0
T20	490	0	0	0
T21	490	0	0	0
T35	0	17	0	0
T36	0	25	0	0
T38	0	9	0	0
T126	0	35	0	0
T127	0	15	0	0
T137	0	29	0	0
T141	0	24	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5569512	0	0
T1	7230	2055	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	2015	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5571644	0	0
T1	7230	2055	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	2015	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	1751	0	0
T1	7230	23	0	0
T2	11153	0	0	0
T3	0	14	0	0
T10	0	26	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	23	0	0
T20	490	0	0	0
T21	490	0	0	0
T35	0	17	0	0
T36	0	25	0	0
T48	0	4	0	0
T49	0	13	0	0
T50	0	21	0	0
T73	0	26	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	1740	0	0
T1	7230	23	0	0
T2	11153	0	0	0
T3	0	14	0	0
T10	0	26	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	23	0	0
T20	490	0	0	0
T21	490	0	0	0
T35	0	17	0	0
T36	0	25	0	0
T48	0	4	0	0
T49	0	13	0	0
T50	0	21	0	0
T73	0	26	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	960	0	0
T1	7230	23	0	0
T2	11153	0	0	0
T3	0	14	0	0
T10	0	26	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	0	0	0
T20	490	0	0	0
T21	490	0	0	0
T35	0	17	0	0
T36	0	25	0	0
T38	0	9	0	0
T126	0	35	0	0
T127	0	15	0	0
T137	0	29	0	0
T141	0	24	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	960	0	0
T1	7230	23	0	0
T2	11153	0	0	0
T3	0	14	0	0
T10	0	26	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	0	0	0
T20	490	0	0	0
T21	490	0	0	0
T35	0	17	0	0
T36	0	25	0	0
T38	0	9	0	0
T126	0	35	0	0
T127	0	15	0	0
T137	0	29	0	0
T141	0	24	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	85571	0	0
T1	7230	2064	0	0
T2	11153	0	0	0
T3	0	1752	0	0
T10	0	3202	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	0	0	0
T20	490	0	0	0
T21	490	0	0	0
T35	0	1381	0	0
T36	0	2406	0	0
T38	0	782	0	0
T126	0	1337	0	0
T127	0	353	0	0
T137	0	2061	0	0
T141	0	3653	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6058011	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6058011	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	818	0	0
T1	7230	23	0	0
T2	11153	0	0	0
T3	0	7	0	0
T10	0	23	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	0	0	0
T20	490	0	0	0
T21	490	0	0	0
T35	0	15	0	0
T36	0	19	0	0
T38	0	5	0	0
T126	0	35	0	0
T127	0	15	0	0
T137	0	29	0	0
T141	0	12	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T19,T2
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T2
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T19
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T96,T80,T99
1	0	Covered	T80,T81

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T82,T81,T268

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T3
DetectSt	168	Covered	T1,T2,T3
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T3
DebounceSt->IdleSt	163	Covered	T3,T13,T59
DetectSt->IdleSt	186	Covered	T96,T80,T99
DetectSt->StableSt	191	Covered	T1,T2,T3
IdleSt->DebounceSt	148	Covered	T1,T2,T3
StableSt->IdleSt	206	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T13,T59
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T96,T80,T99
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6727276	923	0	0
CntIncr_A	6727276	47317	0	0
CntNoWrap_A	6727276	6054742	0	0
DetectStDropOut_A	6727276	51	0	0
DetectedOut_A	6727276	15579	0	0
DetectedPulseOut_A	6727276	368	0	0
DisabledIdleSt_A	6727276	5685771	0	0
DisabledNoDetection_A	6727276	5687417	0	0
EnterDebounceSt_A	6727276	503	0	0
EnterDetectSt_A	6727276	422	0	0
EnterStableSt_A	6727276	368	0	0
PulseIsPulse_A	6727276	368	0	0
StayInStableSt	6727276	15177	0	0
gen_high_level_sva.HighLevelEvent_A	6727276	6058011	0	0
gen_not_sticky_sva.StableStDropOut_A	6727276	328	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	923	0	0
T1	7230	2	0	0
T2	11153	8	0	0
T3	0	15	0	0
T9	0	4	0	0
T10	0	6	0	0
T11	0	4	0	0
T13	0	3	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	0	0	0
T20	490	0	0	0
T21	490	0	0	0
T35	0	4	0	0
T36	0	12	0	0
T59	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	47317	0	0
T1	7230	86	0	0
T2	11153	588	0	0
T3	0	651	0	0
T9	0	290	0	0
T10	0	213	0	0
T11	0	336	0	0
T13	0	174	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	0	0	0
T20	490	0	0	0
T21	490	0	0	0
T35	0	146	0	0
T36	0	480	0	0
T59	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6054742	0	0
T1	7230	6827	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	4815	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	51	0	0
T44	272590	0	0	0
T74	701	0	0	0
T80	0	1	0	0
T84	0	7	0	0
T96	12432	6	0	0
T99	0	3	0	0
T100	0	3	0	0
T101	0	2	0	0
T102	0	4	0	0
T103	0	13	0	0
T104	0	1	0	0
T108	0	5	0	0
T110	2388	0	0	0
T111	29996	0	0	0
T112	519	0	0	0
T113	402	0	0	0
T114	33810	0	0	0
T115	521	0	0	0
T116	501	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	15579	0	0
T1	7230	60	0	0
T2	11153	118	0	0
T3	0	225	0	0
T9	0	82	0	0
T10	0	152	0	0
T11	0	39	0	0
T13	0	73	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	0	0	0
T20	490	0	0	0
T21	490	0	0	0
T26	0	3	0	0
T35	0	135	0	0
T36	0	306	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	368	0	0
T1	7230	1	0	0
T2	11153	4	0	0
T3	0	7	0	0
T9	0	2	0	0
T10	0	3	0	0
T11	0	2	0	0
T13	0	1	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	0	0	0
T20	490	0	0	0
T21	490	0	0	0
T26	0	1	0	0
T35	0	2	0	0
T36	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5685771	0	0
T1	7230	4742	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	4815	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5687417	0	0
T1	7230	4743	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	503	0	0
T1	7230	1	0	0
T2	11153	4	0	0
T3	0	8	0	0
T9	0	2	0	0
T10	0	3	0	0
T11	0	2	0	0
T13	0	2	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	0	0	0
T20	490	0	0	0
T21	490	0	0	0
T35	0	2	0	0
T36	0	6	0	0
T59	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	422	0	0
T1	7230	1	0	0
T2	11153	4	0	0
T3	0	7	0	0
T9	0	2	0	0
T10	0	3	0	0
T11	0	2	0	0
T13	0	1	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	0	0	0
T20	490	0	0	0
T21	490	0	0	0
T26	0	1	0	0
T35	0	2	0	0
T36	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	368	0	0
T1	7230	1	0	0
T2	11153	4	0	0
T3	0	7	0	0
T9	0	2	0	0
T10	0	3	0	0
T11	0	2	0	0
T13	0	1	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	0	0	0
T20	490	0	0	0
T21	490	0	0	0
T26	0	1	0	0
T35	0	2	0	0
T36	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	368	0	0
T1	7230	1	0	0
T2	11153	4	0	0
T3	0	7	0	0
T9	0	2	0	0
T10	0	3	0	0
T11	0	2	0	0
T13	0	1	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	0	0	0
T20	490	0	0	0
T21	490	0	0	0
T26	0	1	0	0
T35	0	2	0	0
T36	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	15177	0	0
T1	7230	59	0	0
T2	11153	114	0	0
T3	0	214	0	0
T9	0	80	0	0
T10	0	149	0	0
T11	0	37	0	0
T13	0	72	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	0	0	0
T20	490	0	0	0
T21	490	0	0	0
T26	0	2	0	0
T35	0	133	0	0
T36	0	297	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6058011	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	328	0	0
T1	7230	1	0	0
T2	11153	4	0	0
T3	0	3	0	0
T9	0	2	0	0
T10	0	3	0	0
T11	0	2	0	0
T13	0	1	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	0	0	0
T20	490	0	0	0
T21	490	0	0	0
T26	0	1	0	0
T35	0	2	0	0
T36	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T19,T3
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T19,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T19,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T19,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T3
1	0	Covered	T1,T3,T48
1	1	Covered	T1,T19,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T3
0	1	Covered	T19,T49,T36
1	0	Covered	T36,T73,T37

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T48
0	1	Covered	T1,T3,T48
1	0	Covered	T80

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T48
1	-	Covered	T1,T3,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T19,T3
DetectSt	168	Covered	T1,T19,T3
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T3,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T19,T3
DebounceSt->IdleSt	163	Covered	T80,T81,T264
DetectSt->IdleSt	186	Covered	T19,T49,T36
DetectSt->StableSt	191	Covered	T1,T3,T48
IdleSt->DebounceSt	148	Covered	T1,T19,T3
StableSt->IdleSt	206	Covered	T1,T3,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T19,T3
0	1	Covered	T1,T19,T3
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T19,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T19,T3
IdleSt	0	-	-	-	-	-	-	Covered	T1,T19,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T19,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T80,T81,T264
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T19,T3
DetectSt	-	-	-	-	1	-	-	Covered	T19,T49,T36
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T48
DetectSt	-	-	-	-	0	0	-	Covered	T1,T19,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T48
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T48
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6727276	2988	0	0
CntIncr_A	6727276	109740	0	0
CntNoWrap_A	6727276	6052677	0	0
DetectStDropOut_A	6727276	438	0	0
DetectedOut_A	6727276	86863	0	0
DetectedPulseOut_A	6727276	803	0	0
DisabledIdleSt_A	6727276	5566618	0	0
DisabledNoDetection_A	6727276	5568784	0	0
EnterDebounceSt_A	6727276	1497	0	0
EnterDetectSt_A	6727276	1491	0	0
EnterStableSt_A	6727276	803	0	0
PulseIsPulse_A	6727276	803	0	0
StayInStableSt	6727276	85973	0	0
gen_high_event_sva.HighLevelEvent_A	6727276	6058011	0	0
gen_high_level_sva.HighLevelEvent_A	6727276	6058011	0	0
gen_not_sticky_sva.StableStDropOut_A	6727276	715	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	2988	0	0
T1	7230	44	0	0
T2	11153	0	0	0
T3	0	26	0	0
T10	0	12	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	8	0	0
T20	490	0	0	0
T21	490	0	0	0
T35	0	10	0	0
T36	0	58	0	0
T48	0	48	0	0
T49	0	42	0	0
T50	0	20	0	0
T73	0	56	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	109740	0	0
T1	7230	924	0	0
T2	11153	0	0	0
T3	0	780	0	0
T10	0	588	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	207	0	0
T20	490	0	0	0
T21	490	0	0	0
T35	0	425	0	0
T36	0	1531	0	0
T48	0	1536	0	0
T49	0	1156	0	0
T50	0	470	0	0
T73	0	1414	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6052677	0	0
T1	7230	6785	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	4807	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	438	0	0
T2	11153	0	0	0
T3	37660	0	0	0
T7	11771	0	0	0
T19	5216	4	0	0
T20	490	0	0	0
T21	490	0	0	0
T34	946	0	0	0
T36	0	13	0	0
T38	0	2	0	0
T48	10437	0	0	0
T49	0	21	0	0
T60	560	0	0	0
T68	491	0	0	0
T73	0	18	0	0
T80	0	1	0	0
T95	0	13	0	0
T97	0	8	0	0
T265	0	29	0	0
T267	0	27	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	86863	0	0
T1	7230	761	0	0
T2	11153	0	0	0
T3	0	1884	0	0
T10	0	512	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	0	0	0
T20	490	0	0	0
T21	490	0	0	0
T35	0	14	0	0
T48	0	2926	0	0
T50	0	1289	0	0
T98	0	615	0	0
T126	0	398	0	0
T127	0	1575	0	0
T137	0	241	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	803	0	0
T1	7230	22	0	0
T2	11153	0	0	0
T3	0	13	0	0
T10	0	6	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	0	0	0
T20	490	0	0	0
T21	490	0	0	0
T35	0	5	0	0
T48	0	24	0	0
T50	0	10	0	0
T98	0	9	0	0
T126	0	14	0	0
T127	0	19	0	0
T137	0	22	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5566618	0	0
T1	7230	3251	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	2015	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5568784	0	0
T1	7230	3251	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	2015	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	1497	0	0
T1	7230	22	0	0
T2	11153	0	0	0
T3	0	13	0	0
T10	0	6	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	4	0	0
T20	490	0	0	0
T21	490	0	0	0
T35	0	5	0	0
T36	0	29	0	0
T48	0	24	0	0
T49	0	21	0	0
T50	0	10	0	0
T73	0	28	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	1491	0	0
T1	7230	22	0	0
T2	11153	0	0	0
T3	0	13	0	0
T10	0	6	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	4	0	0
T20	490	0	0	0
T21	490	0	0	0
T35	0	5	0	0
T36	0	29	0	0
T48	0	24	0	0
T49	0	21	0	0
T50	0	10	0	0
T73	0	28	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	803	0	0
T1	7230	22	0	0
T2	11153	0	0	0
T3	0	13	0	0
T10	0	6	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	0	0	0
T20	490	0	0	0
T21	490	0	0	0
T35	0	5	0	0
T48	0	24	0	0
T50	0	10	0	0
T98	0	9	0	0
T126	0	14	0	0
T127	0	19	0	0
T137	0	22	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	803	0	0
T1	7230	22	0	0
T2	11153	0	0	0
T3	0	13	0	0
T10	0	6	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	0	0	0
T20	490	0	0	0
T21	490	0	0	0
T35	0	5	0	0
T48	0	24	0	0
T50	0	10	0	0
T98	0	9	0	0
T126	0	14	0	0
T127	0	19	0	0
T137	0	22	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	85973	0	0
T1	7230	739	0	0
T2	11153	0	0	0
T3	0	1868	0	0
T10	0	505	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	0	0	0
T20	490	0	0	0
T21	490	0	0	0
T35	0	9	0	0
T48	0	2902	0	0
T50	0	1279	0	0
T98	0	605	0	0
T126	0	384	0	0
T127	0	1554	0	0
T137	0	219	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6058011	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6058011	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	715	0	0
T1	7230	22	0	0
T2	11153	0	0	0
T3	0	10	0	0
T10	0	5	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	0	0	0
T20	490	0	0	0
T21	490	0	0	0
T35	0	5	0	0
T48	0	24	0	0
T50	0	10	0	0
T98	0	8	0	0
T126	0	14	0	0
T127	0	17	0	0
T137	0	22	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T19,T2
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T2
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T3,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T19
1	1	Covered	T2,T3,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T7
0	1	Covered	T2,T78,T135
1	0	Covered	T80,T81

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T9
0	1	Covered	T3,T7,T9
1	0	Covered	T80,T81

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T9
1	-	Covered	T3,T7,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T7
DetectSt	168	Covered	T2,T3,T7
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T7,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T7
DebounceSt->IdleSt	163	Covered	T7,T9,T50
DetectSt->IdleSt	186	Covered	T2,T78,T135
DetectSt->StableSt	191	Covered	T3,T7,T9
IdleSt->DebounceSt	148	Covered	T2,T3,T7
StableSt->IdleSt	206	Covered	T3,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T7
0	1	Covered	T2,T3,T7
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T9,T50
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T7
DetectSt	-	-	-	-	1	-	-	Covered	T2,T78,T135
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T9
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T7
StableSt	-	-	-	-	-	-	1	Covered	T3,T7,T9
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6727276	782	0	0
CntIncr_A	6727276	46186	0	0
CntNoWrap_A	6727276	6054883	0	0
DetectStDropOut_A	6727276	94	0	0
DetectedOut_A	6727276	17790	0	0
DetectedPulseOut_A	6727276	267	0	0
DisabledIdleSt_A	6727276	5692820	0	0
DisabledNoDetection_A	6727276	5694578	0	0
EnterDebounceSt_A	6727276	418	0	0
EnterDetectSt_A	6727276	366	0	0
EnterStableSt_A	6727276	267	0	0
PulseIsPulse_A	6727276	267	0	0
StayInStableSt	6727276	17499	0	0
gen_high_level_sva.HighLevelEvent_A	6727276	6058011	0	0
gen_not_sticky_sva.StableStDropOut_A	6727276	239	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	782	0	0
T2	11153	4	0	0
T3	37660	6	0	0
T7	11771	7	0	0
T8	424352	0	0	0
T9	0	7	0	0
T10	0	2	0	0
T11	0	2	0	0
T13	0	2	0	0
T21	490	0	0	0
T34	946	0	0	0
T48	10437	0	0	0
T50	0	5	0	0
T60	560	0	0	0
T65	423	0	0	0
T68	491	0	0	0
T78	0	12	0	0
T159	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	46186	0	0
T2	11153	353	0	0
T3	37660	237	0	0
T7	11771	379	0	0
T8	424352	0	0	0
T9	0	593	0	0
T10	0	62	0	0
T11	0	182	0	0
T13	0	222	0	0
T21	490	0	0	0
T34	946	0	0	0
T48	10437	0	0	0
T50	0	113	0	0
T60	560	0	0	0
T65	423	0	0	0
T68	491	0	0	0
T78	0	895	0	0
T159	0	166	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6054883	0	0
T1	7230	6829	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	4815	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	94	0	0
T2	11153	2	0	0
T3	37660	0	0	0
T7	11771	0	0	0
T8	424352	0	0	0
T21	490	0	0	0
T34	946	0	0	0
T48	10437	0	0	0
T60	560	0	0	0
T65	423	0	0	0
T68	491	0	0	0
T78	0	6	0	0
T94	0	8	0	0
T100	0	9	0	0
T101	0	2	0	0
T135	0	2	0	0
T179	0	5	0	0
T194	0	1	0	0
T269	0	3	0	0
T270	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	17790	0	0
T3	37660	121	0	0
T7	11771	32	0	0
T8	424352	0	0	0
T9	6991	45	0	0
T10	0	59	0	0
T11	0	5	0	0
T13	0	5	0	0
T34	946	0	0	0
T48	10437	0	0	0
T50	0	129	0	0
T60	560	0	0	0
T65	423	0	0	0
T66	406	0	0	0
T68	491	0	0	0
T79	0	131	0	0
T114	0	127	0	0
T127	0	147	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	267	0	0
T3	37660	3	0	0
T7	11771	3	0	0
T8	424352	0	0	0
T9	6991	3	0	0
T10	0	1	0	0
T11	0	1	0	0
T13	0	1	0	0
T34	946	0	0	0
T48	10437	0	0	0
T50	0	2	0	0
T60	560	0	0	0
T65	423	0	0	0
T66	406	0	0	0
T68	491	0	0	0
T79	0	5	0	0
T114	0	9	0	0
T127	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5692820	0	0
T1	7230	6068	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	4815	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5694578	0	0
T1	7230	6069	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	418	0	0
T2	11153	2	0	0
T3	37660	3	0	0
T7	11771	4	0	0
T8	424352	0	0	0
T9	0	4	0	0
T10	0	1	0	0
T11	0	1	0	0
T13	0	1	0	0
T21	490	0	0	0
T34	946	0	0	0
T48	10437	0	0	0
T50	0	3	0	0
T60	560	0	0	0
T65	423	0	0	0
T68	491	0	0	0
T78	0	6	0	0
T159	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	366	0	0
T2	11153	2	0	0
T3	37660	3	0	0
T7	11771	3	0	0
T8	424352	0	0	0
T9	0	3	0	0
T10	0	1	0	0
T11	0	1	0	0
T13	0	1	0	0
T21	490	0	0	0
T34	946	0	0	0
T48	10437	0	0	0
T50	0	2	0	0
T60	560	0	0	0
T65	423	0	0	0
T68	491	0	0	0
T78	0	6	0	0
T79	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	267	0	0
T3	37660	3	0	0
T7	11771	3	0	0
T8	424352	0	0	0
T9	6991	3	0	0
T10	0	1	0	0
T11	0	1	0	0
T13	0	1	0	0
T34	946	0	0	0
T48	10437	0	0	0
T50	0	2	0	0
T60	560	0	0	0
T65	423	0	0	0
T66	406	0	0	0
T68	491	0	0	0
T79	0	5	0	0
T114	0	9	0	0
T127	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	267	0	0
T3	37660	3	0	0
T7	11771	3	0	0
T8	424352	0	0	0
T9	6991	3	0	0
T10	0	1	0	0
T11	0	1	0	0
T13	0	1	0	0
T34	946	0	0	0
T48	10437	0	0	0
T50	0	2	0	0
T60	560	0	0	0
T65	423	0	0	0
T66	406	0	0	0
T68	491	0	0	0
T79	0	5	0	0
T114	0	9	0	0
T127	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	17499	0	0
T3	37660	118	0	0
T7	11771	29	0	0
T8	424352	0	0	0
T9	6991	42	0	0
T10	0	58	0	0
T11	0	4	0	0
T13	0	4	0	0
T34	946	0	0	0
T48	10437	0	0	0
T50	0	127	0	0
T60	560	0	0	0
T65	423	0	0	0
T66	406	0	0	0
T68	491	0	0	0
T79	0	126	0	0
T114	0	118	0	0
T127	0	145	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6058011	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	239	0	0
T3	37660	3	0	0
T7	11771	3	0	0
T8	424352	0	0	0
T9	6991	3	0	0
T10	0	1	0	0
T11	0	1	0	0
T13	0	1	0	0
T34	946	0	0	0
T48	10437	0	0	0
T50	0	2	0	0
T60	560	0	0	0
T65	423	0	0	0
T66	406	0	0	0
T68	491	0	0	0
T79	0	5	0	0
T114	0	9	0	0
T127	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T19,T3
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T19,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T19,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T19,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T3
1	0	Covered	T1,T3,T48
1	1	Covered	T1,T19,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T3
0	1	Covered	T19,T49,T50
1	0	Covered	T1,T50,T36

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T48,T10
0	1	Covered	T3,T48,T10
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T48,T10
1	-	Covered	T3,T48,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T19,T3
DetectSt	168	Covered	T1,T19,T3
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T48,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T19,T3
DebounceSt->IdleSt	163	Covered	T80,T81,T264
DetectSt->IdleSt	186	Covered	T1,T19,T49
DetectSt->StableSt	191	Covered	T3,T48,T10
IdleSt->DebounceSt	148	Covered	T1,T19,T3
StableSt->IdleSt	206	Covered	T3,T48,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T19,T3
0	1	Covered	T1,T19,T3
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T19,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T19,T3
IdleSt	0	-	-	-	-	-	-	Covered	T1,T19,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T19,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T80,T81,T264
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T19,T3
DetectSt	-	-	-	-	1	-	-	Covered	T1,T19,T49
DetectSt	-	-	-	-	0	1	-	Covered	T3,T48,T10
DetectSt	-	-	-	-	0	0	-	Covered	T1,T19,T3
StableSt	-	-	-	-	-	-	1	Covered	T3,T48,T10
StableSt	-	-	-	-	-	-	0	Covered	T3,T48,T10
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6727276	3282	0	0
CntIncr_A	6727276	118805	0	0
CntNoWrap_A	6727276	6052383	0	0
DetectStDropOut_A	6727276	454	0	0
DetectedOut_A	6727276	97152	0	0
DetectedPulseOut_A	6727276	992	0	0
DisabledIdleSt_A	6727276	5557034	0	0
DisabledNoDetection_A	6727276	5559173	0	0
EnterDebounceSt_A	6727276	1645	0	0
EnterDetectSt_A	6727276	1637	0	0
EnterStableSt_A	6727276	992	0	0
PulseIsPulse_A	6727276	992	0	0
StayInStableSt	6727276	96045	0	0
gen_high_event_sva.HighLevelEvent_A	6727276	6058011	0	0
gen_high_level_sva.HighLevelEvent_A	6727276	6058011	0	0
gen_not_sticky_sva.StableStDropOut_A	6727276	877	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	3282	0	0
T1	7230	14	0	0
T2	11153	0	0	0
T3	0	20	0	0
T10	0	32	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	10	0	0
T20	490	0	0	0
T21	490	0	0	0
T35	0	52	0	0
T36	0	58	0	0
T48	0	52	0	0
T49	0	14	0	0
T50	0	16	0	0
T73	0	32	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	118805	0	0
T1	7230	425	0	0
T2	11153	0	0	0
T3	0	750	0	0
T10	0	1280	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	256	0	0
T20	490	0	0	0
T21	490	0	0	0
T35	0	1794	0	0
T36	0	1519	0	0
T48	0	2028	0	0
T49	0	379	0	0
T50	0	496	0	0
T73	0	804	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6052383	0	0
T1	7230	6815	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	4805	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	454	0	0
T2	11153	0	0	0
T3	37660	0	0	0
T7	11771	0	0	0
T19	5216	5	0	0
T20	490	0	0	0
T21	490	0	0	0
T34	946	0	0	0
T36	0	16	0	0
T48	10437	0	0	0
T49	0	7	0	0
T50	0	4	0	0
T60	560	0	0	0
T68	491	0	0	0
T73	0	6	0	0
T80	0	1	0	0
T95	0	13	0	0
T141	0	16	0	0
T265	0	10	0	0
T271	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	97152	0	0
T3	37660	1186	0	0
T7	11771	0	0	0
T8	424352	0	0	0
T9	6991	0	0	0
T10	0	2193	0	0
T34	946	0	0	0
T35	0	1366	0	0
T37	0	1785	0	0
T38	0	2791	0	0
T48	10437	2695	0	0
T60	560	0	0	0
T65	423	0	0	0
T66	406	0	0	0
T68	491	0	0	0
T97	0	1271	0	0
T126	0	1860	0	0
T127	0	571	0	0
T137	0	67	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	992	0	0
T3	37660	10	0	0
T7	11771	0	0	0
T8	424352	0	0	0
T9	6991	0	0	0
T10	0	16	0	0
T34	946	0	0	0
T35	0	26	0	0
T37	0	21	0	0
T38	0	16	0	0
T48	10437	26	0	0
T60	560	0	0	0
T65	423	0	0	0
T66	406	0	0	0
T68	491	0	0	0
T97	0	20	0	0
T126	0	34	0	0
T127	0	30	0	0
T137	0	10	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5557034	0	0
T1	7230	3628	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	2015	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5559173	0	0
T1	7230	3628	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	2015	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	1645	0	0
T1	7230	7	0	0
T2	11153	0	0	0
T3	0	10	0	0
T10	0	16	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	5	0	0
T20	490	0	0	0
T21	490	0	0	0
T35	0	26	0	0
T36	0	29	0	0
T48	0	26	0	0
T49	0	7	0	0
T50	0	8	0	0
T73	0	16	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	1637	0	0
T1	7230	7	0	0
T2	11153	0	0	0
T3	0	10	0	0
T10	0	16	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	5	0	0
T20	490	0	0	0
T21	490	0	0	0
T35	0	26	0	0
T36	0	29	0	0
T48	0	26	0	0
T49	0	7	0	0
T50	0	8	0	0
T73	0	16	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	992	0	0
T3	37660	10	0	0
T7	11771	0	0	0
T8	424352	0	0	0
T9	6991	0	0	0
T10	0	16	0	0
T34	946	0	0	0
T35	0	26	0	0
T37	0	21	0	0
T38	0	16	0	0
T48	10437	26	0	0
T60	560	0	0	0
T65	423	0	0	0
T66	406	0	0	0
T68	491	0	0	0
T97	0	20	0	0
T126	0	34	0	0
T127	0	30	0	0
T137	0	10	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	992	0	0
T3	37660	10	0	0
T7	11771	0	0	0
T8	424352	0	0	0
T9	6991	0	0	0
T10	0	16	0	0
T34	946	0	0	0
T35	0	26	0	0
T37	0	21	0	0
T38	0	16	0	0
T48	10437	26	0	0
T60	560	0	0	0
T65	423	0	0	0
T66	406	0	0	0
T68	491	0	0	0
T97	0	20	0	0
T126	0	34	0	0
T127	0	30	0	0
T137	0	10	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	96045	0	0
T3	37660	1172	0	0
T7	11771	0	0	0
T8	424352	0	0	0
T9	6991	0	0	0
T10	0	2177	0	0
T34	946	0	0	0
T35	0	1338	0	0
T37	0	1762	0	0
T38	0	2763	0	0
T48	10437	2669	0	0
T60	560	0	0	0
T65	423	0	0	0
T66	406	0	0	0
T68	491	0	0	0
T97	0	1251	0	0
T126	0	1826	0	0
T127	0	540	0	0
T137	0	57	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6058011	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6058011	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	877	0	0
T3	37660	6	0	0
T7	11771	0	0	0
T8	424352	0	0	0
T9	6991	0	0	0
T10	0	16	0	0
T34	946	0	0	0
T35	0	24	0	0
T37	0	19	0	0
T38	0	4	0	0
T48	10437	26	0	0
T60	560	0	0	0
T65	423	0	0	0
T66	406	0	0	0
T68	491	0	0	0
T97	0	20	0	0
T126	0	34	0	0
T127	0	29	0	0
T137	0	10	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T19,T2
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T2
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T3,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T48
1	0	Covered	T4,T1,T19
1	1	Covered	T2,T3,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T9
0	1	Covered	T79,T135,T270
1	0	Covered	T80,T81

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T9
0	1	Covered	T2,T3,T9
1	0	Covered	T83,T81

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T9
1	-	Covered	T2,T3,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T9
DetectSt	168	Covered	T2,T3,T9
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T3,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T9
DebounceSt->IdleSt	163	Covered	T269,T96,T111
DetectSt->IdleSt	186	Covered	T79,T135,T270
DetectSt->StableSt	191	Covered	T2,T3,T9
IdleSt->DebounceSt	148	Covered	T2,T3,T9
StableSt->IdleSt	206	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T9
0	1	Covered	T2,T3,T9
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T269,T96,T111
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T9
DetectSt	-	-	-	-	1	-	-	Covered	T79,T135,T270
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T9
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T9
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T9
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6727276	851	0	0
CntIncr_A	6727276	47151	0	0
CntNoWrap_A	6727276	6054814	0	0
DetectStDropOut_A	6727276	77	0	0
DetectedOut_A	6727276	17337	0	0
DetectedPulseOut_A	6727276	320	0	0
DisabledIdleSt_A	6727276	5673837	0	0
DisabledNoDetection_A	6727276	5675547	0	0
EnterDebounceSt_A	6727276	450	0	0
EnterDetectSt_A	6727276	402	0	0
EnterStableSt_A	6727276	320	0	0
PulseIsPulse_A	6727276	320	0	0
StayInStableSt	6727276	16991	0	0
gen_high_level_sva.HighLevelEvent_A	6727276	6058011	0	0
gen_not_sticky_sva.StableStDropOut_A	6727276	290	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	851	0	0
T2	11153	6	0	0
T3	37660	6	0	0
T7	11771	0	0	0
T8	424352	0	0	0
T9	0	10	0	0
T10	0	4	0	0
T11	0	4	0	0
T13	0	2	0	0
T21	490	0	0	0
T34	946	0	0	0
T35	0	2	0	0
T48	10437	0	0	0
T60	560	0	0	0
T65	423	0	0	0
T68	491	0	0	0
T78	0	2	0	0
T126	0	4	0	0
T159	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	47151	0	0
T2	11153	438	0	0
T3	37660	252	0	0
T7	11771	0	0	0
T8	424352	0	0	0
T9	0	790	0	0
T10	0	140	0	0
T11	0	306	0	0
T13	0	130	0	0
T21	490	0	0	0
T34	946	0	0	0
T35	0	91	0	0
T48	10437	0	0	0
T60	560	0	0	0
T65	423	0	0	0
T68	491	0	0	0
T78	0	138	0	0
T126	0	152	0	0
T159	0	103	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6054814	0	0
T1	7230	6829	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	4815	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	77	0	0
T53	5871	0	0	0
T54	1619	0	0	0
T55	734	0	0	0
T63	1013	0	0	0
T69	1305	0	0	0
T79	18885	2	0	0
T84	0	4	0	0
T101	0	3	0	0
T102	0	4	0	0
T135	0	3	0	0
T199	0	14	0	0
T205	0	9	0	0
T270	0	2	0	0
T272	0	2	0	0
T273	0	6	0	0
T274	453	0	0	0
T275	442	0	0	0
T276	513	0	0	0
T277	426	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	17337	0	0
T2	11153	91	0	0
T3	37660	107	0	0
T7	11771	0	0	0
T8	424352	0	0	0
T9	0	143	0	0
T10	0	102	0	0
T11	0	69	0	0
T13	0	98	0	0
T21	490	0	0	0
T34	946	0	0	0
T35	0	49	0	0
T48	10437	0	0	0
T60	560	0	0	0
T65	423	0	0	0
T68	491	0	0	0
T78	0	11	0	0
T126	0	68	0	0
T159	0	84	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	320	0	0
T2	11153	3	0	0
T3	37660	3	0	0
T7	11771	0	0	0
T8	424352	0	0	0
T9	0	5	0	0
T10	0	2	0	0
T11	0	2	0	0
T13	0	1	0	0
T21	490	0	0	0
T34	946	0	0	0
T35	0	1	0	0
T48	10437	0	0	0
T60	560	0	0	0
T65	423	0	0	0
T68	491	0	0	0
T78	0	1	0	0
T126	0	2	0	0
T159	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5673837	0	0
T1	7230	6829	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	4815	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5675547	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	450	0	0
T2	11153	3	0	0
T3	37660	3	0	0
T7	11771	0	0	0
T8	424352	0	0	0
T9	0	5	0	0
T10	0	2	0	0
T11	0	2	0	0
T13	0	1	0	0
T21	490	0	0	0
T34	946	0	0	0
T35	0	1	0	0
T48	10437	0	0	0
T60	560	0	0	0
T65	423	0	0	0
T68	491	0	0	0
T78	0	1	0	0
T126	0	2	0	0
T159	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	402	0	0
T2	11153	3	0	0
T3	37660	3	0	0
T7	11771	0	0	0
T8	424352	0	0	0
T9	0	5	0	0
T10	0	2	0	0
T11	0	2	0	0
T13	0	1	0	0
T21	490	0	0	0
T34	946	0	0	0
T35	0	1	0	0
T48	10437	0	0	0
T60	560	0	0	0
T65	423	0	0	0
T68	491	0	0	0
T78	0	1	0	0
T126	0	2	0	0
T159	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	320	0	0
T2	11153	3	0	0
T3	37660	3	0	0
T7	11771	0	0	0
T8	424352	0	0	0
T9	0	5	0	0
T10	0	2	0	0
T11	0	2	0	0
T13	0	1	0	0
T21	490	0	0	0
T34	946	0	0	0
T35	0	1	0	0
T48	10437	0	0	0
T60	560	0	0	0
T65	423	0	0	0
T68	491	0	0	0
T78	0	1	0	0
T126	0	2	0	0
T159	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	320	0	0
T2	11153	3	0	0
T3	37660	3	0	0
T7	11771	0	0	0
T8	424352	0	0	0
T9	0	5	0	0
T10	0	2	0	0
T11	0	2	0	0
T13	0	1	0	0
T21	490	0	0	0
T34	946	0	0	0
T35	0	1	0	0
T48	10437	0	0	0
T60	560	0	0	0
T65	423	0	0	0
T68	491	0	0	0
T78	0	1	0	0
T126	0	2	0	0
T159	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	16991	0	0
T2	11153	88	0	0
T3	37660	104	0	0
T7	11771	0	0	0
T8	424352	0	0	0
T9	0	138	0	0
T10	0	100	0	0
T11	0	67	0	0
T13	0	97	0	0
T21	490	0	0	0
T34	946	0	0	0
T35	0	47	0	0
T48	10437	0	0	0
T60	560	0	0	0
T65	423	0	0	0
T68	491	0	0	0
T78	0	10	0	0
T126	0	66	0	0
T159	0	83	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6058011	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	290	0	0
T2	11153	3	0	0
T3	37660	3	0	0
T7	11771	0	0	0
T8	424352	0	0	0
T9	0	5	0	0
T10	0	2	0	0
T11	0	2	0	0
T13	0	1	0	0
T21	490	0	0	0
T34	946	0	0	0
T37	0	2	0	0
T48	10437	0	0	0
T60	560	0	0	0
T65	423	0	0	0
T68	491	0	0	0
T78	0	1	0	0
T126	0	2	0	0
T159	0	1	0	0