Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T19,T3
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T19,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T19,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T19,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T3
1	0	Covered	T1,T3,T48
1	1	Covered	T1,T19,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T3
0	1	Covered	T19,T49,T35
1	0	Covered	T1,T10,T50

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T48,T36
0	1	Covered	T3,T48,T36
1	0	Covered	T86

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T48,T36
1	-	Covered	T3,T48,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T19,T3
DetectSt	168	Covered	T1,T19,T3
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T48,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T19,T3
DebounceSt->IdleSt	163	Covered	T80,T81,T264
DetectSt->IdleSt	186	Covered	T1,T19,T10
DetectSt->StableSt	191	Covered	T3,T48,T36
IdleSt->DebounceSt	148	Covered	T1,T19,T3
StableSt->IdleSt	206	Covered	T3,T48,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T19,T3
0	1	Covered	T1,T19,T3
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T19,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T19,T3
IdleSt	0	-	-	-	-	-	-	Covered	T1,T19,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T19,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T80,T81,T264
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T19,T3
DetectSt	-	-	-	-	1	-	-	Covered	T1,T19,T10
DetectSt	-	-	-	-	0	1	-	Covered	T3,T48,T36
DetectSt	-	-	-	-	0	0	-	Covered	T1,T19,T3
StableSt	-	-	-	-	-	-	1	Covered	T3,T48,T36
StableSt	-	-	-	-	-	-	0	Covered	T3,T48,T36
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6727276	3128	0	0
CntIncr_A	6727276	110369	0	0
CntNoWrap_A	6727276	6052537	0	0
DetectStDropOut_A	6727276	499	0	0
DetectedOut_A	6727276	72542	0	0
DetectedPulseOut_A	6727276	774	0	0
DisabledIdleSt_A	6727276	5576045	0	0
DisabledNoDetection_A	6727276	5578194	0	0
EnterDebounceSt_A	6727276	1568	0	0
EnterDetectSt_A	6727276	1560	0	0
EnterStableSt_A	6727276	774	0	0
PulseIsPulse_A	6727276	774	0	0
StayInStableSt	6727276	71664	0	0
gen_high_event_sva.HighLevelEvent_A	6727276	6058011	0	0
gen_high_level_sva.HighLevelEvent_A	6727276	6058011	0	0
gen_not_sticky_sva.StableStDropOut_A	6727276	664	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	3128	0	0
T1	7230	8	0	0
T2	11153	0	0	0
T3	0	30	0	0
T10	0	12	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	46	0	0
T20	490	0	0	0
T21	490	0	0	0
T35	0	52	0	0
T36	0	50	0	0
T48	0	24	0	0
T49	0	56	0	0
T50	0	6	0	0
T73	0	20	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	110369	0	0
T1	7230	242	0	0
T2	11153	0	0	0
T3	0	1035	0	0
T10	0	959	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	1199	0	0
T20	490	0	0	0
T21	490	0	0	0
T35	0	2226	0	0
T36	0	1225	0	0
T48	0	912	0	0
T49	0	1541	0	0
T50	0	189	0	0
T73	0	390	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6052537	0	0
T1	7230	6821	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	4769	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	499	0	0
T2	11153	0	0	0
T3	37660	0	0	0
T7	11771	0	0	0
T19	5216	23	0	0
T20	490	0	0	0
T21	490	0	0	0
T34	946	0	0	0
T35	0	5	0	0
T48	10437	0	0	0
T49	0	28	0	0
T60	560	0	0	0
T68	491	0	0	0
T80	0	1	0	0
T95	0	11	0	0
T265	0	5	0	0
T266	0	17	0	0
T267	0	32	0	0
T271	0	18	0	0
T278	0	27	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	72542	0	0
T3	37660	1858	0	0
T7	11771	0	0	0
T8	424352	0	0	0
T9	6991	0	0	0
T34	946	0	0	0
T36	0	2337	0	0
T37	0	1806	0	0
T38	0	703	0	0
T48	10437	610	0	0
T60	560	0	0	0
T65	423	0	0	0
T66	406	0	0	0
T68	491	0	0	0
T73	0	1287	0	0
T82	0	360	0	0
T98	0	2140	0	0
T126	0	728	0	0
T279	0	170	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	774	0	0
T3	37660	15	0	0
T7	11771	0	0	0
T8	424352	0	0	0
T9	6991	0	0	0
T34	946	0	0	0
T36	0	25	0	0
T37	0	21	0	0
T38	0	10	0	0
T48	10437	12	0	0
T60	560	0	0	0
T65	423	0	0	0
T66	406	0	0	0
T68	491	0	0	0
T73	0	10	0	0
T82	0	10	0	0
T98	0	23	0	0
T126	0	18	0	0
T279	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5576045	0	0
T1	7230	3628	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	2015	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5578194	0	0
T1	7230	3628	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	2015	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	1568	0	0
T1	7230	4	0	0
T2	11153	0	0	0
T3	0	15	0	0
T10	0	6	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	23	0	0
T20	490	0	0	0
T21	490	0	0	0
T35	0	26	0	0
T36	0	25	0	0
T48	0	12	0	0
T49	0	28	0	0
T50	0	3	0	0
T73	0	10	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	1560	0	0
T1	7230	4	0	0
T2	11153	0	0	0
T3	0	15	0	0
T10	0	6	0	0
T14	539	0	0	0
T15	501	0	0	0
T16	742	0	0	0
T17	428	0	0	0
T18	493	0	0	0
T19	5216	23	0	0
T20	490	0	0	0
T21	490	0	0	0
T35	0	26	0	0
T36	0	25	0	0
T48	0	12	0	0
T49	0	28	0	0
T50	0	3	0	0
T73	0	10	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	774	0	0
T3	37660	15	0	0
T7	11771	0	0	0
T8	424352	0	0	0
T9	6991	0	0	0
T34	946	0	0	0
T36	0	25	0	0
T37	0	21	0	0
T38	0	10	0	0
T48	10437	12	0	0
T60	560	0	0	0
T65	423	0	0	0
T66	406	0	0	0
T68	491	0	0	0
T73	0	10	0	0
T82	0	10	0	0
T98	0	23	0	0
T126	0	18	0	0
T279	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	774	0	0
T3	37660	15	0	0
T7	11771	0	0	0
T8	424352	0	0	0
T9	6991	0	0	0
T34	946	0	0	0
T36	0	25	0	0
T37	0	21	0	0
T38	0	10	0	0
T48	10437	12	0	0
T60	560	0	0	0
T65	423	0	0	0
T66	406	0	0	0
T68	491	0	0	0
T73	0	10	0	0
T82	0	10	0	0
T98	0	23	0	0
T126	0	18	0	0
T279	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	71664	0	0
T3	37660	1836	0	0
T7	11771	0	0	0
T8	424352	0	0	0
T9	6991	0	0	0
T34	946	0	0	0
T36	0	2306	0	0
T37	0	1783	0	0
T38	0	690	0	0
T48	10437	598	0	0
T60	560	0	0	0
T65	423	0	0	0
T66	406	0	0	0
T68	491	0	0	0
T73	0	1277	0	0
T82	0	350	0	0
T98	0	2116	0	0
T126	0	710	0	0
T279	0	162	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6058011	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6058011	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	664	0	0
T3	37660	8	0	0
T7	11771	0	0	0
T8	424352	0	0	0
T9	6991	0	0	0
T34	946	0	0	0
T36	0	19	0	0
T37	0	19	0	0
T38	0	7	0	0
T48	10437	12	0	0
T60	560	0	0	0
T65	423	0	0	0
T66	406	0	0	0
T68	491	0	0	0
T73	0	10	0	0
T82	0	10	0	0
T98	0	22	0	0
T126	0	18	0	0
T279	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T19,T2
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T2
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T3,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T48
1	0	Covered	T4,T1,T19
1	1	Covered	T2,T3,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T11
0	1	Covered	T11,T79,T94
1	0	Covered	T80,T81

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T13
0	1	Covered	T2,T3,T13
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T13
1	-	Covered	T2,T3,T13

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T11
DetectSt	168	Covered	T2,T3,T11
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T3,T13

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T11
DebounceSt->IdleSt	163	Covered	T11,T36,T159
DetectSt->IdleSt	186	Covered	T11,T79,T94
DetectSt->StableSt	191	Covered	T2,T3,T13
IdleSt->DebounceSt	148	Covered	T2,T3,T11
StableSt->IdleSt	206	Covered	T2,T3,T13

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T11
0	1	Covered	T2,T3,T11
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T11
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T80,T81
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T36,T159
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T11
DetectSt	-	-	-	-	1	-	-	Covered	T11,T79,T94
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T13
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T11
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T13
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T13
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6727276	706	0	0
CntIncr_A	6727276	42412	0	0
CntNoWrap_A	6727276	6054959	0	0
DetectStDropOut_A	6727276	41	0	0
DetectedOut_A	6727276	14345	0	0
DetectedPulseOut_A	6727276	285	0	0
DisabledIdleSt_A	6727276	5701944	0	0
DisabledNoDetection_A	6727276	5703667	0	0
EnterDebounceSt_A	6727276	377	0	0
EnterDetectSt_A	6727276	331	0	0
EnterStableSt_A	6727276	285	0	0
PulseIsPulse_A	6727276	285	0	0
StayInStableSt	6727276	14034	0	0
gen_high_level_sva.HighLevelEvent_A	6727276	6058011	0	0
gen_not_sticky_sva.StableStDropOut_A	6727276	257	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	706	0	0
T2	11153	4	0	0
T3	37660	12	0	0
T7	11771	0	0	0
T8	424352	0	0	0
T11	0	17	0	0
T13	0	6	0	0
T21	490	0	0	0
T34	946	0	0	0
T36	0	11	0	0
T37	0	5	0	0
T48	10437	0	0	0
T60	560	0	0	0
T65	423	0	0	0
T68	491	0	0	0
T73	0	9	0	0
T78	0	2	0	0
T79	0	6	0	0
T159	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	42412	0	0
T2	11153	338	0	0
T3	37660	528	0	0
T7	11771	0	0	0
T8	424352	0	0	0
T11	0	1602	0	0
T13	0	543	0	0
T21	490	0	0	0
T34	946	0	0	0
T36	0	425	0	0
T37	0	136	0	0
T48	10437	0	0	0
T60	560	0	0	0
T65	423	0	0	0
T68	491	0	0	0
T73	0	301	0	0
T78	0	89	0	0
T79	0	430	0	0
T159	0	166	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6054959	0	0
T1	7230	6829	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	4815	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	41	0	0
T11	13539	8	0	0
T12	2950	0	0	0
T13	17737	0	0	0
T27	1163	0	0	0
T35	14953	0	0	0
T49	5368	0	0	0
T50	6864	0	0	0
T58	493	0	0	0
T59	431	0	0	0
T67	523	0	0	0
T79	0	3	0	0
T80	0	1	0	0
T90	0	3	0	0
T94	0	3	0	0
T102	0	5	0	0
T103	0	5	0	0
T219	0	4	0	0
T280	0	6	0	0
T281	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	14345	0	0
T2	11153	15	0	0
T3	37660	186	0	0
T7	11771	0	0	0
T8	424352	0	0	0
T13	0	140	0	0
T21	490	0	0	0
T34	946	0	0	0
T36	0	265	0	0
T37	0	165	0	0
T38	0	190	0	0
T48	10437	0	0	0
T60	560	0	0	0
T65	423	0	0	0
T68	491	0	0	0
T73	0	182	0	0
T78	0	60	0	0
T135	0	6	0	0
T269	0	106	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	285	0	0
T2	11153	2	0	0
T3	37660	6	0	0
T7	11771	0	0	0
T8	424352	0	0	0
T13	0	3	0	0
T21	490	0	0	0
T34	946	0	0	0
T36	0	5	0	0
T37	0	2	0	0
T38	0	3	0	0
T48	10437	0	0	0
T60	560	0	0	0
T65	423	0	0	0
T68	491	0	0	0
T73	0	4	0	0
T78	0	1	0	0
T135	0	1	0	0
T269	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5701944	0	0
T1	7230	6829	0	0
T4	26326	17889	0	0
T5	652	251	0	0
T6	507	106	0	0
T14	539	138	0	0
T15	501	100	0	0
T16	742	341	0	0
T17	428	27	0	0
T18	493	92	0	0
T19	5216	4815	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	5703667	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	377	0	0
T2	11153	2	0	0
T3	37660	6	0	0
T7	11771	0	0	0
T8	424352	0	0	0
T11	0	9	0	0
T13	0	3	0	0
T21	490	0	0	0
T34	946	0	0	0
T36	0	6	0	0
T37	0	3	0	0
T48	10437	0	0	0
T60	560	0	0	0
T65	423	0	0	0
T68	491	0	0	0
T73	0	5	0	0
T78	0	1	0	0
T79	0	3	0	0
T159	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	331	0	0
T2	11153	2	0	0
T3	37660	6	0	0
T7	11771	0	0	0
T8	424352	0	0	0
T11	0	8	0	0
T13	0	3	0	0
T21	490	0	0	0
T34	946	0	0	0
T36	0	5	0	0
T37	0	2	0	0
T38	0	3	0	0
T48	10437	0	0	0
T60	560	0	0	0
T65	423	0	0	0
T68	491	0	0	0
T73	0	4	0	0
T78	0	1	0	0
T79	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	285	0	0
T2	11153	2	0	0
T3	37660	6	0	0
T7	11771	0	0	0
T8	424352	0	0	0
T13	0	3	0	0
T21	490	0	0	0
T34	946	0	0	0
T36	0	5	0	0
T37	0	2	0	0
T38	0	3	0	0
T48	10437	0	0	0
T60	560	0	0	0
T65	423	0	0	0
T68	491	0	0	0
T73	0	4	0	0
T78	0	1	0	0
T135	0	1	0	0
T269	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	285	0	0
T2	11153	2	0	0
T3	37660	6	0	0
T7	11771	0	0	0
T8	424352	0	0	0
T13	0	3	0	0
T21	490	0	0	0
T34	946	0	0	0
T36	0	5	0	0
T37	0	2	0	0
T38	0	3	0	0
T48	10437	0	0	0
T60	560	0	0	0
T65	423	0	0	0
T68	491	0	0	0
T73	0	4	0	0
T78	0	1	0	0
T135	0	1	0	0
T269	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	14034	0	0
T2	11153	13	0	0
T3	37660	177	0	0
T7	11771	0	0	0
T8	424352	0	0	0
T13	0	137	0	0
T21	490	0	0	0
T34	946	0	0	0
T36	0	260	0	0
T37	0	163	0	0
T38	0	187	0	0
T48	10437	0	0	0
T60	560	0	0	0
T65	423	0	0	0
T68	491	0	0	0
T73	0	178	0	0
T78	0	59	0	0
T135	0	5	0	0
T269	0	101	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	6058011	0	0
T1	7230	6830	0	0
T4	26326	17911	0	0
T5	652	252	0	0
T6	507	107	0	0
T14	539	139	0	0
T15	501	101	0	0
T16	742	342	0	0
T17	428	28	0	0
T18	493	93	0	0
T19	5216	4816	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6727276	257	0	0
T2	11153	2	0	0
T3	37660	3	0	0
T7	11771	0	0	0
T8	424352	0	0	0
T13	0	3	0	0
T21	490	0	0	0
T34	946	0	0	0
T36	0	5	0	0
T37	0	2	0	0
T38	0	3	0	0
T48	10437	0	0	0
T60	560	0	0	0
T65	423	0	0	0
T68	491	0	0	0
T73	0	4	0	0
T78	0	1	0	0
T135	0	1	0	0
T269	0	5	0	0