Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T13
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T13
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T16,T28,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T16,T28,T29

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T16,T28,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T28,T29
1	0	Covered	T1,T5,T13
1	1	Covered	T16,T28,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T28,T29
0	1	Covered	T110,T111,T127
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T28,T29
0	1	Covered	T16,T28,T29
1	0	Covered	T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T28,T29
1	-	Covered	T16,T28,T29

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T16,T28,T29
DetectSt	168	Covered	T16,T28,T29
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T16,T28,T29

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T16,T28,T29
DebounceSt->IdleSt	163	Covered	T38,T119,T153
DetectSt->IdleSt	186	Covered	T110,T111,T127
DetectSt->StableSt	191	Covered	T16,T28,T29
IdleSt->DebounceSt	148	Covered	T16,T28,T29
StableSt->IdleSt	206	Covered	T16,T28,T29

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T28,T29
0	1	Covered	T16,T28,T29
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T28,T29
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T28,T29
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T38
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T28,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T119,T153,T154
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T28,T29
DetectSt	-	-	-	-	1	-	-	Covered	T110,T111,T127
DetectSt	-	-	-	-	0	1	-	Covered	T16,T28,T29
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T16,T28,T29
StableSt	-	-	-	-	-	-	0	Covered	T16,T28,T29
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7109587	221	0	0
CntIncr_A	7109587	162867	0	0
CntNoWrap_A	7109587	6483416	0	0
DetectStDropOut_A	7109587	4	0	0
DetectedOut_A	7109587	684	0	0
DetectedPulseOut_A	7109587	99	0	0
DisabledIdleSt_A	7109587	6315735	0	0
DisabledNoDetection_A	7109587	6318035	0	0
EnterDebounceSt_A	7109587	120	0	0
EnterDetectSt_A	7109587	103	0	0
EnterStableSt_A	7109587	99	0	0
PulseIsPulse_A	7109587	99	0	0
StayInStableSt	7109587	584	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7109587	6707	0	0
gen_low_level_sva.LowLevelEvent_A	7109587	6485978	0	0
gen_not_sticky_sva.StableStDropOut_A	7109587	97	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	221	0	0
T2	12694	0	0	0
T11	0	6	0	0
T16	688	4	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T24	493	0	0	0
T26	522	0	0	0
T28	724	6	0	0
T29	0	4	0	0
T31	2131	0	0	0
T38	0	1	0	0
T54	0	4	0	0
T55	0	2	0	0
T57	0	2	0	0
T58	506	0	0	0
T119	0	2	0	0
T120	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	162867	0	0
T2	12694	0	0	0
T11	0	193	0	0
T16	688	54	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T24	493	0	0	0
T26	522	0	0	0
T28	724	177	0	0
T29	0	107	0	0
T31	2131	0	0	0
T38	0	22	0	0
T54	0	80	0	0
T55	0	21	0	0
T57	0	57072	0	0
T58	506	0	0	0
T119	0	133	0	0
T120	0	57	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6483416	0	0
T1	16996	16569	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	283	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	4	0	0
T110	10589	1	0	0
T111	34377	1	0	0
T123	5171	0	0	0
T127	0	1	0	0
T131	0	1	0	0
T135	62929	0	0	0
T136	438	0	0	0
T137	2981	0	0	0
T138	407	0	0	0
T139	403	0	0	0
T140	616	0	0	0
T141	5220	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	684	0	0
T2	12694	0	0	0
T11	0	16	0	0
T16	688	18	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T24	493	0	0	0
T26	522	0	0	0
T28	724	17	0	0
T29	0	10	0	0
T31	2131	0	0	0
T54	0	12	0	0
T55	0	11	0	0
T57	0	7	0	0
T58	506	0	0	0
T120	0	5	0	0
T142	0	31	0	0
T143	0	10	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	99	0	0
T2	12694	0	0	0
T11	0	3	0	0
T16	688	2	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T24	493	0	0	0
T26	522	0	0	0
T28	724	3	0	0
T29	0	2	0	0
T31	2131	0	0	0
T54	0	2	0	0
T55	0	1	0	0
T57	0	1	0	0
T58	506	0	0	0
T120	0	1	0	0
T142	0	3	0	0
T143	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6315735	0	0
T1	16996	16569	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	150	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6318035	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	151	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	120	0	0
T2	12694	0	0	0
T11	0	3	0	0
T16	688	2	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T24	493	0	0	0
T26	522	0	0	0
T28	724	3	0	0
T29	0	2	0	0
T31	2131	0	0	0
T38	0	1	0	0
T54	0	2	0	0
T55	0	1	0	0
T57	0	1	0	0
T58	506	0	0	0
T119	0	2	0	0
T120	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	103	0	0
T2	12694	0	0	0
T11	0	3	0	0
T16	688	2	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T24	493	0	0	0
T26	522	0	0	0
T28	724	3	0	0
T29	0	2	0	0
T31	2131	0	0	0
T54	0	2	0	0
T55	0	1	0	0
T57	0	1	0	0
T58	506	0	0	0
T120	0	1	0	0
T142	0	3	0	0
T143	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	99	0	0
T2	12694	0	0	0
T11	0	3	0	0
T16	688	2	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T24	493	0	0	0
T26	522	0	0	0
T28	724	3	0	0
T29	0	2	0	0
T31	2131	0	0	0
T54	0	2	0	0
T55	0	1	0	0
T57	0	1	0	0
T58	506	0	0	0
T120	0	1	0	0
T142	0	3	0	0
T143	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	99	0	0
T2	12694	0	0	0
T11	0	3	0	0
T16	688	2	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T24	493	0	0	0
T26	522	0	0	0
T28	724	3	0	0
T29	0	2	0	0
T31	2131	0	0	0
T54	0	2	0	0
T55	0	1	0	0
T57	0	1	0	0
T58	506	0	0	0
T120	0	1	0	0
T142	0	3	0	0
T143	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	584	0	0
T2	12694	0	0	0
T11	0	13	0	0
T16	688	16	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T24	493	0	0	0
T26	522	0	0	0
T28	724	14	0	0
T29	0	8	0	0
T31	2131	0	0	0
T54	0	10	0	0
T55	0	10	0	0
T57	0	6	0	0
T58	506	0	0	0
T120	0	4	0	0
T142	0	28	0	0
T143	0	8	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6707	0	0
T1	16996	9	0	0
T5	522	4	0	0
T6	409	0	0	0
T13	522	4	0	0
T14	502	3	0	0
T15	589	0	0	0
T16	688	3	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	6	0	0
T24	0	6	0	0
T26	0	5	0	0
T31	0	9	0	0
T58	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6485978	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	97	0	0
T2	12694	0	0	0
T11	0	3	0	0
T16	688	2	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T24	493	0	0	0
T26	522	0	0	0
T28	724	3	0	0
T29	0	2	0	0
T31	2131	0	0	0
T54	0	2	0	0
T55	0	1	0	0
T57	0	1	0	0
T58	506	0	0	0
T120	0	1	0	0
T142	0	3	0	0
T143	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T13
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T13
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T23,T9,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T23,T9,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T9,T10,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T23,T9,T10
1	0	Covered	T1,T5,T13
1	1	Covered	T23,T9,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T10,T12
0	1	Covered	T65,T81,T118
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T10,T12
0	1	Unreachable
1	0	Covered	T9,T10,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T23,T9,T10
DetectSt	168	Covered	T9,T10,T12
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T9,T10,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T10,T12
DebounceSt->IdleSt	163	Covered	T23,T38,T146
DetectSt->IdleSt	186	Covered	T65,T81,T118
DetectSt->StableSt	191	Covered	T9,T10,T12
IdleSt->DebounceSt	148	Covered	T23,T9,T10
StableSt->IdleSt	206	Covered	T9,T10,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T23,T9,T10
0	1	Covered	T23,T9,T10
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T12
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T23,T9,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T38,T61
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T10,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T23,T146,T147
DebounceSt	-	0	0	-	-	-	-	Covered	T23,T9,T10
DetectSt	-	-	-	-	1	-	-	Covered	T65,T81,T118
DetectSt	-	-	-	-	0	1	-	Covered	T9,T10,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T10,T12
StableSt	-	-	-	-	-	-	0	Covered	T9,T10,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7109587	192	0	0
CntIncr_A	7109587	21658	0	0
CntNoWrap_A	7109587	6483445	0	0
DetectStDropOut_A	7109587	23	0	0
DetectedOut_A	7109587	15509	0	0
DetectedPulseOut_A	7109587	48	0	0
DisabledIdleSt_A	7109587	5630635	0	0
DisabledNoDetection_A	7109587	5632974	0	0
EnterDebounceSt_A	7109587	123	0	0
EnterDetectSt_A	7109587	71	0	0
EnterStableSt_A	7109587	48	0	0
PulseIsPulse_A	7109587	48	0	0
StayInStableSt	7109587	15461	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7109587	6707	0	0
gen_low_level_sva.LowLevelEvent_A	7109587	6485978	0	0
gen_sticky_sva.StableStDropOut_A	7109587	335885	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	192	0	0
T8	3734	0	0	0
T9	1551	2	0	0
T10	706	2	0	0
T11	15931	0	0	0
T12	70930	2	0	0
T23	859	1	0	0
T38	0	1	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T65	0	4	0	0
T66	0	2	0	0
T76	502	0	0	0
T79	0	4	0	0
T80	0	2	0	0
T81	0	14	0	0
T82	502	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	21658	0	0
T8	3734	0	0	0
T9	1551	90	0	0
T10	706	39	0	0
T11	15931	0	0	0
T12	70930	14967	0	0
T23	859	25	0	0
T38	0	74	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T65	0	20	0	0
T66	0	11	0	0
T76	502	0	0	0
T79	0	62	0	0
T80	0	56	0	0
T81	0	252	0	0
T82	502	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6483445	0	0
T1	16996	16569	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	23	0	0
T37	51911	0	0	0
T56	751	0	0	0
T65	3177	1	0	0
T66	1623	0	0	0
T81	0	5	0	0
T113	0	2	0	0
T118	0	1	0	0
T144	17113	0	0	0
T155	0	6	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	3	0	0
T160	0	1	0	0
T161	447	0	0	0
T162	703	0	0	0
T163	529	0	0	0
T164	412	0	0	0
T165	406	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	15509	0	0
T9	1551	11	0	0
T10	706	3	0	0
T11	15931	0	0	0
T12	70930	8497	0	0
T52	4068	0	0	0
T53	6617	0	0	0
T65	0	25	0	0
T66	0	53	0	0
T76	502	0	0	0
T79	0	302	0	0
T80	0	54	0	0
T81	0	153	0	0
T82	502	0	0	0
T146	0	100	0	0
T148	0	301	0	0
T151	426	0	0	0
T152	441	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	48	0	0
T9	1551	1	0	0
T10	706	1	0	0
T11	15931	0	0	0
T12	70930	1	0	0
T52	4068	0	0	0
T53	6617	0	0	0
T65	0	1	0	0
T66	0	1	0	0
T76	502	0	0	0
T79	0	2	0	0
T80	0	1	0	0
T81	0	2	0	0
T82	502	0	0	0
T146	0	1	0	0
T148	0	1	0	0
T151	426	0	0	0
T152	441	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	5630635	0	0
T1	16996	16569	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	5632974	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	123	0	0
T8	3734	0	0	0
T9	1551	1	0	0
T10	706	1	0	0
T11	15931	0	0	0
T12	70930	1	0	0
T23	859	1	0	0
T38	0	2	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T65	0	2	0	0
T66	0	1	0	0
T76	502	0	0	0
T79	0	2	0	0
T80	0	1	0	0
T81	0	7	0	0
T82	502	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	71	0	0
T9	1551	1	0	0
T10	706	1	0	0
T11	15931	0	0	0
T12	70930	1	0	0
T52	4068	0	0	0
T53	6617	0	0	0
T65	0	2	0	0
T66	0	1	0	0
T76	502	0	0	0
T79	0	2	0	0
T80	0	1	0	0
T81	0	7	0	0
T82	502	0	0	0
T146	0	1	0	0
T148	0	1	0	0
T151	426	0	0	0
T152	441	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	48	0	0
T9	1551	1	0	0
T10	706	1	0	0
T11	15931	0	0	0
T12	70930	1	0	0
T52	4068	0	0	0
T53	6617	0	0	0
T65	0	1	0	0
T66	0	1	0	0
T76	502	0	0	0
T79	0	2	0	0
T80	0	1	0	0
T81	0	2	0	0
T82	502	0	0	0
T146	0	1	0	0
T148	0	1	0	0
T151	426	0	0	0
T152	441	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	48	0	0
T9	1551	1	0	0
T10	706	1	0	0
T11	15931	0	0	0
T12	70930	1	0	0
T52	4068	0	0	0
T53	6617	0	0	0
T65	0	1	0	0
T66	0	1	0	0
T76	502	0	0	0
T79	0	2	0	0
T80	0	1	0	0
T81	0	2	0	0
T82	502	0	0	0
T146	0	1	0	0
T148	0	1	0	0
T151	426	0	0	0
T152	441	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	15461	0	0
T9	1551	10	0	0
T10	706	2	0	0
T11	15931	0	0	0
T12	70930	8496	0	0
T52	4068	0	0	0
T53	6617	0	0	0
T65	0	24	0	0
T66	0	52	0	0
T76	502	0	0	0
T79	0	300	0	0
T80	0	53	0	0
T81	0	151	0	0
T82	502	0	0	0
T146	0	99	0	0
T148	0	300	0	0
T151	426	0	0	0
T152	441	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6707	0	0
T1	16996	9	0	0
T5	522	4	0	0
T6	409	0	0	0
T13	522	4	0	0
T14	502	3	0	0
T15	589	0	0	0
T16	688	3	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	6	0	0
T24	0	6	0	0
T26	0	5	0	0
T31	0	9	0	0
T58	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6485978	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	335885	0	0
T9	1551	55	0	0
T10	706	35	0	0
T11	15931	0	0	0
T12	70930	30	0	0
T52	4068	0	0	0
T53	6617	0	0	0
T65	0	289	0	0
T66	0	450	0	0
T76	502	0	0	0
T79	0	967	0	0
T80	0	27	0	0
T81	0	966	0	0
T82	502	0	0	0
T146	0	39	0	0
T148	0	152819	0	0
T151	426	0	0	0
T152	441	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T5,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T5,T13,T14
1	1	Covered	T5,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T23,T9,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T23,T9,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T23,T9,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T23,T9,T10
1	0	Covered	T5,T13,T14
1	1	Covered	T23,T9,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T10,T12
0	1	Covered	T23,T79,T117
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T10,T12
0	1	Unreachable
1	0	Covered	T9,T10,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T23,T9,T10
DetectSt	168	Covered	T23,T9,T10
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T9,T10,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T23,T9,T10
DebounceSt->IdleSt	163	Covered	T65,T38,T79
DetectSt->IdleSt	186	Covered	T23,T79,T117
DetectSt->StableSt	191	Covered	T9,T10,T12
IdleSt->DebounceSt	148	Covered	T23,T9,T10
StableSt->IdleSt	206	Covered	T9,T10,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T23,T9,T10
0	1	Covered	T23,T9,T10
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T23,T9,T10
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T23,T9,T10
IdleSt	0	-	-	-	-	-	-	Covered	T5,T13,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T38,T61
DebounceSt	-	0	1	1	-	-	-	Covered	T23,T9,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T65,T79,T80
DebounceSt	-	0	0	-	-	-	-	Covered	T23,T9,T10
DetectSt	-	-	-	-	1	-	-	Covered	T23,T79,T117
DetectSt	-	-	-	-	0	1	-	Covered	T9,T10,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T10,T12
StableSt	-	-	-	-	-	-	0	Covered	T9,T10,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7109587	183	0	0
CntIncr_A	7109587	238486	0	0
CntNoWrap_A	7109587	6483454	0	0
DetectStDropOut_A	7109587	18	0	0
DetectedOut_A	7109587	109509	0	0
DetectedPulseOut_A	7109587	46	0	0
DisabledIdleSt_A	7109587	5630635	0	0
DisabledNoDetection_A	7109587	5632974	0	0
EnterDebounceSt_A	7109587	121	0	0
EnterDetectSt_A	7109587	64	0	0
EnterStableSt_A	7109587	46	0	0
PulseIsPulse_A	7109587	46	0	0
StayInStableSt	7109587	109463	0	0
gen_high_level_sva.HighLevelEvent_A	7109587	6485978	0	0
gen_sticky_sva.StableStDropOut_A	7109587	446043	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	183	0	0
T8	3734	0	0	0
T9	1551	2	0	0
T10	706	2	0	0
T11	15931	0	0	0
T12	70930	2	0	0
T23	859	2	0	0
T38	0	1	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T65	0	4	0	0
T66	0	2	0	0
T76	502	0	0	0
T79	0	7	0	0
T80	0	1	0	0
T81	0	6	0	0
T82	502	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	238486	0	0
T8	3734	0	0	0
T9	1551	44	0	0
T10	706	19	0	0
T11	15931	0	0	0
T12	70930	79	0	0
T23	859	44	0	0
T38	0	75	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T65	0	340	0	0
T66	0	85	0	0
T76	502	0	0	0
T79	0	316	0	0
T80	0	14	0	0
T81	0	285	0	0
T82	502	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6483454	0	0
T1	16996	16569	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	18	0	0
T8	3734	0	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T12	70930	0	0	0
T23	859	1	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T76	502	0	0	0
T79	0	1	0	0
T82	502	0	0	0
T91	0	1	0	0
T115	0	2	0	0
T117	0	2	0	0
T155	0	5	0	0
T156	0	3	0	0
T158	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	109509	0	0
T9	1551	14	0	0
T10	706	2	0	0
T11	15931	0	0	0
T12	70930	55	0	0
T52	4068	0	0	0
T53	6617	0	0	0
T66	0	336	0	0
T76	502	0	0	0
T79	0	324	0	0
T81	0	1649	0	0
T82	502	0	0	0
T146	0	227	0	0
T147	0	27	0	0
T149	0	9704	0	0
T150	0	593	0	0
T151	426	0	0	0
T152	441	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	46	0	0
T9	1551	1	0	0
T10	706	1	0	0
T11	15931	0	0	0
T12	70930	1	0	0
T52	4068	0	0	0
T53	6617	0	0	0
T66	0	1	0	0
T76	502	0	0	0
T79	0	2	0	0
T81	0	3	0	0
T82	502	0	0	0
T146	0	1	0	0
T147	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	426	0	0	0
T152	441	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	5630635	0	0
T1	16996	16569	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	5632974	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	121	0	0
T8	3734	0	0	0
T9	1551	1	0	0
T10	706	1	0	0
T11	15931	0	0	0
T12	70930	1	0	0
T23	859	1	0	0
T38	0	2	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T65	0	4	0	0
T66	0	1	0	0
T76	502	0	0	0
T79	0	4	0	0
T80	0	1	0	0
T81	0	3	0	0
T82	502	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	64	0	0
T8	3734	0	0	0
T9	1551	1	0	0
T10	706	1	0	0
T11	15931	0	0	0
T12	70930	1	0	0
T23	859	1	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T66	0	1	0	0
T76	502	0	0	0
T79	0	3	0	0
T81	0	3	0	0
T82	502	0	0	0
T146	0	1	0	0
T147	0	1	0	0
T149	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	46	0	0
T9	1551	1	0	0
T10	706	1	0	0
T11	15931	0	0	0
T12	70930	1	0	0
T52	4068	0	0	0
T53	6617	0	0	0
T66	0	1	0	0
T76	502	0	0	0
T79	0	2	0	0
T81	0	3	0	0
T82	502	0	0	0
T146	0	1	0	0
T147	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	426	0	0	0
T152	441	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	46	0	0
T9	1551	1	0	0
T10	706	1	0	0
T11	15931	0	0	0
T12	70930	1	0	0
T52	4068	0	0	0
T53	6617	0	0	0
T66	0	1	0	0
T76	502	0	0	0
T79	0	2	0	0
T81	0	3	0	0
T82	502	0	0	0
T146	0	1	0	0
T147	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	426	0	0	0
T152	441	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	109463	0	0
T9	1551	13	0	0
T10	706	1	0	0
T11	15931	0	0	0
T12	70930	54	0	0
T52	4068	0	0	0
T53	6617	0	0	0
T66	0	335	0	0
T76	502	0	0	0
T79	0	322	0	0
T81	0	1646	0	0
T82	502	0	0	0
T146	0	226	0	0
T147	0	26	0	0
T149	0	9703	0	0
T150	0	592	0	0
T151	426	0	0	0
T152	441	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6485978	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	446043	0	0
T9	1551	102	0	0
T10	706	45	0	0
T11	15931	0	0	0
T12	70930	23359	0	0
T52	4068	0	0	0
T53	6617	0	0	0
T66	0	95	0	0
T76	502	0	0	0
T79	0	684	0	0
T81	0	232	0	0
T82	502	0	0	0
T146	0	70	0	0
T147	0	279	0	0
T149	0	52	0	0
T150	0	113	0	0
T151	426	0	0	0
T152	441	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T23,T9,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T23,T9,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T9,T10,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T23,T9,T10
1	0	Covered	T1,T5,T13
1	1	Covered	T23,T9,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T10,T12
0	1	Covered	T113,T114,T115
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T10,T12
0	1	Unreachable
1	0	Covered	T9,T10,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T23,T9,T10
DetectSt	168	Covered	T9,T10,T12
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T9,T10,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T10,T12
DebounceSt->IdleSt	163	Covered	T23,T65,T38
DetectSt->IdleSt	186	Covered	T113,T114,T115
DetectSt->StableSt	191	Covered	T9,T10,T12
IdleSt->DebounceSt	148	Covered	T23,T9,T10
StableSt->IdleSt	206	Covered	T9,T10,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T23,T9,T10
0	1	Covered	T23,T9,T10
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T12
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T23,T9,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T38,T61
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T10,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T23,T65,T168
DebounceSt	-	0	0	-	-	-	-	Covered	T23,T9,T10
DetectSt	-	-	-	-	1	-	-	Covered	T113,T114,T115
DetectSt	-	-	-	-	0	1	-	Covered	T9,T10,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T10,T12
StableSt	-	-	-	-	-	-	0	Covered	T9,T10,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7109587	159	0	0
CntIncr_A	7109587	307496	0	0
CntNoWrap_A	7109587	6483478	0	0
DetectStDropOut_A	7109587	8	0	0
DetectedOut_A	7109587	179064	0	0
DetectedPulseOut_A	7109587	54	0	0
DisabledIdleSt_A	7109587	5630635	0	0
DisabledNoDetection_A	7109587	5632974	0	0
EnterDebounceSt_A	7109587	99	0	0
EnterDetectSt_A	7109587	62	0	0
EnterStableSt_A	7109587	54	0	0
PulseIsPulse_A	7109587	54	0	0
StayInStableSt	7109587	179010	0	0
gen_high_event_sva.HighLevelEvent_A	7109587	6485978	0	0
gen_high_level_sva.HighLevelEvent_A	7109587	6485978	0	0
gen_sticky_sva.StableStDropOut_A	7109587	363391	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	159	0	0
T8	3734	0	0	0
T9	1551	2	0	0
T10	706	2	0	0
T11	15931	0	0	0
T12	70930	2	0	0
T23	859	1	0	0
T38	0	1	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T65	0	4	0	0
T66	0	2	0	0
T76	502	0	0	0
T79	0	4	0	0
T80	0	2	0	0
T81	0	6	0	0
T82	502	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	307496	0	0
T8	3734	0	0	0
T9	1551	90	0	0
T10	706	28	0	0
T11	15931	0	0	0
T12	70930	30	0	0
T23	859	23	0	0
T38	0	74	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T65	0	92	0	0
T66	0	82	0	0
T76	502	0	0	0
T79	0	190	0	0
T80	0	68	0	0
T81	0	54	0	0
T82	502	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6483478	0	0
T1	16996	16569	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	8	0	0
T113	183710	5	0	0
T114	0	2	0	0
T115	0	1	0	0
T169	421	0	0	0
T170	5215	0	0	0
T171	6108	0	0	0
T172	5321	0	0	0
T173	26768	0	0	0
T174	522	0	0	0
T175	521	0	0	0
T176	493	0	0	0
T177	30590	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	179064	0	0
T9	1551	55	0	0
T10	706	22	0	0
T11	15931	0	0	0
T12	70930	16	0	0
T52	4068	0	0	0
T53	6617	0	0	0
T66	0	394	0	0
T76	502	0	0	0
T79	0	1266	0	0
T80	0	19	0	0
T81	0	274	0	0
T82	502	0	0	0
T146	0	136	0	0
T147	0	133	0	0
T148	0	323	0	0
T151	426	0	0	0
T152	441	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	54	0	0
T9	1551	1	0	0
T10	706	1	0	0
T11	15931	0	0	0
T12	70930	1	0	0
T52	4068	0	0	0
T53	6617	0	0	0
T66	0	1	0	0
T76	502	0	0	0
T79	0	2	0	0
T80	0	1	0	0
T81	0	3	0	0
T82	502	0	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T151	426	0	0	0
T152	441	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	5630635	0	0
T1	16996	16569	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	5632974	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	99	0	0
T8	3734	0	0	0
T9	1551	1	0	0
T10	706	1	0	0
T11	15931	0	0	0
T12	70930	1	0	0
T23	859	1	0	0
T38	0	2	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T65	0	4	0	0
T66	0	1	0	0
T76	502	0	0	0
T79	0	2	0	0
T80	0	1	0	0
T81	0	3	0	0
T82	502	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	62	0	0
T9	1551	1	0	0
T10	706	1	0	0
T11	15931	0	0	0
T12	70930	1	0	0
T52	4068	0	0	0
T53	6617	0	0	0
T66	0	1	0	0
T76	502	0	0	0
T79	0	2	0	0
T80	0	1	0	0
T81	0	3	0	0
T82	502	0	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T151	426	0	0	0
T152	441	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	54	0	0
T9	1551	1	0	0
T10	706	1	0	0
T11	15931	0	0	0
T12	70930	1	0	0
T52	4068	0	0	0
T53	6617	0	0	0
T66	0	1	0	0
T76	502	0	0	0
T79	0	2	0	0
T80	0	1	0	0
T81	0	3	0	0
T82	502	0	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T151	426	0	0	0
T152	441	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	54	0	0
T9	1551	1	0	0
T10	706	1	0	0
T11	15931	0	0	0
T12	70930	1	0	0
T52	4068	0	0	0
T53	6617	0	0	0
T66	0	1	0	0
T76	502	0	0	0
T79	0	2	0	0
T80	0	1	0	0
T81	0	3	0	0
T82	502	0	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T151	426	0	0	0
T152	441	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	179010	0	0
T9	1551	54	0	0
T10	706	21	0	0
T11	15931	0	0	0
T12	70930	15	0	0
T52	4068	0	0	0
T53	6617	0	0	0
T66	0	393	0	0
T76	502	0	0	0
T79	0	1264	0	0
T80	0	18	0	0
T81	0	271	0	0
T82	502	0	0	0
T146	0	135	0	0
T147	0	132	0	0
T148	0	322	0	0
T151	426	0	0	0
T152	441	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6485978	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6485978	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	363391	0	0
T9	1551	25	0	0
T10	706	29	0	0
T11	15931	0	0	0
T12	70930	23461	0	0
T52	4068	0	0	0
T53	6617	0	0	0
T66	0	57	0	0
T76	502	0	0	0
T79	0	86	0	0
T80	0	54	0	0
T81	0	1867	0	0
T82	502	0	0	0
T146	0	179	0	0
T147	0	105	0	0
T148	0	152830	0	0
T151	426	0	0	0
T152	441	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T38,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T7,T38,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T38,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T43,T38
1	0	Covered	T1,T5,T6
1	1	Covered	T7,T38,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T38,T39
0	1	Covered	T178
1	0	Covered	T61

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T38,T39
0	1	Covered	T39,T47,T179
1	0	Covered	T38

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T38,T39
1	-	Covered	T39,T47,T179

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T38,T39
DetectSt	168	Covered	T7,T38,T39
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T7,T38,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T38,T39
DebounceSt->IdleSt	163	Covered	T179,T159
DetectSt->IdleSt	186	Covered	T61,T178
DetectSt->StableSt	191	Covered	T7,T38,T39
IdleSt->DebounceSt	148	Covered	T7,T38,T39
StableSt->IdleSt	206	Covered	T7,T38,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T38,T39
0	1	Covered	T7,T38,T39
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T38,T39
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T38,T39
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T38,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T179,T159
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T38,T39
DetectSt	-	-	-	-	1	-	-	Covered	T61,T178
DetectSt	-	-	-	-	0	1	-	Covered	T7,T38,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T38,T39,T47
StableSt	-	-	-	-	-	-	0	Covered	T7,T38,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7109587	88	0	0
CntIncr_A	7109587	16314	0	0
CntNoWrap_A	7109587	6483549	0	0
DetectStDropOut_A	7109587	1	0	0
DetectedOut_A	7109587	6271	0	0
DetectedPulseOut_A	7109587	41	0	0
DisabledIdleSt_A	7109587	6400051	0	0
DisabledNoDetection_A	7109587	6402332	0	0
EnterDebounceSt_A	7109587	45	0	0
EnterDetectSt_A	7109587	43	0	0
EnterStableSt_A	7109587	41	0	0
PulseIsPulse_A	7109587	41	0	0
StayInStableSt	7109587	6207	0	0
gen_high_level_sva.HighLevelEvent_A	7109587	6485978	0	0
gen_not_sticky_sva.StableStDropOut_A	7109587	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	88	0	0
T7	29986	2	0	0
T8	3734	0	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T38	0	2	0	0
T39	0	4	0	0
T47	0	4	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T116	0	2	0	0
T149	0	4	0	0
T179	0	3	0	0
T180	0	2	0	0
T181	0	4	0	0
T182	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	16314	0	0
T7	29986	3596	0	0
T8	3734	0	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T38	0	18	0	0
T39	0	156	0	0
T47	0	68	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T116	0	96	0	0
T149	0	45	0	0
T179	0	76	0	0
T180	0	91	0	0
T181	0	151	0	0
T182	0	43	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6483549	0	0
T1	16996	16569	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	1	0	0
T178	54012	1	0	0
T183	423	0	0	0
T184	1163	0	0	0
T185	665	0	0	0
T186	402	0	0	0
T187	6619	0	0	0
T188	619	0	0	0
T189	409	0	0	0
T190	932	0	0	0
T191	759	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6271	0	0
T7	29986	3640	0	0
T8	3734	0	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T38	0	11	0	0
T39	0	84	0	0
T47	0	117	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T116	0	236	0	0
T149	0	203	0	0
T179	0	1	0	0
T180	0	40	0	0
T181	0	165	0	0
T182	0	105	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	41	0	0
T7	29986	1	0	0
T8	3734	0	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T47	0	2	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T116	0	1	0	0
T149	0	2	0	0
T179	0	1	0	0
T180	0	1	0	0
T181	0	2	0	0
T182	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6400051	0	0
T1	16996	16569	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6402332	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	45	0	0
T7	29986	1	0	0
T8	3734	0	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T47	0	2	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T116	0	1	0	0
T149	0	2	0	0
T179	0	2	0	0
T180	0	1	0	0
T181	0	2	0	0
T182	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	43	0	0
T7	29986	1	0	0
T8	3734	0	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T47	0	2	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T116	0	1	0	0
T149	0	2	0	0
T179	0	1	0	0
T180	0	1	0	0
T181	0	2	0	0
T182	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	41	0	0
T7	29986	1	0	0
T8	3734	0	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T47	0	2	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T116	0	1	0	0
T149	0	2	0	0
T179	0	1	0	0
T180	0	1	0	0
T181	0	2	0	0
T182	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	41	0	0
T7	29986	1	0	0
T8	3734	0	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T47	0	2	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T116	0	1	0	0
T149	0	2	0	0
T179	0	1	0	0
T180	0	1	0	0
T181	0	2	0	0
T182	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6207	0	0
T7	29986	3638	0	0
T8	3734	0	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T38	0	10	0	0
T39	0	81	0	0
T47	0	114	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T116	0	235	0	0
T149	0	199	0	0
T180	0	38	0	0
T181	0	161	0	0
T182	0	104	0	0
T192	0	38	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6485978	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	17	0	0
T34	24784	0	0	0
T39	833	1	0	0
T47	0	1	0	0
T110	10589	0	0	0
T116	0	1	0	0
T118	0	1	0	0
T122	20089	0	0	0
T179	0	1	0	0
T182	0	1	0	0
T193	0	1	0	0
T194	0	1	0	0
T195	0	1	0	0
T196	0	2	0	0
T197	726	0	0	0
T198	422	0	0	0
T199	698	0	0	0
T200	491	0	0	0
T201	491	0	0	0
T202	422	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T8,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T7,T8,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T8,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T42
1	0	Covered	T1,T5,T13
1	1	Covered	T7,T8,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T42
0	1	Covered	T39,T203
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T42
0	1	Covered	T7,T8,T42
1	0	Covered	T38

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T8,T42
1	-	Covered	T7,T8,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T8,T42
DetectSt	168	Covered	T7,T8,T42
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T7,T8,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T8,T42
DebounceSt->IdleSt	163	Covered	T61,T178,T191
DetectSt->IdleSt	186	Covered	T39,T203
DetectSt->StableSt	191	Covered	T7,T8,T42
IdleSt->DebounceSt	148	Covered	T7,T8,T42
StableSt->IdleSt	206	Covered	T7,T8,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T8,T42
0	1	Covered	T7,T8,T42
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T42
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T8,T42
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T61
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T8,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T178,T191,T204
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T8,T42
DetectSt	-	-	-	-	1	-	-	Covered	T39,T203
DetectSt	-	-	-	-	0	1	-	Covered	T7,T8,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T8,T42
StableSt	-	-	-	-	-	-	0	Covered	T7,T8,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7109587	157	0	0
CntIncr_A	7109587	18388	0	0
CntNoWrap_A	7109587	6483480	0	0
DetectStDropOut_A	7109587	2	0	0
DetectedOut_A	7109587	39478	0	0
DetectedPulseOut_A	7109587	74	0	0
DisabledIdleSt_A	7109587	6399201	0	0
DisabledNoDetection_A	7109587	6401486	0	0
EnterDebounceSt_A	7109587	81	0	0
EnterDetectSt_A	7109587	76	0	0
EnterStableSt_A	7109587	74	0	0
PulseIsPulse_A	7109587	74	0	0
StayInStableSt	7109587	39380	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7109587	2567	0	0
gen_low_level_sva.LowLevelEvent_A	7109587	6485978	0	0
gen_not_sticky_sva.StableStDropOut_A	7109587	49	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	157	0	0
T7	29986	2	0	0
T8	3734	2	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T37	0	4	0	0
T38	0	2	0	0
T39	0	4	0	0
T41	0	4	0	0
T42	0	2	0	0
T45	0	4	0	0
T46	0	4	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T199	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	18388	0	0
T7	29986	3596	0	0
T8	3734	58	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T37	0	110	0	0
T38	0	18	0	0
T39	0	156	0	0
T41	0	72	0	0
T42	0	33	0	0
T45	0	82	0	0
T46	0	106	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T199	0	30	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6483480	0	0
T1	16996	16569	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	2	0	0
T34	24784	0	0	0
T39	833	1	0	0
T110	10589	0	0	0
T122	20089	0	0	0
T197	726	0	0	0
T198	422	0	0	0
T199	698	0	0	0
T200	491	0	0	0
T201	491	0	0	0
T202	422	0	0	0
T203	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	39478	0	0
T7	29986	16617	0	0
T8	3734	346	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T37	0	104	0	0
T38	0	11	0	0
T39	0	24	0	0
T41	0	85	0	0
T42	0	22	0	0
T45	0	127	0	0
T46	0	254	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T199	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	74	0	0
T7	29986	1	0	0
T8	3734	1	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T45	0	2	0	0
T46	0	2	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T199	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6399201	0	0
T1	16996	16569	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6401486	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	81	0	0
T7	29986	1	0	0
T8	3734	1	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T45	0	2	0	0
T46	0	2	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T199	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	76	0	0
T7	29986	1	0	0
T8	3734	1	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T45	0	2	0	0
T46	0	2	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T199	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	74	0	0
T7	29986	1	0	0
T8	3734	1	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T45	0	2	0	0
T46	0	2	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T199	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	74	0	0
T7	29986	1	0	0
T8	3734	1	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T45	0	2	0	0
T46	0	2	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T199	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	39380	0	0
T7	29986	16616	0	0
T8	3734	345	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T37	0	102	0	0
T38	0	10	0	0
T39	0	23	0	0
T41	0	83	0	0
T42	0	21	0	0
T45	0	124	0	0
T46	0	251	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T199	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	2567	0	0
T3	0	20	0	0
T5	522	7	0	0
T6	409	0	0	0
T13	522	4	0	0
T14	502	7	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	4	0	0
T24	0	5	0	0
T26	0	7	0	0
T31	2131	0	0	0
T58	0	6	0	0
T60	0	3	0	0
T72	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6485978	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	49	0	0
T7	29986	1	0	0
T8	3734	1	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T37	0	2	0	0
T39	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T180	0	1	0	0
T199	0	1	0	0