Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T43,T37,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T43,T37,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T43,T38,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T43,T37,T38
1	0	Covered	T1,T5,T6
1	1	Covered	T43,T37,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T43,T38,T45
0	1	Covered	T205,T178
1	0	Covered	T61

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T43,T38,T45
0	1	Covered	T43,T46,T47
1	0	Covered	T38

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T43,T38,T45
1	-	Covered	T43,T46,T47

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T43,T37,T38
DetectSt	168	Covered	T43,T38,T45
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T43,T38,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T43,T38,T45
DebounceSt->IdleSt	163	Covered	T37,T181,T204
DetectSt->IdleSt	186	Covered	T205,T61,T178
DetectSt->StableSt	191	Covered	T43,T38,T45
IdleSt->DebounceSt	148	Covered	T43,T37,T38
StableSt->IdleSt	206	Covered	T43,T38,T46

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T43,T37,T38
0	1	Covered	T43,T37,T38
0	0	Excluded	T1,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T43,T38,T45
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T43,T37,T38
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T43,T38,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T37,T181,T204
DebounceSt	-	0	0	-	-	-	-	Covered	T43,T37,T38
DetectSt	-	-	-	-	1	-	-	Covered	T205,T61,T178
DetectSt	-	-	-	-	0	1	-	Covered	T43,T38,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T43,T38,T46
StableSt	-	-	-	-	-	-	0	Covered	T43,T38,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7109587	65	0	0
CntIncr_A	7109587	1900	0	0
CntNoWrap_A	7109587	6483572	0	0
DetectStDropOut_A	7109587	2	0	0
DetectedOut_A	7109587	1401	0	0
DetectedPulseOut_A	7109587	28	0	0
DisabledIdleSt_A	7109587	6467626	0	0
DisabledNoDetection_A	7109587	6469919	0	0
EnterDebounceSt_A	7109587	34	0	0
EnterDetectSt_A	7109587	31	0	0
EnterStableSt_A	7109587	28	0	0
PulseIsPulse_A	7109587	28	0	0
StayInStableSt	7109587	1359	0	0
gen_high_level_sva.HighLevelEvent_A	7109587	6485978	0	0
gen_not_sticky_sva.StableStDropOut_A	7109587	13	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7109587	65
T37	0	1
T38	0	2
T40	0	2
T43	835	4
T45	0	2
T46	0	4
T47	0	2
T50	22701	0
T55	678	0
T64	800	0
T65	3177	0
T149	0	2
T161	447	0
T181	0	1
T205	0	2
T206	404	0
T207	420	0
T208	506	0
T209	422	0

CntIncr_A

Name	Attempts	Real Successes
Total	7109587	1900
T37	0	55
T38	0	18
T40	0	75
T43	835	118
T45	0	41
T46	0	106
T47	0	34
T50	22701	0
T55	678	0
T64	800	0
T65	3177	0
T149	0	27
T161	447	0
T181	0	91
T205	0	54
T206	404	0
T207	420	0
T208	506	0
T209	422	0

CntNoWrap_A

Name	Attempts	Real Successes
Total	7109587	6483572
T1	16996	16569
T5	522	121
T6	409	8
T13	522	121
T14	502	101
T15	589	188
T16	688	287
T17	407	6
T18	419	18
T19	525	124

DetectStDropOut_A

Name	Attempts	Real Successes
Total	7109587	2
T178	0	1
T205	19452	1
T210	428	0
T211	408	0
T212	435	0
T213	31427	0
T214	421	0
T215	426	0
T216	17880	0
T217	610	0
T218	17044	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7109587	1401
T38	0	12
T40	0	38
T43	835	82
T45	0	120
T46	0	48
T47	0	24
T50	22701	0
T55	678	0
T64	800	0
T65	3177	0
T149	0	43
T161	447	0
T194	0	45
T206	404	0
T207	420	0
T208	506	0
T209	422	0
T219	0	122
T220	0	41

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7109587	28
T38	0	1
T40	0	1
T43	835	2
T45	0	1
T46	0	2
T47	0	1
T50	22701	0
T55	678	0
T64	800	0
T65	3177	0
T149	0	1
T161	447	0
T194	0	1
T206	404	0
T207	420	0
T208	506	0
T209	422	0
T219	0	3
T220	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7109587	6467626
T1	16996	16569
T5	522	121
T6	409	8
T13	522	121
T14	502	101
T15	589	188
T16	688	287
T17	407	6
T18	419	18
T19	525	124

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7109587	6469919
T1	16996	16575
T5	522	122
T6	409	9
T13	522	122
T14	502	102
T15	589	189
T16	688	288
T17	407	7
T18	419	19
T19	525	125

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7109587	34
T37	0	1
T38	0	1
T40	0	1
T43	835	2
T45	0	1
T46	0	2
T47	0	1
T50	22701	0
T55	678	0
T64	800	0
T65	3177	0
T149	0	1
T161	447	0
T181	0	1
T205	0	1
T206	404	0
T207	420	0
T208	506	0
T209	422	0

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7109587	31
T38	0	1
T40	0	1
T43	835	2
T45	0	1
T46	0	2
T47	0	1
T50	22701	0
T55	678	0
T64	800	0
T65	3177	0
T149	0	1
T161	447	0
T194	0	1
T205	0	1
T206	404	0
T207	420	0
T208	506	0
T209	422	0
T219	0	3

EnterStableSt_A

Name	Attempts	Real Successes
Total	7109587	28
T38	0	1
T40	0	1
T43	835	2
T45	0	1
T46	0	2
T47	0	1
T50	22701	0
T55	678	0
T64	800	0
T65	3177	0
T149	0	1
T161	447	0
T194	0	1
T206	404	0
T207	420	0
T208	506	0
T209	422	0
T219	0	3
T220	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7109587	28
T38	0	1
T40	0	1
T43	835	2
T45	0	1
T46	0	2
T47	0	1
T50	22701	0
T55	678	0
T64	800	0
T65	3177	0
T149	0	1
T161	447	0
T194	0	1
T206	404	0
T207	420	0
T208	506	0
T209	422	0
T219	0	3
T220	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7109587	1359
T38	0	11
T40	0	36
T43	835	79
T45	0	118
T46	0	46
T47	0	23
T50	22701	0
T55	678	0
T64	800	0
T65	3177	0
T149	0	42
T161	447	0
T194	0	44
T206	404	0
T207	420	0
T208	506	0
T209	422	0
T219	0	118
T220	0	40

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	7109587	6485978
T1	16996	16575
T5	522	122
T6	409	9
T13	522	122
T14	502	102
T15	589	189
T16	688	288
T17	407	7
T18	419	19
T19	525	125

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7109587	13
T43	835	1
T46	0	2
T47	0	1
T50	22701	0
T55	678	0
T64	800	0
T65	3177	0
T149	0	1
T161	447	0
T194	0	1
T203	0	1
T206	404	0
T207	420	0
T208	506	0
T209	422	0
T219	0	2
T220	0	1
T221	0	1
T222	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T42,T43,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T42,T43,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T42,T43,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T42,T43,T37
1	0	Covered	T1,T5,T13
1	1	Covered	T42,T43,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T42,T43,T37
0	1	Covered	T46,T223,T224
1	0	Covered	T61

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T42,T43,T37
0	1	Covered	T43,T37,T45
1	0	Covered	T38

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T42,T43,T37
1	-	Covered	T43,T37,T45

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T42,T43,T37
DetectSt	168	Covered	T42,T43,T37
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T42,T43,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T42,T43,T37
DebounceSt->IdleSt	163	Covered	T225,T226
DetectSt->IdleSt	186	Covered	T46,T223,T224
DetectSt->StableSt	191	Covered	T42,T43,T37
IdleSt->DebounceSt	148	Covered	T42,T43,T37
StableSt->IdleSt	206	Covered	T42,T43,T37

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T42,T43,T37
0	1	Covered	T42,T43,T37
0	0	Excluded	T1,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T37
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T42,T43,T37
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T42,T43,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T225,T226
DebounceSt	-	0	0	-	-	-	-	Covered	T42,T43,T37
DetectSt	-	-	-	-	1	-	-	Covered	T46,T223,T224
DetectSt	-	-	-	-	0	1	-	Covered	T42,T43,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T43,T37,T38
StableSt	-	-	-	-	-	-	0	Covered	T42,T43,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7109587	132	0	0
CntIncr_A	7109587	8891	0	0
CntNoWrap_A	7109587	6483505	0	0
DetectStDropOut_A	7109587	4	0	0
DetectedOut_A	7109587	21264	0	0
DetectedPulseOut_A	7109587	60	0	0
DisabledIdleSt_A	7109587	6429733	0	0
DisabledNoDetection_A	7109587	6432024	0	0
EnterDebounceSt_A	7109587	67	0	0
EnterDetectSt_A	7109587	65	0	0
EnterStableSt_A	7109587	60	0	0
PulseIsPulse_A	7109587	60	0	0
StayInStableSt	7109587	21179	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7109587	2869	0	0
gen_low_level_sva.LowLevelEvent_A	7109587	6485978	0	0
gen_not_sticky_sva.StableStDropOut_A	7109587	34	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7109587	132
T36	9994	0
T37	0	4
T38	0	2
T40	0	2
T42	3304	2
T43	835	4
T45	0	2
T46	0	6
T50	22701	0
T55	678	0
T63	1072	0
T64	800	0
T74	0	2
T134	427	0
T180	0	2
T206	404	0
T207	420	0
T223	0	4

CntIncr_A

Name	Attempts	Real Successes
Total	7109587	8891
T36	9994	0
T37	0	110
T38	0	18
T40	0	75
T42	3304	33
T43	835	118
T45	0	41
T46	0	159
T50	22701	0
T55	678	0
T63	1072	0
T64	800	0
T74	0	88
T134	427	0
T180	0	91
T206	404	0
T207	420	0
T223	0	64

CntNoWrap_A

Name	Attempts	Real Successes
Total	7109587	6483505
T1	16996	16569
T5	522	121
T6	409	8
T13	522	121
T14	502	101
T15	589	188
T16	688	287
T17	407	6
T18	419	18
T19	525	124

DetectStDropOut_A

Name	Attempts	Real Successes
Total	7109587	4
T46	885	1
T47	775	0
T223	0	1
T224	0	1
T227	0	1
T228	492	0
T229	513	0
T230	2114	0
T231	2413	0
T232	24427	0
T233	5297	0
T234	504	0
T235	1989	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7109587	21264
T36	9994	0
T37	0	277
T38	0	12
T40	0	73
T42	3304	98
T43	835	104
T45	0	41
T46	0	159
T50	22701	0
T55	678	0
T63	1072	0
T64	800	0
T74	0	43
T134	427	0
T180	0	174
T206	404	0
T207	420	0
T223	0	76

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7109587	60
T36	9994	0
T37	0	2
T38	0	1
T40	0	1
T42	3304	1
T43	835	2
T45	0	1
T46	0	2
T50	22701	0
T55	678	0
T63	1072	0
T64	800	0
T74	0	1
T134	427	0
T180	0	1
T206	404	0
T207	420	0
T223	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7109587	6429733
T1	16996	16569
T5	522	121
T6	409	8
T13	522	121
T14	502	101
T15	589	188
T16	688	287
T17	407	6
T18	419	18
T19	525	124

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7109587	6432024
T1	16996	16575
T5	522	122
T6	409	9
T13	522	122
T14	502	102
T15	589	189
T16	688	288
T17	407	7
T18	419	19
T19	525	125

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7109587	67
T36	9994	0
T37	0	2
T38	0	1
T40	0	1
T42	3304	1
T43	835	2
T45	0	1
T46	0	3
T50	22701	0
T55	678	0
T63	1072	0
T64	800	0
T74	0	1
T134	427	0
T180	0	1
T206	404	0
T207	420	0
T223	0	2

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7109587	65
T36	9994	0
T37	0	2
T38	0	1
T40	0	1
T42	3304	1
T43	835	2
T45	0	1
T46	0	3
T50	22701	0
T55	678	0
T63	1072	0
T64	800	0
T74	0	1
T134	427	0
T180	0	1
T206	404	0
T207	420	0
T223	0	2

EnterStableSt_A

Name	Attempts	Real Successes
Total	7109587	60
T36	9994	0
T37	0	2
T38	0	1
T40	0	1
T42	3304	1
T43	835	2
T45	0	1
T46	0	2
T50	22701	0
T55	678	0
T63	1072	0
T64	800	0
T74	0	1
T134	427	0
T180	0	1
T206	404	0
T207	420	0
T223	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7109587	60
T36	9994	0
T37	0	2
T38	0	1
T40	0	1
T42	3304	1
T43	835	2
T45	0	1
T46	0	2
T50	22701	0
T55	678	0
T63	1072	0
T64	800	0
T74	0	1
T134	427	0
T180	0	1
T206	404	0
T207	420	0
T223	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7109587	21179
T36	9994	0
T37	0	274
T38	0	11
T40	0	72
T42	3304	96
T43	835	102
T45	0	40
T46	0	156
T50	22701	0
T55	678	0
T63	1072	0
T64	800	0
T74	0	41
T134	427	0
T180	0	172
T206	404	0
T207	420	0
T223	0	75

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	7109587	2869
T3	0	21
T5	522	4
T6	409	0
T13	522	6
T14	502	4
T15	589	5
T16	688	0
T17	407	0
T18	419	0
T19	525	5
T24	0	3
T26	0	4
T31	2131	0
T58	0	5
T60	0	2

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	7109587	6485978
T1	16996	16575
T5	522	122
T6	409	9
T13	522	122
T14	502	102
T15	589	189
T16	688	288
T17	407	7
T18	419	19
T19	525	125

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7109587	34
T37	0	1
T40	0	1
T43	835	2
T45	0	1
T46	0	1
T50	22701	0
T55	678	0
T64	800	0
T65	3177	0
T116	0	2
T118	0	1
T149	0	1
T161	447	0
T206	404	0
T207	420	0
T208	506	0
T209	422	0
T223	0	1
T236	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T27,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T7,T27,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T27,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T27,T43
1	0	Covered	T1,T5,T13
1	1	Covered	T7,T27,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T27,T43
0	1	Covered	T205
1	0	Covered	T61

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T27,T43
0	1	Covered	T7,T43,T37
1	0	Covered	T38

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T27,T43
1	-	Covered	T7,T43,T37

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T27,T43
DetectSt	168	Covered	T7,T27,T43
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T7,T27,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T27,T43
DebounceSt->IdleSt	163	Covered	T41,T205,T127
DetectSt->IdleSt	186	Covered	T205,T61
DetectSt->StableSt	191	Covered	T7,T27,T43
IdleSt->DebounceSt	148	Covered	T7,T27,T43
StableSt->IdleSt	206	Covered	T7,T27,T43

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T27,T43
0	1	Covered	T7,T27,T43
0	0	Excluded	T1,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T27,T43
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T27,T43
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T13
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T27,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T41,T205,T127
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T27,T43
DetectSt	-	-	-	-	1	-	-	Covered	T205,T61
DetectSt	-	-	-	-	0	1	-	Covered	T7,T27,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T43,T37
StableSt	-	-	-	-	-	-	0	Covered	T7,T27,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7109587	123	0	0
CntIncr_A	7109587	11019	0	0
CntNoWrap_A	7109587	6483514	0	0
DetectStDropOut_A	7109587	1	0	0
DetectedOut_A	7109587	8085	0	0
DetectedPulseOut_A	7109587	58	0	0
DisabledIdleSt_A	7109587	6438427	0	0
DisabledNoDetection_A	7109587	6440718	0	0
EnterDebounceSt_A	7109587	63	0	0
EnterDetectSt_A	7109587	60	0	0
EnterStableSt_A	7109587	58	0	0
PulseIsPulse_A	7109587	58	0	0
StayInStableSt	7109587	8002	0	0
gen_high_level_sva.HighLevelEvent_A	7109587	6485978	0	0
gen_not_sticky_sva.StableStDropOut_A	7109587	32	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7109587	123
T7	29986	4
T8	3734	0
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T27	0	2
T37	0	4
T38	0	2
T41	0	1
T43	0	4
T44	0	2
T45	0	2
T51	5284	0
T52	4068	0
T74	0	2
T75	523	0
T76	502	0
T140	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	7109587	11019
T7	29986	7192
T8	3734	0
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T27	0	66
T37	0	110
T38	0	18
T41	0	36
T43	0	118
T44	0	41
T45	0	41
T51	5284	0
T52	4068	0
T74	0	88
T75	523	0
T76	502	0
T140	0	81

CntNoWrap_A

Name	Attempts	Real Successes
Total	7109587	6483514
T1	16996	16569
T5	522	121
T6	409	8
T13	522	121
T14	502	101
T15	589	188
T16	688	287
T17	407	6
T18	419	18
T19	525	124

DetectStDropOut_A

Name	Attempts	Real Successes
Total	7109587	1
T205	19452	1
T210	428	0
T211	408	0
T212	435	0
T213	31427	0
T214	421	0
T215	426	0
T216	17880	0
T217	610	0
T218	17044	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7109587	8085
T7	29986	3237
T8	3734	0
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T27	0	40
T37	0	67
T38	0	12
T43	0	89
T44	0	122
T45	0	203
T51	5284	0
T52	4068	0
T74	0	73
T75	523	0
T76	502	0
T140	0	125
T235	0	41

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7109587	58
T7	29986	2
T8	3734	0
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T27	0	1
T37	0	2
T38	0	1
T43	0	2
T44	0	1
T45	0	1
T51	5284	0
T52	4068	0
T74	0	1
T75	523	0
T76	502	0
T140	0	1
T235	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7109587	6438427
T1	16996	16569
T5	522	121
T6	409	8
T13	522	121
T14	502	101
T15	589	188
T16	688	287
T17	407	6
T18	419	18
T19	525	124

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7109587	6440718
T1	16996	16575
T5	522	122
T6	409	9
T13	522	122
T14	502	102
T15	589	189
T16	688	288
T17	407	7
T18	419	19
T19	525	125

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7109587	63
T7	29986	2
T8	3734	0
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T27	0	1
T37	0	2
T38	0	1
T41	0	1
T43	0	2
T44	0	1
T45	0	1
T51	5284	0
T52	4068	0
T74	0	1
T75	523	0
T76	502	0
T140	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7109587	60
T7	29986	2
T8	3734	0
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T27	0	1
T37	0	2
T38	0	1
T43	0	2
T44	0	1
T45	0	1
T51	5284	0
T52	4068	0
T74	0	1
T75	523	0
T76	502	0
T140	0	1
T235	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	7109587	58
T7	29986	2
T8	3734	0
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T27	0	1
T37	0	2
T38	0	1
T43	0	2
T44	0	1
T45	0	1
T51	5284	0
T52	4068	0
T74	0	1
T75	523	0
T76	502	0
T140	0	1
T235	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7109587	58
T7	29986	2
T8	3734	0
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T27	0	1
T37	0	2
T38	0	1
T43	0	2
T44	0	1
T45	0	1
T51	5284	0
T52	4068	0
T74	0	1
T75	523	0
T76	502	0
T140	0	1
T235	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7109587	8002
T7	29986	3234
T8	3734	0
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T27	0	38
T37	0	65
T38	0	11
T43	0	86
T44	0	120
T45	0	201
T51	5284	0
T52	4068	0
T74	0	72
T75	523	0
T76	502	0
T140	0	123
T235	0	39

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	7109587	6485978
T1	16996	16575
T5	522	122
T6	409	9
T13	522	122
T14	502	102
T15	589	189
T16	688	288
T17	407	7
T18	419	19
T19	525	125

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7109587	32
T7	29986	1
T8	3734	0
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T37	0	2
T43	0	1
T51	5284	0
T52	4068	0
T74	0	1
T75	523	0
T76	502	0
T181	0	1
T182	0	1
T192	0	1
T193	0	2
T205	0	1
T237	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T13
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T13
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T8,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T7,T8,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T8,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T27
1	0	Covered	T1,T5,T13
1	1	Covered	T7,T8,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T38
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T38
0	1	Covered	T7,T8,T149
1	0	Covered	T38,T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T8,T38
1	-	Covered	T7,T8,T149

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T8,T38
DetectSt	168	Covered	T7,T8,T38
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T7,T8,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T8,T38
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T7,T8,T38
IdleSt->DebounceSt	148	Covered	T7,T8,T38
StableSt->IdleSt	206	Covered	T7,T8,T38

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T8,T38
0	1	Covered	T7,T8,T38
0	0	Excluded	T1,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T38
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T8,T38
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T8,T38
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T8,T38
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T7,T8,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T8,T38
StableSt	-	-	-	-	-	-	0	Covered	T7,T8,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7109587	78	0	0
CntIncr_A	7109587	10687	0	0
CntNoWrap_A	7109587	6483559	0	0
DetectStDropOut_A	7109587	0	0	0
DetectedOut_A	7109587	26993	0	0
DetectedPulseOut_A	7109587	39	0	0
DisabledIdleSt_A	7109587	6402889	0	0
DisabledNoDetection_A	7109587	6405177	0	0
EnterDebounceSt_A	7109587	39	0	0
EnterDetectSt_A	7109587	39	0	0
EnterStableSt_A	7109587	39	0	0
PulseIsPulse_A	7109587	39	0	0
StayInStableSt	7109587	26932	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7109587	6408	0	0
gen_low_level_sva.LowLevelEvent_A	7109587	6485978	0	0
gen_not_sticky_sva.StableStDropOut_A	7109587	15	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7109587	78
T7	29986	2
T8	3734	2
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T38	0	2
T39	0	2
T41	0	2
T51	5284	0
T52	4068	0
T75	523	0
T76	502	0
T149	0	4
T182	0	2
T192	0	2
T237	0	2
T238	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	7109587	10687
T7	29986	3596
T8	3734	58
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T38	0	18
T39	0	78
T41	0	36
T51	5284	0
T52	4068	0
T75	523	0
T76	502	0
T149	0	54
T182	0	43
T192	0	86
T237	0	85
T238	0	83

CntNoWrap_A

Name	Attempts	Real Successes
Total	7109587	6483559
T1	16996	16569
T5	522	121
T6	409	8
T13	522	121
T14	502	101
T15	589	188
T16	688	287
T17	407	6
T18	419	18
T19	525	124

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7109587	26993
T7	29986	13424
T8	3734	130
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T38	0	11
T39	0	41
T41	0	290
T51	5284	0
T52	4068	0
T75	523	0
T76	502	0
T149	0	127
T182	0	358
T192	0	30
T237	0	38
T238	0	127

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7109587	39
T7	29986	1
T8	3734	1
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T38	0	1
T39	0	1
T41	0	1
T51	5284	0
T52	4068	0
T75	523	0
T76	502	0
T149	0	2
T182	0	1
T192	0	1
T237	0	1
T238	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7109587	6402889
T1	16996	16569
T5	522	121
T6	409	8
T13	522	121
T14	502	101
T15	589	188
T16	688	287
T17	407	6
T18	419	18
T19	525	124

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7109587	6405177
T1	16996	16575
T5	522	122
T6	409	9
T13	522	122
T14	502	102
T15	589	189
T16	688	288
T17	407	7
T18	419	19
T19	525	125

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7109587	39
T7	29986	1
T8	3734	1
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T38	0	1
T39	0	1
T41	0	1
T51	5284	0
T52	4068	0
T75	523	0
T76	502	0
T149	0	2
T182	0	1
T192	0	1
T237	0	1
T238	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7109587	39
T7	29986	1
T8	3734	1
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T38	0	1
T39	0	1
T41	0	1
T51	5284	0
T52	4068	0
T75	523	0
T76	502	0
T149	0	2
T182	0	1
T192	0	1
T237	0	1
T238	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	7109587	39
T7	29986	1
T8	3734	1
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T38	0	1
T39	0	1
T41	0	1
T51	5284	0
T52	4068	0
T75	523	0
T76	502	0
T149	0	2
T182	0	1
T192	0	1
T237	0	1
T238	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7109587	39
T7	29986	1
T8	3734	1
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T38	0	1
T39	0	1
T41	0	1
T51	5284	0
T52	4068	0
T75	523	0
T76	502	0
T149	0	2
T182	0	1
T192	0	1
T237	0	1
T238	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7109587	26932
T7	29986	13423
T8	3734	129
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T38	0	10
T39	0	39
T41	0	288
T51	5284	0
T52	4068	0
T75	523	0
T76	502	0
T149	0	124
T182	0	356
T192	0	29
T237	0	36
T238	0	126

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	7109587	6408
T1	16996	12
T2	0	30
T5	522	4
T6	409	0
T13	522	8
T14	502	5
T15	589	0
T16	688	0
T17	407	0
T18	419	0
T19	525	7
T24	0	7
T26	0	3
T31	0	9
T58	0	3

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	7109587	6485978
T1	16996	16575
T5	522	122
T6	409	9
T13	522	122
T14	502	102
T15	589	189
T16	688	288
T17	407	7
T18	419	19
T19	525	125

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7109587	15
T7	29986	1
T8	3734	1
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T51	5284	0
T52	4068	0
T75	523	0
T76	502	0
T118	0	1
T127	0	1
T149	0	1
T192	0	1
T203	0	1
T238	0	1
T239	0	1
T240	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T27,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T7,T27,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T27,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T27,T42
1	0	Covered	T1,T5,T6
1	1	Covered	T7,T27,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T42,T37
0	1	Covered	T27,T127
1	0	Covered	T61

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T42,T37
0	1	Covered	T7,T37,T47
1	0	Covered	T38

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T42,T37
1	-	Covered	T7,T37,T47

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T27,T42
DetectSt	168	Covered	T7,T27,T42
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T7,T42,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T27,T42
DebounceSt->IdleSt	163	Covered	T241,T127,T242
DetectSt->IdleSt	186	Covered	T27,T127,T61
DetectSt->StableSt	191	Covered	T7,T42,T37
IdleSt->DebounceSt	148	Covered	T7,T27,T42
StableSt->IdleSt	206	Covered	T7,T42,T37

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T27,T42
0	1	Covered	T7,T27,T42
0	0	Excluded	T1,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T27,T42
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T27,T42
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T27,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T241,T127,T242
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T27,T42
DetectSt	-	-	-	-	1	-	-	Covered	T27,T127,T61
DetectSt	-	-	-	-	0	1	-	Covered	T7,T42,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T37,T38
StableSt	-	-	-	-	-	-	0	Covered	T7,T42,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7109587	113	0	0
CntIncr_A	7109587	15686	0	0
CntNoWrap_A	7109587	6483524	0	0
DetectStDropOut_A	7109587	2	0	0
DetectedOut_A	7109587	26753	0	0
DetectedPulseOut_A	7109587	52	0	0
DisabledIdleSt_A	7109587	6402725	0	0
DisabledNoDetection_A	7109587	6405017	0	0
EnterDebounceSt_A	7109587	58	0	0
EnterDetectSt_A	7109587	55	0	0
EnterStableSt_A	7109587	52	0	0
PulseIsPulse_A	7109587	52	0	0
StayInStableSt	7109587	26674	0	0
gen_high_level_sva.HighLevelEvent_A	7109587	6485978	0	0
gen_not_sticky_sva.StableStDropOut_A	7109587	24	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7109587	113
T7	29986	4
T8	3734	0
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T27	0	2
T37	0	4
T38	0	2
T39	0	2
T40	0	2
T42	0	2
T47	0	4
T51	5284	0
T52	4068	0
T75	523	0
T76	502	0
T135	0	2
T180	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	7109587	15686
T7	29986	7192
T8	3734	0
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T27	0	66
T37	0	110
T38	0	18
T39	0	78
T40	0	75
T42	0	33
T47	0	68
T51	5284	0
T52	4068	0
T75	523	0
T76	502	0
T135	0	97
T180	0	91

CntNoWrap_A

Name	Attempts	Real Successes
Total	7109587	6483524
T1	16996	16569
T5	522	121
T6	409	8
T13	522	121
T14	502	101
T15	589	188
T16	688	287
T17	407	6
T18	419	18
T19	525	124

DetectStDropOut_A

Name	Attempts	Real Successes
Total	7109587	2
T27	30910	1
T36	9994	0
T42	3304	0
T43	835	0
T48	9944	0
T49	11736	0
T63	1072	0
T127	0	1
T132	402	0
T133	502	0
T134	427	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7109587	26753
T7	29986	6832
T8	3734	0
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T37	0	181
T38	0	12
T39	0	40
T40	0	39
T42	0	42
T47	0	187
T51	5284	0
T52	4068	0
T75	523	0
T76	502	0
T135	0	41
T149	0	160
T180	0	39

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7109587	52
T7	29986	2
T8	3734	0
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T37	0	2
T38	0	1
T39	0	1
T40	0	1
T42	0	1
T47	0	2
T51	5284	0
T52	4068	0
T75	523	0
T76	502	0
T135	0	1
T149	0	2
T180	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7109587	6402725
T1	16996	16569
T5	522	121
T6	409	8
T13	522	121
T14	502	101
T15	589	188
T16	688	287
T17	407	6
T18	419	18
T19	525	124

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7109587	6405017
T1	16996	16575
T5	522	122
T6	409	9
T13	522	122
T14	502	102
T15	589	189
T16	688	288
T17	407	7
T18	419	19
T19	525	125

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7109587	58
T7	29986	2
T8	3734	0
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T27	0	1
T37	0	2
T38	0	1
T39	0	1
T40	0	1
T42	0	1
T47	0	2
T51	5284	0
T52	4068	0
T75	523	0
T76	502	0
T135	0	1
T180	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7109587	55
T7	29986	2
T8	3734	0
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T27	0	1
T37	0	2
T38	0	1
T39	0	1
T40	0	1
T42	0	1
T47	0	2
T51	5284	0
T52	4068	0
T75	523	0
T76	502	0
T135	0	1
T180	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	7109587	52
T7	29986	2
T8	3734	0
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T37	0	2
T38	0	1
T39	0	1
T40	0	1
T42	0	1
T47	0	2
T51	5284	0
T52	4068	0
T75	523	0
T76	502	0
T135	0	1
T149	0	2
T180	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7109587	52
T7	29986	2
T8	3734	0
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T37	0	2
T38	0	1
T39	0	1
T40	0	1
T42	0	1
T47	0	2
T51	5284	0
T52	4068	0
T75	523	0
T76	502	0
T135	0	1
T149	0	2
T180	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7109587	26674
T7	29986	6830
T8	3734	0
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T37	0	178
T38	0	11
T39	0	38
T40	0	37
T42	0	40
T47	0	185
T51	5284	0
T52	4068	0
T75	523	0
T76	502	0
T135	0	39
T149	0	157
T180	0	37

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	7109587	6485978
T1	16996	16575
T5	522	122
T6	409	9
T13	522	122
T14	502	102
T15	589	189
T16	688	288
T17	407	7
T18	419	19
T19	525	125

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7109587	24
T7	29986	2
T8	3734	0
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T37	0	1
T47	0	2
T51	5284	0
T52	4068	0
T75	523	0
T76	502	0
T149	0	1
T182	0	1
T194	0	1
T205	0	2
T238	0	1
T243	0	1
T244	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T27,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T7,T27,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T27,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T27
1	0	Covered	T1,T5,T13
1	1	Covered	T7,T27,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T27,T38
0	1	Covered	T47,T181,T245
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T27,T38
0	1	Covered	T7,T41,T219
1	0	Covered	T38,T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T27,T38
1	-	Covered	T7,T41,T219

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T27,T38
DetectSt	168	Covered	T7,T27,T38
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T7,T27,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T27,T38
DebounceSt->IdleSt	163	Covered	T205,T227
DetectSt->IdleSt	186	Covered	T47,T181,T245
DetectSt->StableSt	191	Covered	T7,T27,T38
IdleSt->DebounceSt	148	Covered	T7,T27,T38
StableSt->IdleSt	206	Covered	T7,T27,T38

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T27,T38
0	1	Covered	T7,T27,T38
0	0	Excluded	T1,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T27,T38
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T27,T38
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T27,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T205,T227
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T27,T38
DetectSt	-	-	-	-	1	-	-	Covered	T47,T181,T245
DetectSt	-	-	-	-	0	1	-	Covered	T7,T27,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T38,T41
StableSt	-	-	-	-	-	-	0	Covered	T7,T27,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7109587	72	0	0
CntIncr_A	7109587	9062	0	0
CntNoWrap_A	7109587	6483565	0	0
DetectStDropOut_A	7109587	3	0	0
DetectedOut_A	7109587	8597	0	0
DetectedPulseOut_A	7109587	32	0	0
DisabledIdleSt_A	7109587	6398955	0	0
DisabledNoDetection_A	7109587	6401231	0	0
EnterDebounceSt_A	7109587	37	0	0
EnterDetectSt_A	7109587	35	0	0
EnterStableSt_A	7109587	32	0	0
PulseIsPulse_A	7109587	32	0	0
StayInStableSt	7109587	8547	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7109587	6090	0	0
gen_low_level_sva.LowLevelEvent_A	7109587	6485978	0	0
gen_not_sticky_sva.StableStDropOut_A	7109587	12	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7109587	72
T7	29986	4
T8	3734	0
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T27	0	2
T38	0	2
T41	0	6
T47	0	4
T51	5284	0
T52	4068	0
T75	523	0
T76	502	0
T181	0	2
T182	0	2
T205	0	3
T235	0	2
T237	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	7109587	9062
T7	29986	7192
T8	3734	0
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T27	0	66
T38	0	18
T41	0	108
T47	0	68
T51	5284	0
T52	4068	0
T75	523	0
T76	502	0
T181	0	91
T182	0	43
T205	0	180
T235	0	90
T237	0	85

CntNoWrap_A

Name	Attempts	Real Successes
Total	7109587	6483565
T1	16996	16569
T5	522	121
T6	409	8
T13	522	121
T14	502	101
T15	589	188
T16	688	287
T17	407	6
T18	419	18
T19	525	124

DetectStDropOut_A

Name	Attempts	Real Successes
Total	7109587	3
T47	775	1
T181	0	1
T228	492	0
T229	513	0
T230	2114	0
T231	2413	0
T232	24427	0
T233	5297	0
T234	504	0
T235	1989	0
T245	0	1
T246	492	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7109587	8597
T7	29986	6231
T8	3734	0
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T27	0	41
T38	0	12
T41	0	128
T47	0	40
T51	5284	0
T52	4068	0
T75	523	0
T76	502	0
T182	0	191
T205	0	202
T219	0	84
T235	0	41
T237	0	306

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7109587	32
T7	29986	2
T8	3734	0
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T27	0	1
T38	0	1
T41	0	3
T47	0	1
T51	5284	0
T52	4068	0
T75	523	0
T76	502	0
T182	0	1
T205	0	1
T219	0	1
T235	0	1
T237	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7109587	6398955
T1	16996	16569
T5	522	121
T6	409	8
T13	522	121
T14	502	101
T15	589	188
T16	688	287
T17	407	6
T18	419	18
T19	525	124

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7109587	6401231
T1	16996	16575
T5	522	122
T6	409	9
T13	522	122
T14	502	102
T15	589	189
T16	688	288
T17	407	7
T18	419	19
T19	525	125

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7109587	37
T7	29986	2
T8	3734	0
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T27	0	1
T38	0	1
T41	0	3
T47	0	2
T51	5284	0
T52	4068	0
T75	523	0
T76	502	0
T181	0	1
T182	0	1
T205	0	2
T235	0	1
T237	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7109587	35
T7	29986	2
T8	3734	0
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T27	0	1
T38	0	1
T41	0	3
T47	0	2
T51	5284	0
T52	4068	0
T75	523	0
T76	502	0
T181	0	1
T182	0	1
T205	0	1
T235	0	1
T237	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	7109587	32
T7	29986	2
T8	3734	0
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T27	0	1
T38	0	1
T41	0	3
T47	0	1
T51	5284	0
T52	4068	0
T75	523	0
T76	502	0
T182	0	1
T205	0	1
T219	0	1
T235	0	1
T237	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7109587	32
T7	29986	2
T8	3734	0
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T27	0	1
T38	0	1
T41	0	3
T47	0	1
T51	5284	0
T52	4068	0
T75	523	0
T76	502	0
T182	0	1
T205	0	1
T219	0	1
T235	0	1
T237	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7109587	8547
T7	29986	6228
T8	3734	0
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T27	0	39
T38	0	11
T41	0	124
T47	0	38
T51	5284	0
T52	4068	0
T75	523	0
T76	502	0
T182	0	189
T205	0	200
T219	0	83
T235	0	39
T237	0	304

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	7109587	6090
T1	16996	11
T2	0	34
T5	522	4
T6	409	0
T13	522	6
T14	502	3
T15	589	0
T16	688	0
T17	407	0
T18	419	0
T19	525	6
T24	0	8
T26	0	5
T30	0	25
T58	0	4

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	7109587	6485978
T1	16996	16575
T5	522	122
T6	409	9
T13	522	122
T14	502	102
T15	589	189
T16	688	288
T17	407	7
T18	419	19
T19	525	125

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7109587	12
T7	29986	1
T8	3734	0
T9	1551	0
T10	706	0
T11	15931	0
T23	859	0
T41	0	2
T51	5284	0
T52	4068	0
T75	523	0
T76	502	0
T127	0	1
T178	0	1
T195	0	1
T219	0	1
T220	0	2
T247	0	1
T248	0	1
T249	0	1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr