Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T42,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T7,T42,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T42,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T42,T37
1	0	Covered	T1,T5,T13
1	1	Covered	T7,T42,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T42,T37
0	1	Covered	T116,T205,T250
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T42,T37
0	1	Covered	T42,T37,T45
1	0	Covered	T38

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T42,T37
1	-	Covered	T42,T37,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T42,T37
DetectSt	168	Covered	T7,T42,T37
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T7,T42,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T42,T37
DebounceSt->IdleSt	163	Covered	T140,T194,T61
DetectSt->IdleSt	186	Covered	T116,T205,T250
DetectSt->StableSt	191	Covered	T7,T42,T37
IdleSt->DebounceSt	148	Covered	T7,T42,T37
StableSt->IdleSt	206	Covered	T7,T42,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T42,T37
0	1	Covered	T7,T42,T37
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T42,T37
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T42,T37
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T61
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T42,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T140,T194,T178
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T42,T37
DetectSt	-	-	-	-	1	-	-	Covered	T116,T205,T250
DetectSt	-	-	-	-	0	1	-	Covered	T7,T42,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T42,T37,T38
StableSt	-	-	-	-	-	-	0	Covered	T7,T42,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7109587	116	0	0
CntIncr_A	7109587	17430	0	0
CntNoWrap_A	7109587	6483521	0	0
DetectStDropOut_A	7109587	3	0	0
DetectedOut_A	7109587	31096	0	0
DetectedPulseOut_A	7109587	53	0	0
DisabledIdleSt_A	7109587	6404013	0	0
DisabledNoDetection_A	7109587	6406309	0	0
EnterDebounceSt_A	7109587	60	0	0
EnterDetectSt_A	7109587	56	0	0
EnterStableSt_A	7109587	53	0	0
PulseIsPulse_A	7109587	53	0	0
StayInStableSt	7109587	31022	0	0
gen_high_level_sva.HighLevelEvent_A	7109587	6485978	0	0
gen_not_sticky_sva.StableStDropOut_A	7109587	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	116	0	0
T7	29986	2	0	0
T8	3734	0	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T37	0	2	0	0
T38	0	2	0	0
T42	0	2	0	0
T45	0	2	0	0
T46	0	2	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T74	0	2	0	0
T75	523	0	0	0
T76	502	0	0	0
T135	0	2	0	0
T140	0	1	0	0
T199	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	17430	0	0
T7	29986	3596	0	0
T8	3734	0	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T37	0	55	0	0
T38	0	18	0	0
T42	0	33	0	0
T45	0	41	0	0
T46	0	53	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T74	0	88	0	0
T75	523	0	0	0
T76	502	0	0	0
T135	0	97	0	0
T140	0	81	0	0
T199	0	30	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6483521	0	0
T1	16996	16569	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	3	0	0
T116	1136	1	0	0
T124	11471	0	0	0
T205	0	1	0	0
T250	0	1	0	0
T251	404108	0	0	0
T252	417	0	0	0
T253	422	0	0	0
T254	496	0	0	0
T255	20402	0	0	0
T256	547	0	0	0
T257	677	0	0	0
T258	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	31096	0	0
T7	29986	17065	0	0
T8	3734	0	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T37	0	77	0	0
T38	0	11	0	0
T42	0	23	0	0
T45	0	39	0	0
T46	0	8	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T74	0	43	0	0
T75	523	0	0	0
T76	502	0	0	0
T135	0	42	0	0
T199	0	70	0	0
T237	0	53	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	53	0	0
T7	29986	1	0	0
T8	3734	0	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T42	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T74	0	1	0	0
T75	523	0	0	0
T76	502	0	0	0
T135	0	1	0	0
T199	0	1	0	0
T237	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6404013	0	0
T1	16996	16569	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6406309	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	60	0	0
T7	29986	1	0	0
T8	3734	0	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T42	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T74	0	1	0	0
T75	523	0	0	0
T76	502	0	0	0
T135	0	1	0	0
T140	0	1	0	0
T199	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	56	0	0
T7	29986	1	0	0
T8	3734	0	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T42	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T74	0	1	0	0
T75	523	0	0	0
T76	502	0	0	0
T135	0	1	0	0
T199	0	1	0	0
T237	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	53	0	0
T7	29986	1	0	0
T8	3734	0	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T42	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T74	0	1	0	0
T75	523	0	0	0
T76	502	0	0	0
T135	0	1	0	0
T199	0	1	0	0
T237	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	53	0	0
T7	29986	1	0	0
T8	3734	0	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T42	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T74	0	1	0	0
T75	523	0	0	0
T76	502	0	0	0
T135	0	1	0	0
T199	0	1	0	0
T237	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	31022	0	0
T7	29986	17063	0	0
T8	3734	0	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T37	0	76	0	0
T38	0	10	0	0
T42	0	22	0	0
T45	0	38	0	0
T46	0	7	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T74	0	41	0	0
T75	523	0	0	0
T76	502	0	0	0
T135	0	40	0	0
T199	0	69	0	0
T237	0	52	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6485978	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	31	0	0
T36	9994	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T42	3304	1	0	0
T43	835	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T50	22701	0	0	0
T55	678	0	0	0
T63	1072	0	0	0
T64	800	0	0	0
T134	427	0	0	0
T181	0	1	0	0
T182	0	1	0	0
T192	0	1	0	0
T199	0	1	0	0
T206	404	0	0	0
T207	420	0	0	0
T237	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T13
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T13
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T37,T38,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T37,T38,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T37,T38,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T27,T37
1	0	Covered	T1,T5,T13
1	1	Covered	T37,T38,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T37,T38,T41
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T37,T38,T41
0	1	Covered	T41,T39,T47
1	0	Covered	T38

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T37,T38,T41
1	-	Covered	T41,T39,T47

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T37,T38,T41
DetectSt	168	Covered	T37,T38,T41
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T37,T38,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T37,T38,T41
DebounceSt->IdleSt	163	Covered	T61
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T37,T38,T41
IdleSt->DebounceSt	148	Covered	T37,T38,T41
StableSt->IdleSt	206	Covered	T37,T38,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T37,T38,T41
0	1	Covered	T37,T38,T41
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T37,T38,T41
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T37,T38,T41
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T61
DebounceSt	-	0	1	1	-	-	-	Covered	T37,T38,T41
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T37,T38,T41
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T37,T38,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T38,T41,T39
StableSt	-	-	-	-	-	-	0	Covered	T37,T38,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7109587	83	0	0
CntIncr_A	7109587	2442	0	0
CntNoWrap_A	7109587	6483554	0	0
DetectStDropOut_A	7109587	0	0	0
DetectedOut_A	7109587	2985	0	0
DetectedPulseOut_A	7109587	41	0	0
DisabledIdleSt_A	7109587	6438082	0	0
DisabledNoDetection_A	7109587	6440367	0	0
EnterDebounceSt_A	7109587	42	0	0
EnterDetectSt_A	7109587	41	0	0
EnterStableSt_A	7109587	41	0	0
PulseIsPulse_A	7109587	41	0	0
StayInStableSt	7109587	2922	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7109587	6151	0	0
gen_low_level_sva.LowLevelEvent_A	7109587	6485978	0	0
gen_not_sticky_sva.StableStDropOut_A	7109587	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	83	0	0
T37	51911	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T41	0	2	0	0
T46	0	2	0	0
T47	0	2	0	0
T56	751	0	0	0
T140	0	2	0	0
T144	17113	0	0	0
T145	36629	0	0	0
T154	0	2	0	0
T162	703	0	0	0
T163	529	0	0	0
T164	412	0	0	0
T165	406	0	0	0
T223	0	2	0	0
T237	0	2	0	0
T259	865	0	0	0
T260	507	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	2442	0	0
T37	51911	55	0	0
T38	0	18	0	0
T39	0	78	0	0
T41	0	36	0	0
T46	0	53	0	0
T47	0	34	0	0
T56	751	0	0	0
T140	0	81	0	0
T144	17113	0	0	0
T145	36629	0	0	0
T154	0	47	0	0
T162	703	0	0	0
T163	529	0	0	0
T164	412	0	0	0
T165	406	0	0	0
T223	0	32	0	0
T237	0	85	0	0
T259	865	0	0	0
T260	507	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6483554	0	0
T1	16996	16569	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	2985	0	0
T37	51911	40	0	0
T38	0	10	0	0
T39	0	43	0	0
T41	0	191	0	0
T46	0	55	0	0
T47	0	136	0	0
T56	751	0	0	0
T140	0	44	0	0
T144	17113	0	0	0
T145	36629	0	0	0
T154	0	87	0	0
T162	703	0	0	0
T163	529	0	0	0
T164	412	0	0	0
T165	406	0	0	0
T223	0	41	0	0
T237	0	38	0	0
T259	865	0	0	0
T260	507	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	41	0	0
T37	51911	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T56	751	0	0	0
T140	0	1	0	0
T144	17113	0	0	0
T145	36629	0	0	0
T154	0	1	0	0
T162	703	0	0	0
T163	529	0	0	0
T164	412	0	0	0
T165	406	0	0	0
T223	0	1	0	0
T237	0	1	0	0
T259	865	0	0	0
T260	507	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6438082	0	0
T1	16996	16569	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6440367	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	42	0	0
T37	51911	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T56	751	0	0	0
T140	0	1	0	0
T144	17113	0	0	0
T145	36629	0	0	0
T154	0	1	0	0
T162	703	0	0	0
T163	529	0	0	0
T164	412	0	0	0
T165	406	0	0	0
T223	0	1	0	0
T237	0	1	0	0
T259	865	0	0	0
T260	507	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	41	0	0
T37	51911	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T56	751	0	0	0
T140	0	1	0	0
T144	17113	0	0	0
T145	36629	0	0	0
T154	0	1	0	0
T162	703	0	0	0
T163	529	0	0	0
T164	412	0	0	0
T165	406	0	0	0
T223	0	1	0	0
T237	0	1	0	0
T259	865	0	0	0
T260	507	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	41	0	0
T37	51911	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T56	751	0	0	0
T140	0	1	0	0
T144	17113	0	0	0
T145	36629	0	0	0
T154	0	1	0	0
T162	703	0	0	0
T163	529	0	0	0
T164	412	0	0	0
T165	406	0	0	0
T223	0	1	0	0
T237	0	1	0	0
T259	865	0	0	0
T260	507	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	41	0	0
T37	51911	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T56	751	0	0	0
T140	0	1	0	0
T144	17113	0	0	0
T145	36629	0	0	0
T154	0	1	0	0
T162	703	0	0	0
T163	529	0	0	0
T164	412	0	0	0
T165	406	0	0	0
T223	0	1	0	0
T237	0	1	0	0
T259	865	0	0	0
T260	507	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	2922	0	0
T37	51911	38	0	0
T38	0	9	0	0
T39	0	42	0	0
T41	0	190	0	0
T46	0	53	0	0
T47	0	135	0	0
T56	751	0	0	0
T140	0	42	0	0
T144	17113	0	0	0
T145	36629	0	0	0
T154	0	86	0	0
T162	703	0	0	0
T163	529	0	0	0
T164	412	0	0	0
T165	406	0	0	0
T223	0	39	0	0
T237	0	36	0	0
T259	865	0	0	0
T260	507	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6151	0	0
T1	16996	12	0	0
T2	0	23	0	0
T5	522	5	0	0
T6	409	0	0	0
T13	522	6	0	0
T14	502	7	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	5	0	0
T24	0	6	0	0
T26	0	5	0	0
T30	0	23	0	0
T58	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6485978	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	18	0	0
T39	0	1	0	0
T41	770	1	0	0
T45	700	0	0	0
T47	0	1	0	0
T71	491	0	0	0
T74	703	0	0	0
T77	5820	0	0	0
T79	2402	0	0	0
T120	682	0	0	0
T127	0	1	0	0
T154	0	1	0	0
T192	0	1	0	0
T194	0	1	0	0
T219	0	1	0	0
T261	0	1	0	0
T262	0	1	0	0
T263	524	0	0	0
T264	14029	0	0	0
T265	503	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T27,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T7,T27,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T27,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T27,T38
1	0	Covered	T1,T5,T6
1	1	Covered	T7,T27,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T38,T44
0	1	Covered	T27,T47
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T38,T44
0	1	Covered	T7,T39,T40
1	0	Covered	T38

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T38,T44
1	-	Covered	T7,T39,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T27,T38
DetectSt	168	Covered	T7,T27,T38
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T7,T38,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T27,T38
DebounceSt->IdleSt	163	Covered	T205,T250,T224
DetectSt->IdleSt	186	Covered	T27,T47
DetectSt->StableSt	191	Covered	T7,T38,T44
IdleSt->DebounceSt	148	Covered	T7,T27,T38
StableSt->IdleSt	206	Covered	T7,T38,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T27,T38
0	1	Covered	T7,T27,T38
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T27,T38
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T27,T38
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T61
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T27,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T205,T250,T224
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T27,T38
DetectSt	-	-	-	-	1	-	-	Covered	T27,T47
DetectSt	-	-	-	-	0	1	-	Covered	T7,T38,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T38,T39
StableSt	-	-	-	-	-	-	0	Covered	T7,T38,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7109587	81	0	0
CntIncr_A	7109587	9159	0	0
CntNoWrap_A	7109587	6483556	0	0
DetectStDropOut_A	7109587	2	0	0
DetectedOut_A	7109587	16737	0	0
DetectedPulseOut_A	7109587	36	0	0
DisabledIdleSt_A	7109587	6445923	0	0
DisabledNoDetection_A	7109587	6448228	0	0
EnterDebounceSt_A	7109587	43	0	0
EnterDetectSt_A	7109587	38	0	0
EnterStableSt_A	7109587	36	0	0
PulseIsPulse_A	7109587	36	0	0
StayInStableSt	7109587	16683	0	0
gen_high_level_sva.HighLevelEvent_A	7109587	6485978	0	0
gen_not_sticky_sva.StableStDropOut_A	7109587	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	81	0	0
T7	29986	4	0	0
T8	3734	0	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T27	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T44	0	2	0	0
T47	0	2	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T116	0	4	0	0
T181	0	2	0	0
T182	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	9159	0	0
T7	29986	7192	0	0
T8	3734	0	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T27	0	66	0	0
T38	0	18	0	0
T39	0	78	0	0
T40	0	75	0	0
T44	0	41	0	0
T47	0	34	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T116	0	192	0	0
T181	0	91	0	0
T182	0	129	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6483556	0	0
T1	16996	16569	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	2	0	0
T27	30910	1	0	0
T36	9994	0	0	0
T42	3304	0	0	0
T43	835	0	0	0
T47	0	1	0	0
T48	9944	0	0	0
T49	11736	0	0	0
T63	1072	0	0	0
T132	402	0	0	0
T133	502	0	0	0
T134	427	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	16737	0	0
T7	29986	14109	0	0
T8	3734	0	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T38	0	10	0	0
T39	0	25	0	0
T40	0	72	0	0
T44	0	42	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T116	0	199	0	0
T181	0	130	0	0
T182	0	198	0	0
T193	0	151	0	0
T205	0	311	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	36	0	0
T7	29986	2	0	0
T8	3734	0	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T44	0	1	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T116	0	2	0	0
T181	0	1	0	0
T182	0	3	0	0
T193	0	1	0	0
T205	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6445923	0	0
T1	16996	16569	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6448228	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	43	0	0
T7	29986	2	0	0
T8	3734	0	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T27	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T44	0	1	0	0
T47	0	1	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T116	0	2	0	0
T181	0	1	0	0
T182	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	38	0	0
T7	29986	2	0	0
T8	3734	0	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T27	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T44	0	1	0	0
T47	0	1	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T116	0	2	0	0
T181	0	1	0	0
T182	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	36	0	0
T7	29986	2	0	0
T8	3734	0	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T44	0	1	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T116	0	2	0	0
T181	0	1	0	0
T182	0	3	0	0
T193	0	1	0	0
T205	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	36	0	0
T7	29986	2	0	0
T8	3734	0	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T44	0	1	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T116	0	2	0	0
T181	0	1	0	0
T182	0	3	0	0
T193	0	1	0	0
T205	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	16683	0	0
T7	29986	14106	0	0
T8	3734	0	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T38	0	9	0	0
T39	0	24	0	0
T40	0	71	0	0
T44	0	40	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T116	0	196	0	0
T181	0	128	0	0
T182	0	194	0	0
T193	0	149	0	0
T205	0	308	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6485978	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	17	0	0
T7	29986	1	0	0
T8	3734	0	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T116	0	1	0	0
T182	0	2	0	0
T196	0	1	0	0
T205	0	1	0	0
T219	0	1	0	0
T221	0	1	0	0
T225	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T37,T38,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T37,T38,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T37,T38,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T42,T37,T38
1	0	Covered	T1,T5,T13
1	1	Covered	T37,T38,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T37,T38,T39
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T37,T38,T39
0	1	Covered	T37,T116,T238
1	0	Covered	T38

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T37,T38,T39
1	-	Covered	T37,T116,T238

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T37,T38,T39
DetectSt	168	Covered	T37,T38,T39
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T37,T38,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T37,T38,T39
DebounceSt->IdleSt	163	Covered	T225,T61
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T37,T38,T39
IdleSt->DebounceSt	148	Covered	T37,T38,T39
StableSt->IdleSt	206	Covered	T37,T38,T116

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T37,T38,T39
0	1	Covered	T37,T38,T39
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T37,T38,T39
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T37,T38,T39
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T61
DebounceSt	-	0	1	1	-	-	-	Covered	T37,T38,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T225
DebounceSt	-	0	0	-	-	-	-	Covered	T37,T38,T39
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T37,T38,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T37,T38,T116
StableSt	-	-	-	-	-	-	0	Covered	T37,T38,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7109587	52	0	0
CntIncr_A	7109587	1277	0	0
CntNoWrap_A	7109587	6483585	0	0
DetectStDropOut_A	7109587	0	0	0
DetectedOut_A	7109587	1714	0	0
DetectedPulseOut_A	7109587	25	0	0
DisabledIdleSt_A	7109587	6471698	0	0
DisabledNoDetection_A	7109587	6474001	0	0
EnterDebounceSt_A	7109587	27	0	0
EnterDetectSt_A	7109587	25	0	0
EnterStableSt_A	7109587	25	0	0
PulseIsPulse_A	7109587	25	0	0
StayInStableSt	7109587	1673	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7109587	6084	0	0
gen_low_level_sva.LowLevelEvent_A	7109587	6485978	0	0
gen_not_sticky_sva.StableStDropOut_A	7109587	8	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	52	0	0
T37	51911	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T56	751	0	0	0
T116	0	2	0	0
T144	17113	0	0	0
T145	36629	0	0	0
T149	0	2	0	0
T162	703	0	0	0
T163	529	0	0	0
T164	412	0	0	0
T165	406	0	0	0
T181	0	2	0	0
T192	0	2	0	0
T219	0	2	0	0
T238	0	2	0	0
T259	865	0	0	0
T260	507	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	1277	0	0
T37	51911	55	0	0
T38	0	18	0	0
T39	0	78	0	0
T40	0	75	0	0
T56	751	0	0	0
T116	0	96	0	0
T144	17113	0	0	0
T145	36629	0	0	0
T149	0	18	0	0
T162	703	0	0	0
T163	529	0	0	0
T164	412	0	0	0
T165	406	0	0	0
T181	0	60	0	0
T192	0	86	0	0
T219	0	23	0	0
T238	0	83	0	0
T259	865	0	0	0
T260	507	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6483585	0	0
T1	16996	16569	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	1714	0	0
T37	51911	41	0	0
T38	0	10	0	0
T39	0	242	0	0
T40	0	38	0	0
T56	751	0	0	0
T116	0	141	0	0
T144	17113	0	0	0
T145	36629	0	0	0
T149	0	65	0	0
T162	703	0	0	0
T163	529	0	0	0
T164	412	0	0	0
T165	406	0	0	0
T181	0	229	0	0
T192	0	39	0	0
T219	0	40	0	0
T238	0	137	0	0
T259	865	0	0	0
T260	507	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	25	0	0
T37	51911	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T56	751	0	0	0
T116	0	1	0	0
T144	17113	0	0	0
T145	36629	0	0	0
T149	0	1	0	0
T162	703	0	0	0
T163	529	0	0	0
T164	412	0	0	0
T165	406	0	0	0
T181	0	1	0	0
T192	0	1	0	0
T219	0	1	0	0
T238	0	1	0	0
T259	865	0	0	0
T260	507	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6471698	0	0
T1	16996	16569	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6474001	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	27	0	0
T37	51911	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T56	751	0	0	0
T116	0	1	0	0
T144	17113	0	0	0
T145	36629	0	0	0
T149	0	1	0	0
T162	703	0	0	0
T163	529	0	0	0
T164	412	0	0	0
T165	406	0	0	0
T181	0	1	0	0
T192	0	1	0	0
T219	0	1	0	0
T238	0	1	0	0
T259	865	0	0	0
T260	507	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	25	0	0
T37	51911	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T56	751	0	0	0
T116	0	1	0	0
T144	17113	0	0	0
T145	36629	0	0	0
T149	0	1	0	0
T162	703	0	0	0
T163	529	0	0	0
T164	412	0	0	0
T165	406	0	0	0
T181	0	1	0	0
T192	0	1	0	0
T219	0	1	0	0
T238	0	1	0	0
T259	865	0	0	0
T260	507	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	25	0	0
T37	51911	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T56	751	0	0	0
T116	0	1	0	0
T144	17113	0	0	0
T145	36629	0	0	0
T149	0	1	0	0
T162	703	0	0	0
T163	529	0	0	0
T164	412	0	0	0
T165	406	0	0	0
T181	0	1	0	0
T192	0	1	0	0
T219	0	1	0	0
T238	0	1	0	0
T259	865	0	0	0
T260	507	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	25	0	0
T37	51911	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T56	751	0	0	0
T116	0	1	0	0
T144	17113	0	0	0
T145	36629	0	0	0
T149	0	1	0	0
T162	703	0	0	0
T163	529	0	0	0
T164	412	0	0	0
T165	406	0	0	0
T181	0	1	0	0
T192	0	1	0	0
T219	0	1	0	0
T238	0	1	0	0
T259	865	0	0	0
T260	507	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	1673	0	0
T37	51911	40	0	0
T38	0	9	0	0
T39	0	240	0	0
T40	0	36	0	0
T56	751	0	0	0
T116	0	140	0	0
T144	17113	0	0	0
T145	36629	0	0	0
T149	0	63	0	0
T162	703	0	0	0
T163	529	0	0	0
T164	412	0	0	0
T165	406	0	0	0
T181	0	227	0	0
T192	0	37	0	0
T219	0	38	0	0
T238	0	136	0	0
T259	865	0	0	0
T260	507	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6084	0	0
T1	16996	14	0	0
T2	0	26	0	0
T5	522	6	0	0
T6	409	0	0	0
T13	522	6	0	0
T14	502	5	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	4	0	0
T24	0	7	0	0
T26	0	4	0	0
T30	0	24	0	0
T58	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6485978	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	8	0	0
T37	51911	1	0	0
T56	751	0	0	0
T116	0	1	0	0
T144	17113	0	0	0
T145	36629	0	0	0
T162	703	0	0	0
T163	529	0	0	0
T164	412	0	0	0
T165	406	0	0	0
T196	0	1	0	0
T204	0	1	0	0
T226	0	1	0	0
T238	0	1	0	0
T242	0	1	0	0
T249	0	1	0	0
T259	865	0	0	0
T260	507	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T13
1	1	Covered	T1,T5,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T8,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T7,T8,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T42,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T27
1	0	Covered	T1,T5,T13
1	1	Covered	T7,T8,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T42,T38
0	1	Covered	T47
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T42,T38
0	1	Covered	T7,T42,T39
1	0	Covered	T38,T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T42,T38
1	-	Covered	T7,T42,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T8,T42
DetectSt	168	Covered	T7,T42,T38
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T7,T42,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T42,T38
DebounceSt->IdleSt	163	Covered	T8,T39,T241
DetectSt->IdleSt	186	Covered	T47
DetectSt->StableSt	191	Covered	T7,T42,T38
IdleSt->DebounceSt	148	Covered	T7,T8,T42
StableSt->IdleSt	206	Covered	T7,T42,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T8,T42
0	1	Covered	T7,T8,T42
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T42,T38
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T8,T42
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T13
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T42,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T39,T241
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T8,T42
DetectSt	-	-	-	-	1	-	-	Covered	T47
DetectSt	-	-	-	-	0	1	-	Covered	T7,T42,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T42,T38
StableSt	-	-	-	-	-	-	0	Covered	T7,T42,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7109587	124	0	0
CntIncr_A	7109587	21034	0	0
CntNoWrap_A	7109587	6483513	0	0
DetectStDropOut_A	7109587	1	0	0
DetectedOut_A	7109587	7526	0	0
DetectedPulseOut_A	7109587	56	0	0
DisabledIdleSt_A	7109587	6403772	0	0
DisabledNoDetection_A	7109587	6406064	0	0
EnterDebounceSt_A	7109587	67	0	0
EnterDetectSt_A	7109587	57	0	0
EnterStableSt_A	7109587	56	0	0
PulseIsPulse_A	7109587	56	0	0
StayInStableSt	7109587	7449	0	0
gen_high_level_sva.HighLevelEvent_A	7109587	6485978	0	0
gen_not_sticky_sva.StableStDropOut_A	7109587	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	124	0	0
T7	29986	4	0	0
T8	3734	1	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T38	0	2	0	0
T39	0	3	0	0
T42	0	2	0	0
T47	0	6	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T135	0	2	0	0
T149	0	6	0	0
T223	0	4	0	0
T266	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	21034	0	0
T7	29986	7192	0	0
T8	3734	58	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T38	0	18	0	0
T39	0	156	0	0
T42	0	33	0	0
T47	0	102	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T135	0	97	0	0
T149	0	72	0	0
T223	0	64	0	0
T266	0	19	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6483513	0	0
T1	16996	16569	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	1	0	0
T47	775	1	0	0
T228	492	0	0	0
T229	513	0	0	0
T230	2114	0	0	0
T231	2413	0	0	0
T232	24427	0	0	0
T233	5297	0	0	0
T234	504	0	0	0
T235	1989	0	0	0
T246	492	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	7526	0	0
T7	29986	3679	0	0
T8	3734	0	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T38	0	11	0	0
T39	0	25	0	0
T42	0	22	0	0
T47	0	47	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T135	0	218	0	0
T149	0	263	0	0
T181	0	78	0	0
T223	0	207	0	0
T266	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	56	0	0
T7	29986	2	0	0
T8	3734	0	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T47	0	2	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T135	0	1	0	0
T149	0	3	0	0
T181	0	1	0	0
T223	0	2	0	0
T266	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6403772	0	0
T1	16996	16569	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6406064	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	67	0	0
T7	29986	2	0	0
T8	3734	1	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T42	0	1	0	0
T47	0	3	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T135	0	1	0	0
T149	0	3	0	0
T223	0	2	0	0
T266	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	57	0	0
T7	29986	2	0	0
T8	3734	0	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T47	0	3	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T135	0	1	0	0
T149	0	3	0	0
T181	0	1	0	0
T223	0	2	0	0
T266	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	56	0	0
T7	29986	2	0	0
T8	3734	0	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T47	0	2	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T135	0	1	0	0
T149	0	3	0	0
T181	0	1	0	0
T223	0	2	0	0
T266	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	56	0	0
T7	29986	2	0	0
T8	3734	0	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T47	0	2	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T135	0	1	0	0
T149	0	3	0	0
T181	0	1	0	0
T223	0	2	0	0
T266	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	7449	0	0
T7	29986	3677	0	0
T8	3734	0	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T38	0	10	0	0
T39	0	24	0	0
T42	0	21	0	0
T47	0	44	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T135	0	216	0	0
T149	0	259	0	0
T181	0	77	0	0
T223	0	204	0	0
T266	0	36	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6485978	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	33	0	0
T7	29986	2	0	0
T8	3734	0	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T23	859	0	0	0
T39	0	1	0	0
T42	0	1	0	0
T47	0	1	0	0
T51	5284	0	0	0
T52	4068	0	0	0
T75	523	0	0	0
T76	502	0	0	0
T118	0	1	0	0
T149	0	2	0	0
T181	0	1	0	0
T205	0	3	0	0
T219	0	1	0	0
T223	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T13
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T13
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T37,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T8,T37,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T37,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T37,T38
1	0	Covered	T1,T5,T13
1	1	Covered	T8,T37,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T37,T38
0	1	Covered	T247
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T37,T38
0	1	Covered	T37,T39,T47
1	0	Covered	T38

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T37,T38
1	-	Covered	T37,T39,T47

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T37,T38
DetectSt	168	Covered	T8,T37,T38
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T8,T37,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T37,T38
DebounceSt->IdleSt	163	Covered	T37,T225,T61
DetectSt->IdleSt	186	Covered	T247
DetectSt->StableSt	191	Covered	T8,T37,T38
IdleSt->DebounceSt	148	Covered	T8,T37,T38
StableSt->IdleSt	206	Covered	T8,T37,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T37,T38
0	1	Covered	T8,T37,T38
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T37,T38
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T37,T38
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T61
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T37,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T37,T225,T159
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T37,T38
DetectSt	-	-	-	-	1	-	-	Covered	T247
DetectSt	-	-	-	-	0	1	-	Covered	T8,T37,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T37,T38,T39
StableSt	-	-	-	-	-	-	0	Covered	T8,T37,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7109587	70	0	0
CntIncr_A	7109587	2013	0	0
CntNoWrap_A	7109587	6483567	0	0
DetectStDropOut_A	7109587	1	0	0
DetectedOut_A	7109587	2738	0	0
DetectedPulseOut_A	7109587	32	0	0
DisabledIdleSt_A	7109587	6467616	0	0
DisabledNoDetection_A	7109587	6469909	0	0
EnterDebounceSt_A	7109587	37	0	0
EnterDetectSt_A	7109587	33	0	0
EnterStableSt_A	7109587	32	0	0
PulseIsPulse_A	7109587	32	0	0
StayInStableSt	7109587	2689	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7109587	6707	0	0
gen_low_level_sva.LowLevelEvent_A	7109587	6485978	0	0
gen_not_sticky_sva.StableStDropOut_A	7109587	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	70	0	0
T8	3734	2	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T12	70930	0	0	0
T37	0	3	0	0
T38	0	2	0	0
T39	0	4	0	0
T47	0	4	0	0
T52	4068	0	0	0
T53	6617	0	0	0
T76	502	0	0	0
T82	502	0	0	0
T116	0	2	0	0
T118	0	2	0	0
T149	0	2	0	0
T151	426	0	0	0
T181	0	2	0	0
T193	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	2013	0	0
T8	3734	58	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T12	70930	0	0	0
T37	0	110	0	0
T38	0	18	0	0
T39	0	156	0	0
T47	0	68	0	0
T52	4068	0	0	0
T53	6617	0	0	0
T76	502	0	0	0
T82	502	0	0	0
T116	0	96	0	0
T118	0	31	0	0
T149	0	27	0	0
T151	426	0	0	0
T181	0	91	0	0
T193	0	33	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6483567	0	0
T1	16996	16569	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	1	0	0
T158	546	0	0	0
T247	1119	1	0	0
T267	4820	0	0	0
T268	28756	0	0	0
T269	11707	0	0	0
T270	14065	0	0	0
T271	403	0	0	0
T272	790	0	0	0
T273	6574	0	0	0
T274	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	2738	0	0
T8	3734	388	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T12	70930	0	0	0
T37	0	44	0	0
T38	0	10	0	0
T39	0	84	0	0
T47	0	144	0	0
T52	4068	0	0	0
T53	6617	0	0	0
T76	502	0	0	0
T82	502	0	0	0
T116	0	237	0	0
T118	0	10	0	0
T149	0	43	0	0
T151	426	0	0	0
T181	0	265	0	0
T193	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	32	0	0
T8	3734	1	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T12	70930	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T47	0	2	0	0
T52	4068	0	0	0
T53	6617	0	0	0
T76	502	0	0	0
T82	502	0	0	0
T116	0	1	0	0
T118	0	1	0	0
T149	0	1	0	0
T151	426	0	0	0
T181	0	1	0	0
T193	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6467616	0	0
T1	16996	16569	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6469909	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	37	0	0
T8	3734	1	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T12	70930	0	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	2	0	0
T47	0	2	0	0
T52	4068	0	0	0
T53	6617	0	0	0
T76	502	0	0	0
T82	502	0	0	0
T116	0	1	0	0
T118	0	1	0	0
T149	0	1	0	0
T151	426	0	0	0
T181	0	1	0	0
T193	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	33	0	0
T8	3734	1	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T12	70930	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T47	0	2	0	0
T52	4068	0	0	0
T53	6617	0	0	0
T76	502	0	0	0
T82	502	0	0	0
T116	0	1	0	0
T118	0	1	0	0
T149	0	1	0	0
T151	426	0	0	0
T181	0	1	0	0
T193	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	32	0	0
T8	3734	1	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T12	70930	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T47	0	2	0	0
T52	4068	0	0	0
T53	6617	0	0	0
T76	502	0	0	0
T82	502	0	0	0
T116	0	1	0	0
T118	0	1	0	0
T149	0	1	0	0
T151	426	0	0	0
T181	0	1	0	0
T193	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	32	0	0
T8	3734	1	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T12	70930	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T47	0	2	0	0
T52	4068	0	0	0
T53	6617	0	0	0
T76	502	0	0	0
T82	502	0	0	0
T116	0	1	0	0
T118	0	1	0	0
T149	0	1	0	0
T151	426	0	0	0
T181	0	1	0	0
T193	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	2689	0	0
T8	3734	386	0	0
T9	1551	0	0	0
T10	706	0	0	0
T11	15931	0	0	0
T12	70930	0	0	0
T37	0	43	0	0
T38	0	9	0	0
T39	0	81	0	0
T47	0	142	0	0
T52	4068	0	0	0
T53	6617	0	0	0
T76	502	0	0	0
T82	502	0	0	0
T116	0	236	0	0
T118	0	9	0	0
T149	0	42	0	0
T151	426	0	0	0
T181	0	263	0	0
T193	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6707	0	0
T1	16996	9	0	0
T5	522	4	0	0
T6	409	0	0	0
T13	522	4	0	0
T14	502	3	0	0
T15	589	0	0	0
T16	688	3	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	6	0	0
T24	0	6	0	0
T26	0	5	0	0
T31	0	9	0	0
T58	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6485978	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	14	0	0
T37	51911	1	0	0
T39	0	1	0	0
T47	0	2	0	0
T56	751	0	0	0
T116	0	1	0	0
T118	0	1	0	0
T127	0	1	0	0
T144	17113	0	0	0
T145	36629	0	0	0
T149	0	1	0	0
T162	703	0	0	0
T163	529	0	0	0
T164	412	0	0	0
T165	406	0	0	0
T205	0	1	0	0
T221	0	1	0	0
T244	0	1	0	0
T259	865	0	0	0
T260	507	0	0	0