Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T30,T4
1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T2,T30,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T2,T30,T4

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T2,T30,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T30,T4
1	0	Covered	T2,T4,T48
1	1	Covered	T2,T30,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T30,T4
0	1	Covered	T30,T51,T52
1	0	Covered	T38,T34,T275

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T48
0	1	Covered	T2,T4,T48
1	0	Covered	T38,T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T4,T48
1	-	Covered	T2,T4,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T30,T4
DetectSt	168	Covered	T2,T30,T4
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T2,T4,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T30,T4
DebounceSt->IdleSt	163	Covered	T52,T38,T276
DetectSt->IdleSt	186	Covered	T30,T51,T52
DetectSt->StableSt	191	Covered	T2,T4,T48
IdleSt->DebounceSt	148	Covered	T2,T30,T4
StableSt->IdleSt	206	Covered	T2,T4,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T30,T4
0	1	Covered	T2,T30,T4
0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T30,T4
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T30,T4
IdleSt	0	-	-	-	-	-	-	Covered	T2,T30,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T38,T61
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T30,T4
DebounceSt	-	0	1	0	-	-	-	Covered	T52,T38,T276
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T30,T4
DetectSt	-	-	-	-	1	-	-	Covered	T30,T51,T52
DetectSt	-	-	-	-	0	1	-	Covered	T2,T4,T48
DetectSt	-	-	-	-	0	0	-	Covered	T2,T30,T4
StableSt	-	-	-	-	-	-	1	Covered	T2,T4,T48
StableSt	-	-	-	-	-	-	0	Covered	T2,T4,T48
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7109587	3226	0	0
CntIncr_A	7109587	101356	0	0
CntNoWrap_A	7109587	6480411	0	0
DetectStDropOut_A	7109587	488	0	0
DetectedOut_A	7109587	69935	0	0
DetectedPulseOut_A	7109587	939	0	0
DisabledIdleSt_A	7109587	6055219	0	0
DisabledNoDetection_A	7109587	6057333	0	0
EnterDebounceSt_A	7109587	1632	0	0
EnterDetectSt_A	7109587	1594	0	0
EnterStableSt_A	7109587	939	0	0
PulseIsPulse_A	7109587	939	0	0
StayInStableSt	7109587	68862	0	0
gen_high_event_sva.HighLevelEvent_A	7109587	6485978	0	0
gen_high_level_sva.HighLevelEvent_A	7109587	6485978	0	0
gen_not_sticky_sva.StableStDropOut_A	7109587	802	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	3226	0	0
T2	12694	30	0	0
T3	2766	0	0	0
T4	9089	26	0	0
T29	748	0	0	0
T30	5416	24	0	0
T38	0	16	0	0
T48	0	50	0	0
T49	0	34	0	0
T50	0	28	0	0
T51	0	52	0	0
T52	0	14	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T77	0	48	0	0
T78	423	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	101356	0	0
T2	12694	510	0	0
T3	2766	0	0	0
T4	9089	676	0	0
T29	748	0	0	0
T30	5416	664	0	0
T38	0	520	0	0
T48	0	1150	0	0
T49	0	1088	0	0
T50	0	1036	0	0
T51	0	1376	0	0
T52	0	270	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T77	0	1536	0	0
T78	423	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6480411	0	0
T1	16996	16569	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	488	0	0
T3	2766	0	0	0
T4	9089	0	0	0
T25	499	0	0	0
T29	748	0	0	0
T30	5416	12	0	0
T34	0	5	0	0
T38	0	1	0	0
T51	0	26	0	0
T52	0	5	0	0
T60	427	0	0	0
T62	976	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T77	0	24	0	0
T78	423	0	0	0
T121	0	26	0	0
T123	0	24	0	0
T141	0	26	0	0
T277	0	20	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	69935	0	0
T2	12694	1098	0	0
T3	2766	0	0	0
T4	9089	136	0	0
T29	748	0	0	0
T30	5416	0	0	0
T38	0	408	0	0
T48	0	1020	0	0
T49	0	353	0	0
T50	0	879	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T78	423	0	0	0
T112	0	1724	0	0
T264	0	1350	0	0
T278	0	316	0	0
T279	0	3103	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	939	0	0
T2	12694	15	0	0
T3	2766	0	0	0
T4	9089	13	0	0
T29	748	0	0	0
T30	5416	0	0	0
T38	0	5	0	0
T48	0	25	0	0
T49	0	17	0	0
T50	0	14	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T78	423	0	0	0
T112	0	24	0	0
T264	0	29	0	0
T278	0	13	0	0
T279	0	32	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6055219	0	0
T1	16996	16569	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6057333	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	1632	0	0
T2	12694	15	0	0
T3	2766	0	0	0
T4	9089	13	0	0
T29	748	0	0	0
T30	5416	12	0	0
T38	0	9	0	0
T48	0	25	0	0
T49	0	17	0	0
T50	0	14	0	0
T51	0	26	0	0
T52	0	9	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T77	0	24	0	0
T78	423	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	1594	0	0
T2	12694	15	0	0
T3	2766	0	0	0
T4	9089	13	0	0
T29	748	0	0	0
T30	5416	12	0	0
T38	0	7	0	0
T48	0	25	0	0
T49	0	17	0	0
T50	0	14	0	0
T51	0	26	0	0
T52	0	5	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T77	0	24	0	0
T78	423	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	939	0	0
T2	12694	15	0	0
T3	2766	0	0	0
T4	9089	13	0	0
T29	748	0	0	0
T30	5416	0	0	0
T38	0	5	0	0
T48	0	25	0	0
T49	0	17	0	0
T50	0	14	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T78	423	0	0	0
T112	0	24	0	0
T264	0	29	0	0
T278	0	13	0	0
T279	0	32	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	939	0	0
T2	12694	15	0	0
T3	2766	0	0	0
T4	9089	13	0	0
T29	748	0	0	0
T30	5416	0	0	0
T38	0	5	0	0
T48	0	25	0	0
T49	0	17	0	0
T50	0	14	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T78	423	0	0	0
T112	0	24	0	0
T264	0	29	0	0
T278	0	13	0	0
T279	0	32	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	68862	0	0
T2	12694	1080	0	0
T3	2766	0	0	0
T4	9089	123	0	0
T29	748	0	0	0
T30	5416	0	0	0
T38	0	403	0	0
T48	0	994	0	0
T49	0	334	0	0
T50	0	862	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T78	423	0	0	0
T112	0	1698	0	0
T264	0	1320	0	0
T278	0	303	0	0
T279	0	3068	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6485978	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6485978	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	802	0	0
T2	12694	12	0	0
T3	2766	0	0	0
T4	9089	13	0	0
T29	748	0	0	0
T30	5416	0	0	0
T38	0	4	0	0
T48	0	24	0	0
T49	0	15	0	0
T50	0	11	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T78	423	0	0	0
T112	0	22	0	0
T264	0	28	0	0
T278	0	13	0	0
T279	0	29	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T30
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T30
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T30
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T35,T27,T38
1	0	Covered	T38,T61

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T38,T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T3
DetectSt	168	Covered	T1,T2,T3
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T3
DebounceSt->IdleSt	163	Covered	T11,T27,T48
DetectSt->IdleSt	186	Covered	T35,T27,T38
DetectSt->StableSt	191	Covered	T1,T2,T3
IdleSt->DebounceSt	148	Covered	T1,T2,T3
StableSt->IdleSt	206	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T38,T61
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T27,T48
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T35,T27,T38
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7109587	985	0	0
CntIncr_A	7109587	48198	0	0
CntNoWrap_A	7109587	6482652	0	0
DetectStDropOut_A	7109587	69	0	0
DetectedOut_A	7109587	16253	0	0
DetectedPulseOut_A	7109587	382	0	0
DisabledIdleSt_A	7109587	6127134	0	0
DisabledNoDetection_A	7109587	6128698	0	0
EnterDebounceSt_A	7109587	534	0	0
EnterDetectSt_A	7109587	454	0	0
EnterStableSt_A	7109587	382	0	0
PulseIsPulse_A	7109587	382	0	0
StayInStableSt	7109587	15827	0	0
gen_high_level_sva.HighLevelEvent_A	7109587	6485978	0	0
gen_not_sticky_sva.StableStDropOut_A	7109587	333	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	985	0	0
T1	16996	4	0	0
T2	0	6	0	0
T3	0	2	0	0
T5	522	0	0	0
T6	409	0	0	0
T11	0	5	0	0
T13	522	0	0	0
T14	502	0	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T27	0	12	0	0
T35	0	10	0	0
T36	0	9	0	0
T48	0	3	0	0
T49	0	4	0	0
T53	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	48198	0	0
T1	16996	292	0	0
T2	0	171	0	0
T3	0	25	0	0
T5	522	0	0	0
T6	409	0	0	0
T11	0	462	0	0
T13	522	0	0	0
T14	502	0	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T27	0	523	0	0
T35	0	247	0	0
T36	0	558	0	0
T48	0	76	0	0
T49	0	150	0	0
T53	0	75	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6482652	0	0
T1	16996	16565	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	69	0	0
T27	30910	5	0	0
T35	10047	5	0	0
T38	0	1	0	0
T42	3304	0	0	0
T48	9944	0	0	0
T49	11736	0	0	0
T54	713	0	0	0
T63	1072	0	0	0
T122	0	3	0	0
T124	0	3	0	0
T125	0	3	0	0
T126	0	9	0	0
T128	0	1	0	0
T129	0	4	0	0
T130	0	1	0	0
T132	402	0	0	0
T133	502	0	0	0
T134	427	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	16253	0	0
T1	16996	16	0	0
T2	0	173	0	0
T3	0	3	0	0
T5	522	0	0	0
T6	409	0	0	0
T11	0	25	0	0
T13	522	0	0	0
T14	502	0	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T36	0	22	0	0
T37	0	81	0	0
T48	0	86	0	0
T49	0	113	0	0
T50	0	207	0	0
T53	0	9	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	382	0	0
T1	16996	2	0	0
T2	0	3	0	0
T3	0	1	0	0
T5	522	0	0	0
T6	409	0	0	0
T11	0	2	0	0
T13	522	0	0	0
T14	502	0	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T36	0	4	0	0
T37	0	2	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	3	0	0
T53	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6127134	0	0
T1	16996	12086	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6128698	0	0
T1	16996	12086	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	534	0	0
T1	16996	2	0	0
T2	0	3	0	0
T3	0	1	0	0
T5	522	0	0	0
T6	409	0	0	0
T11	0	3	0	0
T13	522	0	0	0
T14	502	0	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T27	0	7	0	0
T35	0	5	0	0
T36	0	5	0	0
T48	0	2	0	0
T49	0	2	0	0
T53	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	454	0	0
T1	16996	2	0	0
T2	0	3	0	0
T3	0	1	0	0
T5	522	0	0	0
T6	409	0	0	0
T11	0	2	0	0
T13	522	0	0	0
T14	502	0	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T27	0	5	0	0
T35	0	5	0	0
T36	0	4	0	0
T48	0	1	0	0
T49	0	2	0	0
T53	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	382	0	0
T1	16996	2	0	0
T2	0	3	0	0
T3	0	1	0	0
T5	522	0	0	0
T6	409	0	0	0
T11	0	2	0	0
T13	522	0	0	0
T14	502	0	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T36	0	4	0	0
T37	0	2	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	3	0	0
T53	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	382	0	0
T1	16996	2	0	0
T2	0	3	0	0
T3	0	1	0	0
T5	522	0	0	0
T6	409	0	0	0
T11	0	2	0	0
T13	522	0	0	0
T14	502	0	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T36	0	4	0	0
T37	0	2	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	3	0	0
T53	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	15827	0	0
T1	16996	14	0	0
T2	0	170	0	0
T3	0	2	0	0
T5	522	0	0	0
T6	409	0	0	0
T11	0	23	0	0
T13	522	0	0	0
T14	502	0	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T36	0	18	0	0
T37	0	79	0	0
T48	0	84	0	0
T49	0	111	0	0
T50	0	201	0	0
T53	0	6	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6485978	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	333	0	0
T1	16996	2	0	0
T2	0	3	0	0
T3	0	1	0	0
T5	522	0	0	0
T6	409	0	0	0
T11	0	2	0	0
T13	522	0	0	0
T14	502	0	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T36	0	4	0	0
T37	0	2	0	0
T49	0	2	0	0
T53	0	3	0	0
T144	0	7	0	0
T145	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T30,T4
1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T2,T30,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T2,T30,T4

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T2,T30,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T30,T4
1	0	Covered	T2,T4,T48
1	1	Covered	T2,T30,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T30,T4
0	1	Covered	T30,T51,T48
1	0	Covered	T4,T48,T264

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T49,T50
0	1	Covered	T2,T49,T50
1	0	Covered	T112

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T49,T50
1	-	Covered	T2,T49,T50

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T30,T4
DetectSt	168	Covered	T2,T30,T4
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T2,T49,T50

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T30,T4
DebounceSt->IdleSt	163	Covered	T52,T38,T276
DetectSt->IdleSt	186	Covered	T30,T4,T51
DetectSt->StableSt	191	Covered	T2,T49,T50
IdleSt->DebounceSt	148	Covered	T2,T30,T4
StableSt->IdleSt	206	Covered	T2,T49,T50

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T30,T4
0	1	Covered	T2,T30,T4
0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T30,T4
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T30,T4
IdleSt	0	-	-	-	-	-	-	Covered	T2,T30,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T38,T61
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T30,T4
DebounceSt	-	0	1	0	-	-	-	Covered	T52,T38,T276
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T30,T4
DetectSt	-	-	-	-	1	-	-	Covered	T30,T4,T51
DetectSt	-	-	-	-	0	1	-	Covered	T2,T49,T50
DetectSt	-	-	-	-	0	0	-	Covered	T2,T30,T4
StableSt	-	-	-	-	-	-	1	Covered	T2,T49,T50
StableSt	-	-	-	-	-	-	0	Covered	T2,T49,T50
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7109587	2995	0	0
CntIncr_A	7109587	100272	0	0
CntNoWrap_A	7109587	6480642	0	0
DetectStDropOut_A	7109587	448	0	0
DetectedOut_A	7109587	61538	0	0
DetectedPulseOut_A	7109587	822	0	0
DisabledIdleSt_A	7109587	6063037	0	0
DisabledNoDetection_A	7109587	6065174	0	0
EnterDebounceSt_A	7109587	1526	0	0
EnterDetectSt_A	7109587	1471	0	0
EnterStableSt_A	7109587	822	0	0
PulseIsPulse_A	7109587	822	0	0
StayInStableSt	7109587	60605	0	0
gen_high_event_sva.HighLevelEvent_A	7109587	6485978	0	0
gen_high_level_sva.HighLevelEvent_A	7109587	6485978	0	0
gen_not_sticky_sva.StableStDropOut_A	7109587	686	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	2995	0	0
T2	12694	52	0	0
T3	2766	0	0	0
T4	9089	24	0	0
T29	748	0	0	0
T30	5416	32	0	0
T38	0	14	0	0
T48	0	16	0	0
T49	0	30	0	0
T50	0	24	0	0
T51	0	62	0	0
T52	0	13	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T77	0	8	0	0
T78	423	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	100272	0	0
T2	12694	754	0	0
T3	2766	0	0	0
T4	9089	727	0	0
T29	748	0	0	0
T30	5416	888	0	0
T38	0	334	0	0
T48	0	587	0	0
T49	0	705	0	0
T50	0	492	0	0
T51	0	1643	0	0
T52	0	390	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T77	0	253	0	0
T78	423	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6480642	0	0
T1	16996	16569	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	448	0	0
T3	2766	0	0	0
T4	9089	0	0	0
T25	499	0	0	0
T29	748	0	0	0
T30	5416	16	0	0
T48	0	1	0	0
T51	0	31	0	0
T60	427	0	0	0
T62	976	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T77	0	4	0	0
T78	423	0	0	0
T121	0	26	0	0
T123	0	4	0	0
T141	0	7	0	0
T264	0	1	0	0
T276	0	9	0	0
T280	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	61538	0	0
T2	12694	2123	0	0
T3	2766	0	0	0
T4	9089	0	0	0
T29	748	0	0	0
T30	5416	0	0	0
T34	0	3068	0	0
T38	0	326	0	0
T49	0	1681	0	0
T50	0	568	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T78	423	0	0	0
T112	0	578	0	0
T278	0	121	0	0
T279	0	704	0	0
T281	0	498	0	0
T282	0	2080	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	822	0	0
T2	12694	26	0	0
T3	2766	0	0	0
T4	9089	0	0	0
T29	748	0	0	0
T30	5416	0	0	0
T34	0	16	0	0
T38	0	5	0	0
T49	0	15	0	0
T50	0	12	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T78	423	0	0	0
T112	0	24	0	0
T278	0	5	0	0
T279	0	13	0	0
T281	0	5	0	0
T282	0	23	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6063037	0	0
T1	16996	16569	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6065174	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	1526	0	0
T2	12694	26	0	0
T3	2766	0	0	0
T4	9089	12	0	0
T29	748	0	0	0
T30	5416	16	0	0
T38	0	9	0	0
T48	0	8	0	0
T49	0	15	0	0
T50	0	12	0	0
T51	0	31	0	0
T52	0	13	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T77	0	4	0	0
T78	423	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	1471	0	0
T2	12694	26	0	0
T3	2766	0	0	0
T4	9089	12	0	0
T29	748	0	0	0
T30	5416	16	0	0
T38	0	5	0	0
T48	0	8	0	0
T49	0	15	0	0
T50	0	12	0	0
T51	0	31	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T77	0	4	0	0
T78	423	0	0	0
T264	0	23	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	822	0	0
T2	12694	26	0	0
T3	2766	0	0	0
T4	9089	0	0	0
T29	748	0	0	0
T30	5416	0	0	0
T34	0	16	0	0
T38	0	5	0	0
T49	0	15	0	0
T50	0	12	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T78	423	0	0	0
T112	0	24	0	0
T278	0	5	0	0
T279	0	13	0	0
T281	0	5	0	0
T282	0	23	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	822	0	0
T2	12694	26	0	0
T3	2766	0	0	0
T4	9089	0	0	0
T29	748	0	0	0
T30	5416	0	0	0
T34	0	16	0	0
T38	0	5	0	0
T49	0	15	0	0
T50	0	12	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T78	423	0	0	0
T112	0	24	0	0
T278	0	5	0	0
T279	0	13	0	0
T281	0	5	0	0
T282	0	23	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	60605	0	0
T2	12694	2094	0	0
T3	2766	0	0	0
T4	9089	0	0	0
T29	748	0	0	0
T30	5416	0	0	0
T34	0	3044	0	0
T38	0	321	0	0
T49	0	1666	0	0
T50	0	556	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T78	423	0	0	0
T112	0	554	0	0
T278	0	116	0	0
T279	0	689	0	0
T281	0	490	0	0
T282	0	2056	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6485978	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6485978	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	686	0	0
T2	12694	23	0	0
T3	2766	0	0	0
T4	9089	0	0	0
T29	748	0	0	0
T30	5416	0	0	0
T34	0	8	0	0
T38	0	5	0	0
T49	0	15	0	0
T50	0	12	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T78	423	0	0	0
T278	0	5	0	0
T279	0	11	0	0
T281	0	2	0	0
T282	0	22	0	0
T283	0	24	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T30
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T30
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T2,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T1,T2,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T2,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T11
1	0	Covered	T1,T2,T30
1	1	Covered	T1,T2,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T11
0	1	Covered	T27,T144,T38
1	0	Covered	T38,T61

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T11
0	1	Covered	T1,T2,T11
1	0	Covered	T38,T109,T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T11
1	-	Covered	T1,T2,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T11
DetectSt	168	Covered	T1,T2,T11
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T1,T2,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T11
DebounceSt->IdleSt	163	Covered	T27,T144,T38
DetectSt->IdleSt	186	Covered	T27,T144,T38
DetectSt->StableSt	191	Covered	T1,T2,T11
IdleSt->DebounceSt	148	Covered	T1,T2,T11
StableSt->IdleSt	206	Covered	T1,T2,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T11
0	1	Covered	T1,T2,T11
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T11
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T38,T61
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T27,T144,T122
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T11
DetectSt	-	-	-	-	1	-	-	Covered	T27,T144,T38
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T11
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T11
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T11
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7109587	912	0	0
CntIncr_A	7109587	48000	0	0
CntNoWrap_A	7109587	6482725	0	0
DetectStDropOut_A	7109587	55	0	0
DetectedOut_A	7109587	16687	0	0
DetectedPulseOut_A	7109587	367	0	0
DisabledIdleSt_A	7109587	6155665	0	0
DisabledNoDetection_A	7109587	6157337	0	0
EnterDebounceSt_A	7109587	487	0	0
EnterDetectSt_A	7109587	426	0	0
EnterStableSt_A	7109587	367	0	0
PulseIsPulse_A	7109587	367	0	0
StayInStableSt	7109587	16289	0	0
gen_high_level_sva.HighLevelEvent_A	7109587	6485978	0	0
gen_not_sticky_sva.StableStDropOut_A	7109587	329	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	912	0	0
T1	16996	2	0	0
T2	0	8	0	0
T5	522	0	0	0
T6	409	0	0	0
T11	0	6	0	0
T13	522	0	0	0
T14	502	0	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T27	0	23	0	0
T35	0	10	0	0
T36	0	4	0	0
T37	0	2	0	0
T49	0	12	0	0
T144	0	28	0	0
T145	0	16	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	48000	0	0
T1	16996	135	0	0
T2	0	252	0	0
T5	522	0	0	0
T6	409	0	0	0
T11	0	567	0	0
T13	522	0	0	0
T14	502	0	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T27	0	999	0	0
T35	0	220	0	0
T36	0	150	0	0
T37	0	152	0	0
T49	0	444	0	0
T144	0	2407	0	0
T145	0	560	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6482725	0	0
T1	16996	16567	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	55	0	0
T27	30910	10	0	0
T36	9994	0	0	0
T38	0	1	0	0
T42	3304	0	0	0
T43	835	0	0	0
T48	9944	0	0	0
T49	11736	0	0	0
T63	1072	0	0	0
T122	0	3	0	0
T132	402	0	0	0
T133	502	0	0	0
T134	427	0	0	0
T144	0	13	0	0
T232	0	2	0	0
T233	0	2	0	0
T269	0	11	0	0
T284	0	3	0	0
T285	0	6	0	0
T286	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	16687	0	0
T1	16996	19	0	0
T2	0	208	0	0
T5	522	0	0	0
T6	409	0	0	0
T11	0	15	0	0
T13	522	0	0	0
T14	502	0	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T35	0	30	0	0
T36	0	109	0	0
T37	0	5	0	0
T38	0	91	0	0
T49	0	342	0	0
T145	0	467	0	0
T279	0	84	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	367	0	0
T1	16996	1	0	0
T2	0	4	0	0
T5	522	0	0	0
T6	409	0	0	0
T11	0	3	0	0
T13	522	0	0	0
T14	502	0	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T35	0	5	0	0
T36	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T49	0	6	0	0
T145	0	8	0	0
T279	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6155665	0	0
T1	16996	12086	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6157337	0	0
T1	16996	12086	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	487	0	0
T1	16996	1	0	0
T2	0	4	0	0
T5	522	0	0	0
T6	409	0	0	0
T11	0	3	0	0
T13	522	0	0	0
T14	502	0	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T27	0	13	0	0
T35	0	5	0	0
T36	0	2	0	0
T37	0	1	0	0
T49	0	6	0	0
T144	0	15	0	0
T145	0	8	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	426	0	0
T1	16996	1	0	0
T2	0	4	0	0
T5	522	0	0	0
T6	409	0	0	0
T11	0	3	0	0
T13	522	0	0	0
T14	502	0	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T27	0	10	0	0
T35	0	5	0	0
T36	0	2	0	0
T37	0	1	0	0
T49	0	6	0	0
T144	0	14	0	0
T145	0	8	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	367	0	0
T1	16996	1	0	0
T2	0	4	0	0
T5	522	0	0	0
T6	409	0	0	0
T11	0	3	0	0
T13	522	0	0	0
T14	502	0	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T35	0	5	0	0
T36	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T49	0	6	0	0
T145	0	8	0	0
T279	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	367	0	0
T1	16996	1	0	0
T2	0	4	0	0
T5	522	0	0	0
T6	409	0	0	0
T11	0	3	0	0
T13	522	0	0	0
T14	502	0	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T35	0	5	0	0
T36	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T49	0	6	0	0
T145	0	8	0	0
T279	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	16289	0	0
T1	16996	18	0	0
T2	0	204	0	0
T5	522	0	0	0
T6	409	0	0	0
T11	0	11	0	0
T13	522	0	0	0
T14	502	0	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T35	0	25	0	0
T36	0	107	0	0
T37	0	4	0	0
T38	0	90	0	0
T49	0	336	0	0
T145	0	459	0	0
T279	0	82	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6485978	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	329	0	0
T1	16996	1	0	0
T2	0	4	0	0
T5	522	0	0	0
T6	409	0	0	0
T11	0	2	0	0
T13	522	0	0	0
T14	502	0	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T34	0	8	0	0
T35	0	5	0	0
T36	0	2	0	0
T37	0	1	0	0
T49	0	6	0	0
T145	0	8	0	0
T281	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T30,T4
1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T2,T30,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T2,T30,T4

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T2,T30,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T30,T4
1	0	Covered	T2,T4,T48
1	1	Covered	T2,T30,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T30,T4
0	1	Covered	T30,T51,T52
1	0	Covered	T49,T38,T34

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T48
0	1	Covered	T2,T4,T48
1	0	Covered	T38,T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T4,T48
1	-	Covered	T2,T4,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T30,T4
DetectSt	168	Covered	T2,T30,T4
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T2,T4,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T30,T4
DebounceSt->IdleSt	163	Covered	T52,T38,T276
DetectSt->IdleSt	186	Covered	T30,T51,T52
DetectSt->StableSt	191	Covered	T2,T4,T48
IdleSt->DebounceSt	148	Covered	T2,T30,T4
StableSt->IdleSt	206	Covered	T2,T4,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T30,T4
0	1	Covered	T2,T30,T4
0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T30,T4
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T30,T4
IdleSt	0	-	-	-	-	-	-	Covered	T2,T30,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T38,T61
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T30,T4
DebounceSt	-	0	1	0	-	-	-	Covered	T52,T38,T276
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T30,T4
DetectSt	-	-	-	-	1	-	-	Covered	T30,T51,T52
DetectSt	-	-	-	-	0	1	-	Covered	T2,T4,T48
DetectSt	-	-	-	-	0	0	-	Covered	T2,T30,T4
StableSt	-	-	-	-	-	-	1	Covered	T2,T4,T48
StableSt	-	-	-	-	-	-	0	Covered	T2,T4,T48
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7109587	2947	0	0
CntIncr_A	7109587	99702	0	0
CntNoWrap_A	7109587	6480690	0	0
DetectStDropOut_A	7109587	448	0	0
DetectedOut_A	7109587	65862	0	0
DetectedPulseOut_A	7109587	855	0	0
DisabledIdleSt_A	7109587	6055296	0	0
DisabledNoDetection_A	7109587	6057440	0	0
EnterDebounceSt_A	7109587	1499	0	0
EnterDetectSt_A	7109587	1449	0	0
EnterStableSt_A	7109587	855	0	0
PulseIsPulse_A	7109587	855	0	0
StayInStableSt	7109587	64902	0	0
gen_high_event_sva.HighLevelEvent_A	7109587	6485978	0	0
gen_high_level_sva.HighLevelEvent_A	7109587	6485978	0	0
gen_not_sticky_sva.StableStDropOut_A	7109587	748	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	2947	0	0
T2	12694	26	0	0
T3	2766	0	0	0
T4	9089	32	0	0
T29	748	0	0	0
T30	5416	42	0	0
T38	0	16	0	0
T48	0	62	0	0
T49	0	40	0	0
T50	0	12	0	0
T51	0	28	0	0
T52	0	33	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T77	0	18	0	0
T78	423	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	99702	0	0
T2	12694	559	0	0
T3	2766	0	0	0
T4	9089	928	0	0
T29	748	0	0	0
T30	5416	1172	0	0
T38	0	508	0	0
T48	0	2232	0	0
T49	0	1308	0	0
T50	0	384	0	0
T51	0	732	0	0
T52	0	810	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T77	0	570	0	0
T78	423	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6480690	0	0
T1	16996	16569	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	448	0	0
T3	2766	0	0	0
T4	9089	0	0	0
T25	499	0	0	0
T29	748	0	0	0
T30	5416	21	0	0
T34	0	19	0	0
T38	0	1	0	0
T49	0	9	0	0
T51	0	14	0	0
T52	0	6	0	0
T60	427	0	0	0
T62	976	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T77	0	9	0	0
T78	423	0	0	0
T121	0	29	0	0
T123	0	24	0	0
T141	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	65862	0	0
T2	12694	572	0	0
T3	2766	0	0	0
T4	9089	428	0	0
T29	748	0	0	0
T30	5416	0	0	0
T38	0	315	0	0
T48	0	1359	0	0
T50	0	203	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T78	423	0	0	0
T112	0	404	0	0
T264	0	1115	0	0
T278	0	1494	0	0
T279	0	408	0	0
T281	0	2446	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	855	0	0
T2	12694	13	0	0
T3	2766	0	0	0
T4	9089	16	0	0
T29	748	0	0	0
T30	5416	0	0	0
T38	0	5	0	0
T48	0	31	0	0
T50	0	6	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T78	423	0	0	0
T112	0	20	0	0
T264	0	25	0	0
T278	0	26	0	0
T279	0	10	0	0
T281	0	20	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6055296	0	0
T1	16996	16569	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6057440	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	1499	0	0
T2	12694	13	0	0
T3	2766	0	0	0
T4	9089	16	0	0
T29	748	0	0	0
T30	5416	21	0	0
T38	0	9	0	0
T48	0	31	0	0
T49	0	20	0	0
T50	0	6	0	0
T51	0	14	0	0
T52	0	27	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T77	0	9	0	0
T78	423	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	1449	0	0
T2	12694	13	0	0
T3	2766	0	0	0
T4	9089	16	0	0
T29	748	0	0	0
T30	5416	21	0	0
T38	0	7	0	0
T48	0	31	0	0
T49	0	20	0	0
T50	0	6	0	0
T51	0	14	0	0
T52	0	6	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T77	0	9	0	0
T78	423	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	855	0	0
T2	12694	13	0	0
T3	2766	0	0	0
T4	9089	16	0	0
T29	748	0	0	0
T30	5416	0	0	0
T38	0	5	0	0
T48	0	31	0	0
T50	0	6	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T78	423	0	0	0
T112	0	20	0	0
T264	0	25	0	0
T278	0	26	0	0
T279	0	10	0	0
T281	0	20	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	855	0	0
T2	12694	13	0	0
T3	2766	0	0	0
T4	9089	16	0	0
T29	748	0	0	0
T30	5416	0	0	0
T38	0	5	0	0
T48	0	31	0	0
T50	0	6	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T78	423	0	0	0
T112	0	20	0	0
T264	0	25	0	0
T278	0	26	0	0
T279	0	10	0	0
T281	0	20	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	64902	0	0
T2	12694	559	0	0
T3	2766	0	0	0
T4	9089	411	0	0
T29	748	0	0	0
T30	5416	0	0	0
T38	0	310	0	0
T48	0	1328	0	0
T50	0	197	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T78	423	0	0	0
T112	0	383	0	0
T264	0	1087	0	0
T278	0	1467	0	0
T279	0	397	0	0
T281	0	2418	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6485978	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6485978	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	748	0	0
T2	12694	13	0	0
T3	2766	0	0	0
T4	9089	15	0	0
T29	748	0	0	0
T30	5416	0	0	0
T38	0	4	0	0
T48	0	31	0	0
T50	0	6	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T78	423	0	0	0
T112	0	19	0	0
T264	0	22	0	0
T278	0	25	0	0
T279	0	9	0	0
T281	0	12	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T30
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T30
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T2,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T1,T2,T4

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T2,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T30
1	1	Covered	T1,T2,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T144,T122
1	0	Covered	T38,T61

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T11
0	1	Covered	T2,T4,T11
1	0	Covered	T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T4,T11
1	-	Covered	T2,T4,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T4
DetectSt	168	Covered	T1,T2,T4
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T2,T4,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T4
DebounceSt->IdleSt	163	Covered	T27,T144,T38
DetectSt->IdleSt	186	Covered	T1,T144,T38
DetectSt->StableSt	191	Covered	T2,T4,T11
IdleSt->DebounceSt	148	Covered	T1,T2,T4
StableSt->IdleSt	206	Covered	T2,T4,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T38,T61
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T4
DebounceSt	-	0	1	0	-	-	-	Covered	T27,T144,T287
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T4
DetectSt	-	-	-	-	1	-	-	Covered	T1,T144,T38
DetectSt	-	-	-	-	0	1	-	Covered	T2,T4,T11
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T4
StableSt	-	-	-	-	-	-	1	Covered	T2,T4,T11
StableSt	-	-	-	-	-	-	0	Covered	T2,T4,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7109587	804	0	0
CntIncr_A	7109587	41294	0	0
CntNoWrap_A	7109587	6482833	0	0
DetectStDropOut_A	7109587	38	0	0
DetectedOut_A	7109587	15483	0	0
DetectedPulseOut_A	7109587	338	0	0
DisabledIdleSt_A	7109587	6139816	0	0
DisabledNoDetection_A	7109587	6141487	0	0
EnterDebounceSt_A	7109587	425	0	0
EnterDetectSt_A	7109587	381	0	0
EnterStableSt_A	7109587	338	0	0
PulseIsPulse_A	7109587	338	0	0
StayInStableSt	7109587	15115	0	0
gen_high_level_sva.HighLevelEvent_A	7109587	6485978	0	0
gen_not_sticky_sva.StableStDropOut_A	7109587	307	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	804	0	0
T1	16996	4	0	0
T2	0	2	0	0
T4	0	2	0	0
T5	522	0	0	0
T6	409	0	0	0
T11	0	4	0	0
T13	522	0	0	0
T14	502	0	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T27	0	25	0	0
T35	0	4	0	0
T36	0	10	0	0
T38	0	8	0	0
T144	0	8	0	0
T145	0	10	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	41294	0	0
T1	16996	308	0	0
T2	0	35	0	0
T4	0	40	0	0
T5	522	0	0	0
T6	409	0	0	0
T11	0	268	0	0
T13	522	0	0	0
T14	502	0	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T27	0	934	0	0
T35	0	90	0	0
T36	0	415	0	0
T38	0	153	0	0
T144	0	739	0	0
T145	0	560	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6482833	0	0
T1	16996	16565	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	38	0	0
T1	16996	2	0	0
T5	522	0	0	0
T6	409	0	0	0
T13	522	0	0	0
T14	502	0	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T122	0	3	0	0
T144	0	3	0	0
T147	0	3	0	0
T154	0	1	0	0
T173	0	2	0	0
T196	0	8	0	0
T213	0	1	0	0
T233	0	4	0	0
T284	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	15483	0	0
T2	12694	80	0	0
T3	2766	0	0	0
T4	9089	75	0	0
T11	0	120	0	0
T27	0	116	0	0
T29	748	0	0	0
T30	5416	0	0	0
T35	0	8	0	0
T36	0	233	0	0
T38	0	90	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T78	423	0	0	0
T145	0	80	0	0
T264	0	202	0	0
T278	0	72	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	338	0	0
T2	12694	1	0	0
T3	2766	0	0	0
T4	9089	1	0	0
T11	0	2	0	0
T27	0	12	0	0
T29	748	0	0	0
T30	5416	0	0	0
T35	0	2	0	0
T36	0	5	0	0
T38	0	1	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T78	423	0	0	0
T145	0	5	0	0
T264	0	5	0	0
T278	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6139816	0	0
T1	16996	12086	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6141487	0	0
T1	16996	12086	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	425	0	0
T1	16996	2	0	0
T2	0	1	0	0
T4	0	1	0	0
T5	522	0	0	0
T6	409	0	0	0
T11	0	2	0	0
T13	522	0	0	0
T14	502	0	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T27	0	13	0	0
T35	0	2	0	0
T36	0	5	0	0
T38	0	5	0	0
T144	0	5	0	0
T145	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	381	0	0
T1	16996	2	0	0
T2	0	1	0	0
T4	0	1	0	0
T5	522	0	0	0
T6	409	0	0	0
T11	0	2	0	0
T13	522	0	0	0
T14	502	0	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T27	0	12	0	0
T35	0	2	0	0
T36	0	5	0	0
T38	0	3	0	0
T144	0	4	0	0
T145	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	338	0	0
T2	12694	1	0	0
T3	2766	0	0	0
T4	9089	1	0	0
T11	0	2	0	0
T27	0	12	0	0
T29	748	0	0	0
T30	5416	0	0	0
T35	0	2	0	0
T36	0	5	0	0
T38	0	1	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T78	423	0	0	0
T145	0	5	0	0
T264	0	5	0	0
T278	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	338	0	0
T2	12694	1	0	0
T3	2766	0	0	0
T4	9089	1	0	0
T11	0	2	0	0
T27	0	12	0	0
T29	748	0	0	0
T30	5416	0	0	0
T35	0	2	0	0
T36	0	5	0	0
T38	0	1	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T78	423	0	0	0
T145	0	5	0	0
T264	0	5	0	0
T278	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	15115	0	0
T2	12694	79	0	0
T3	2766	0	0	0
T4	9089	74	0	0
T11	0	118	0	0
T27	0	104	0	0
T29	748	0	0	0
T30	5416	0	0	0
T35	0	6	0	0
T36	0	228	0	0
T38	0	89	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T78	423	0	0	0
T145	0	75	0	0
T264	0	197	0	0
T278	0	70	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6485978	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	307	0	0
T2	12694	1	0	0
T3	2766	0	0	0
T4	9089	1	0	0
T11	0	2	0	0
T27	0	12	0	0
T29	748	0	0	0
T30	5416	0	0	0
T35	0	2	0	0
T36	0	5	0	0
T38	0	1	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T78	423	0	0	0
T145	0	5	0	0
T264	0	5	0	0
T287	0	2	0	0