Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T30,T4
1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T2,T30,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T2,T30,T4

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T2,T30,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T30,T4
1	0	Covered	T2,T4,T48
1	1	Covered	T2,T30,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T30,T4
0	1	Covered	T2,T30,T51
1	0	Covered	T48,T49,T38

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T50,T38
0	1	Covered	T4,T50,T38
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T50,T38
1	-	Covered	T4,T50,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T30,T4
DetectSt	168	Covered	T2,T30,T4
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T4,T50,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T30,T4
DebounceSt->IdleSt	163	Covered	T52,T38,T276
DetectSt->IdleSt	186	Covered	T2,T30,T51
DetectSt->StableSt	191	Covered	T4,T50,T38
IdleSt->DebounceSt	148	Covered	T2,T30,T4
StableSt->IdleSt	206	Covered	T4,T50,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T30,T4
0	1	Covered	T2,T30,T4
0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T30,T4
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T30,T4
IdleSt	0	-	-	-	-	-	-	Covered	T2,T30,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T38,T61
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T30,T4
DebounceSt	-	0	1	0	-	-	-	Covered	T52,T38,T276
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T30,T4
DetectSt	-	-	-	-	1	-	-	Covered	T2,T30,T51
DetectSt	-	-	-	-	0	1	-	Covered	T4,T50,T38
DetectSt	-	-	-	-	0	0	-	Covered	T2,T30,T4
StableSt	-	-	-	-	-	-	1	Covered	T4,T50,T38
StableSt	-	-	-	-	-	-	0	Covered	T4,T50,T38
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7109587	3047	0	0
CntIncr_A	7109587	97798	0	0
CntNoWrap_A	7109587	6480590	0	0
DetectStDropOut_A	7109587	487	0	0
DetectedOut_A	7109587	62392	0	0
DetectedPulseOut_A	7109587	733	0	0
DisabledIdleSt_A	7109587	6062993	0	0
DisabledNoDetection_A	7109587	6065131	0	0
EnterDebounceSt_A	7109587	1551	0	0
EnterDetectSt_A	7109587	1497	0	0
EnterStableSt_A	7109587	733	0	0
PulseIsPulse_A	7109587	733	0	0
StayInStableSt	7109587	61549	0	0
gen_high_event_sva.HighLevelEvent_A	7109587	6485978	0	0
gen_high_level_sva.HighLevelEvent_A	7109587	6485978	0	0
gen_not_sticky_sva.StableStDropOut_A	7109587	623	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	3047	0	0
T2	12694	2	0	0
T3	2766	0	0	0
T4	9089	42	0	0
T29	748	0	0	0
T30	5416	16	0	0
T38	0	16	0	0
T48	0	8	0	0
T49	0	56	0	0
T50	0	58	0	0
T51	0	38	0	0
T52	0	33	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T77	0	14	0	0
T78	423	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	97798	0	0
T2	12694	46	0	0
T3	2766	0	0	0
T4	9089	819	0	0
T29	748	0	0	0
T30	5416	441	0	0
T38	0	366	0	0
T48	0	295	0	0
T49	0	1841	0	0
T50	0	1914	0	0
T51	0	999	0	0
T52	0	780	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T77	0	445	0	0
T78	423	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6480590	0	0
T1	16996	16569	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	487	0	0
T2	12694	1	0	0
T3	2766	0	0	0
T4	9089	0	0	0
T29	748	0	0	0
T30	5416	8	0	0
T34	0	21	0	0
T38	0	1	0	0
T49	0	13	0	0
T51	0	19	0	0
T52	0	7	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T77	0	7	0	0
T78	423	0	0	0
T121	0	29	0	0
T123	0	24	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	62392	0	0
T4	9089	1831	0	0
T7	29986	0	0	0
T23	859	0	0	0
T25	499	0	0	0
T38	0	354	0	0
T50	0	1772	0	0
T51	5284	0	0	0
T62	976	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T75	523	0	0	0
T78	423	0	0	0
T112	0	61	0	0
T264	0	775	0	0
T278	0	86	0	0
T279	0	2986	0	0
T280	0	200	0	0
T282	0	266	0	0
T283	0	3330	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	733	0	0
T4	9089	21	0	0
T7	29986	0	0	0
T23	859	0	0	0
T25	499	0	0	0
T38	0	5	0	0
T50	0	29	0	0
T51	5284	0	0	0
T62	976	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T75	523	0	0	0
T78	423	0	0	0
T112	0	8	0	0
T264	0	20	0	0
T278	0	10	0	0
T279	0	29	0	0
T280	0	6	0	0
T282	0	9	0	0
T283	0	27	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6062993	0	0
T1	16996	16569	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6065131	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	1551	0	0
T2	12694	1	0	0
T3	2766	0	0	0
T4	9089	21	0	0
T29	748	0	0	0
T30	5416	8	0	0
T38	0	9	0	0
T48	0	4	0	0
T49	0	28	0	0
T50	0	29	0	0
T51	0	19	0	0
T52	0	26	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T77	0	7	0	0
T78	423	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	1497	0	0
T2	12694	1	0	0
T3	2766	0	0	0
T4	9089	21	0	0
T29	748	0	0	0
T30	5416	8	0	0
T38	0	7	0	0
T48	0	4	0	0
T49	0	28	0	0
T50	0	29	0	0
T51	0	19	0	0
T52	0	7	0	0
T59	406	0	0	0
T60	427	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T77	0	7	0	0
T78	423	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	733	0	0
T4	9089	21	0	0
T7	29986	0	0	0
T23	859	0	0	0
T25	499	0	0	0
T38	0	5	0	0
T50	0	29	0	0
T51	5284	0	0	0
T62	976	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T75	523	0	0	0
T78	423	0	0	0
T112	0	8	0	0
T264	0	20	0	0
T278	0	10	0	0
T279	0	29	0	0
T280	0	6	0	0
T282	0	9	0	0
T283	0	27	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	733	0	0
T4	9089	21	0	0
T7	29986	0	0	0
T23	859	0	0	0
T25	499	0	0	0
T38	0	5	0	0
T50	0	29	0	0
T51	5284	0	0	0
T62	976	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T75	523	0	0	0
T78	423	0	0	0
T112	0	8	0	0
T264	0	20	0	0
T278	0	10	0	0
T279	0	29	0	0
T280	0	6	0	0
T282	0	9	0	0
T283	0	27	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	61549	0	0
T4	9089	1809	0	0
T7	29986	0	0	0
T23	859	0	0	0
T25	499	0	0	0
T38	0	349	0	0
T50	0	1738	0	0
T51	5284	0	0	0
T62	976	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T75	523	0	0	0
T78	423	0	0	0
T112	0	53	0	0
T264	0	752	0	0
T278	0	76	0	0
T279	0	2952	0	0
T280	0	193	0	0
T282	0	257	0	0
T283	0	3300	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6485978	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6485978	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	623	0	0
T4	9089	20	0	0
T7	29986	0	0	0
T23	859	0	0	0
T25	499	0	0	0
T38	0	5	0	0
T50	0	24	0	0
T51	5284	0	0	0
T62	976	0	0	0
T72	523	0	0	0
T73	526	0	0	0
T75	523	0	0	0
T78	423	0	0	0
T112	0	8	0	0
T264	0	17	0	0
T278	0	10	0	0
T279	0	24	0	0
T280	0	5	0	0
T282	0	9	0	0
T283	0	24	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T30
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T30
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T4,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T1,T4,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T4,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T11
1	0	Covered	T1,T2,T30
1	1	Covered	T1,T4,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T11
0	1	Covered	T11,T287,T233
1	0	Covered	T38,T61

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T35
0	1	Covered	T1,T4,T35
1	0	Covered	T38

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T4,T35
1	-	Covered	T1,T4,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T4,T11
DetectSt	168	Covered	T1,T4,T11
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T1,T4,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T4,T11
DebounceSt->IdleSt	163	Covered	T11,T27,T145
DetectSt->IdleSt	186	Covered	T11,T38,T287
DetectSt->StableSt	191	Covered	T1,T4,T35
IdleSt->DebounceSt	148	Covered	T1,T4,T11
StableSt->IdleSt	206	Covered	T1,T4,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T4,T11
0	1	Covered	T1,T4,T11
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T11
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T4,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T38,T61
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T4,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T27,T145
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T4,T11
DetectSt	-	-	-	-	1	-	-	Covered	T11,T38,T287
DetectSt	-	-	-	-	0	1	-	Covered	T1,T4,T35
DetectSt	-	-	-	-	0	0	-	Covered	T1,T4,T11
StableSt	-	-	-	-	-	-	1	Covered	T1,T4,T35
StableSt	-	-	-	-	-	-	0	Covered	T1,T4,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7109587	847	0	0
CntIncr_A	7109587	42171	0	0
CntNoWrap_A	7109587	6482790	0	0
DetectStDropOut_A	7109587	59	0	0
DetectedOut_A	7109587	15397	0	0
DetectedPulseOut_A	7109587	335	0	0
DisabledIdleSt_A	7109587	6157133	0	0
DisabledNoDetection_A	7109587	6158818	0	0
EnterDebounceSt_A	7109587	449	0	0
EnterDetectSt_A	7109587	398	0	0
EnterStableSt_A	7109587	335	0	0
PulseIsPulse_A	7109587	335	0	0
StayInStableSt	7109587	15021	0	0
gen_high_level_sva.HighLevelEvent_A	7109587	6485978	0	0
gen_not_sticky_sva.StableStDropOut_A	7109587	291	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	847	0	0
T1	16996	10	0	0
T4	0	8	0	0
T5	522	0	0	0
T6	409	0	0	0
T11	0	9	0	0
T13	522	0	0	0
T14	502	0	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T27	0	9	0	0
T35	0	2	0	0
T36	0	2	0	0
T38	0	8	0	0
T50	0	8	0	0
T144	0	10	0	0
T145	0	31	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	42171	0	0
T1	16996	655	0	0
T4	0	276	0	0
T5	522	0	0	0
T6	409	0	0	0
T11	0	876	0	0
T13	522	0	0	0
T14	502	0	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T27	0	338	0	0
T35	0	45	0	0
T36	0	83	0	0
T38	0	192	0	0
T50	0	244	0	0
T144	0	440	0	0
T145	0	1386	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6482790	0	0
T1	16996	16559	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	59	0	0
T11	15931	4	0	0
T12	70930	0	0	0
T27	30910	0	0	0
T35	10047	0	0	0
T53	6617	0	0	0
T54	713	0	0	0
T82	502	0	0	0
T151	426	0	0	0
T152	441	0	0	0
T233	0	13	0	0
T268	0	6	0	0
T273	0	9	0	0
T287	0	3	0	0
T288	0	6	0	0
T289	0	1	0	0
T290	0	2	0	0
T291	0	1	0	0
T292	0	9	0	0
T293	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	15397	0	0
T1	16996	116	0	0
T4	0	183	0	0
T5	522	0	0	0
T6	409	0	0	0
T13	522	0	0	0
T14	502	0	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T27	0	48	0	0
T35	0	4	0	0
T36	0	46	0	0
T38	0	90	0	0
T50	0	210	0	0
T144	0	391	0	0
T145	0	603	0	0
T264	0	189	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	335	0	0
T1	16996	5	0	0
T4	0	4	0	0
T5	522	0	0	0
T6	409	0	0	0
T13	522	0	0	0
T14	502	0	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T27	0	4	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T50	0	4	0	0
T144	0	5	0	0
T145	0	15	0	0
T264	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6157133	0	0
T1	16996	12086	0	0
T5	522	121	0	0
T6	409	8	0	0
T13	522	121	0	0
T14	502	101	0	0
T15	589	188	0	0
T16	688	287	0	0
T17	407	6	0	0
T18	419	18	0	0
T19	525	124	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6158818	0	0
T1	16996	12086	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	449	0	0
T1	16996	5	0	0
T4	0	4	0	0
T5	522	0	0	0
T6	409	0	0	0
T11	0	5	0	0
T13	522	0	0	0
T14	502	0	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T27	0	5	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	5	0	0
T50	0	4	0	0
T144	0	5	0	0
T145	0	16	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	398	0	0
T1	16996	5	0	0
T4	0	4	0	0
T5	522	0	0	0
T6	409	0	0	0
T11	0	4	0	0
T13	522	0	0	0
T14	502	0	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T27	0	4	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	3	0	0
T50	0	4	0	0
T144	0	5	0	0
T145	0	15	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	335	0	0
T1	16996	5	0	0
T4	0	4	0	0
T5	522	0	0	0
T6	409	0	0	0
T13	522	0	0	0
T14	502	0	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T27	0	4	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T50	0	4	0	0
T144	0	5	0	0
T145	0	15	0	0
T264	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	335	0	0
T1	16996	5	0	0
T4	0	4	0	0
T5	522	0	0	0
T6	409	0	0	0
T13	522	0	0	0
T14	502	0	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T27	0	4	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T50	0	4	0	0
T144	0	5	0	0
T145	0	15	0	0
T264	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	15021	0	0
T1	16996	111	0	0
T4	0	179	0	0
T5	522	0	0	0
T6	409	0	0	0
T13	522	0	0	0
T14	502	0	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T27	0	44	0	0
T35	0	3	0	0
T36	0	45	0	0
T38	0	89	0	0
T50	0	202	0	0
T144	0	385	0	0
T145	0	588	0	0
T264	0	186	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	6485978	0	0
T1	16996	16575	0	0
T5	522	122	0	0
T6	409	9	0	0
T13	522	122	0	0
T14	502	102	0	0
T15	589	189	0	0
T16	688	288	0	0
T17	407	7	0	0
T18	419	19	0	0
T19	525	125	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7109587	291	0	0
T1	16996	5	0	0
T4	0	4	0	0
T5	522	0	0	0
T6	409	0	0	0
T13	522	0	0	0
T14	502	0	0	0
T15	589	0	0	0
T16	688	0	0	0
T17	407	0	0	0
T18	419	0	0	0
T19	525	0	0	0
T27	0	4	0	0
T35	0	1	0	0
T36	0	1	0	0
T122	0	8	0	0
T144	0	4	0	0
T145	0	15	0	0
T264	0	3	0	0
T279	0	1	0	0