SYSRST_CTRL Simulation Results

Thursday May 16 2024 19:02:11 UTC

GitHub Revision: `349bab6601`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 60729333463373082946889975499553948547086354767408862399987151421185145065082

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	6.570s	2.110ms	50	50	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	8.230s	2.455ms	50	50	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	6.930s	2.416ms	5	5	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	7.190s	2.500ms	5	5	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	16.930s	6.029ms	5	5	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	6.340s	2.026ms	20	20	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	4.529m	68.147ms	5	5	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	7.860s	2.164ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	6.640s	2.135ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	6.340s	2.026ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	7.860s	2.164ms	5	5	100.00
V1		TOTAL			165	165	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	6.865m	157.139ms	50	50	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	6.094m	133.602ms	94	100	94.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	12.310m	288.086ms	50	50	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	12.460s	4.638ms	50	50	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	7.740s	2.513ms	50	50	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	6.680s	2.178ms	50	50	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	41.001m	1.028s	48	50	96.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	7.900s	2.615ms	50	50	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	2.260m	476.163ms	49	50	98.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	1.737m	41.745ms	2	2	100.00
V2	stress_all	sysrst_ctrl_stress_all	8.916m	198.494ms	49	50	98.00
V2	alert_test	sysrst_ctrl_alert_test	6.430s	2.012ms	50	50	100.00
V2	intr_test	sysrst_ctrl_intr_test	6.120s	2.012ms	50	50	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	7.880s	2.129ms	20	20	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	7.880s	2.129ms	20	20	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	16.930s	6.029ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.340s	2.026ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	7.860s	2.164ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	48.340s	10.431ms	20	20	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	16.930s	6.029ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.340s	2.026ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	7.860s	2.164ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	48.340s	10.431ms	20	20	100.00
V2		TOTAL			682	692	98.55
V2S	tl_intg_err	sysrst_ctrl_sec_cm	1.011m	22.012ms	5	5	100.00
		sysrst_ctrl_tl_intg_err	2.045m	42.460ms	20	20	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	2.045m	42.460ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	4.888m	1.010s	41	50	82.00
V3		TOTAL			41	50	82.00
		TOTAL			913	932	97.96

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	15	15	11	73.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.71	99.10	96.96	100.00	97.44	98.56	99.71	92.20

Failure Buckets

UVM_FATAL (sysrst_ctrl_base_vseq.sv:67) [sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == * has 4 failures:
- Test sysrst_ctrl_stress_all_with_rand_reset has 2 failures.
  - 6.sysrst_ctrl_stress_all_with_rand_reset.82052625653008798601917046721277269626614707056741458672703339105358738436946
    Line 561, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 4236067849 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
  UVM_INFO @ 4236067849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.sysrst_ctrl_stress_all_with_rand_reset.108943364548586810262109535752058028553429457005458997821837733936125825220031
    Line 564, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 6774555312 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
  UVM_INFO @ 6774555312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test sysrst_ctrl_ec_pwr_on_rst has 2 failures.
  - 12.sysrst_ctrl_ec_pwr_on_rst.70050161682987232043866247644751774962006825962122082181487231979279930306831
    Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_ec_pwr_on_rst/latest/run.log
```
  UVM_FATAL @ 2414171265 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
  UVM_INFO @ 2414171265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.sysrst_ctrl_ec_pwr_on_rst.55838934608215288452717889805067933874895979973803130731536978936538491942474
    Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_ec_pwr_on_rst/latest/run.log
```
  UVM_FATAL @ 2596573942 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
  UVM_INFO @ 2596573942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 3 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 2 failures.

4.sysrst_ctrl_stress_all_with_rand_reset.68658406458485439068546644663657377749026119675078844139293243771093289354751
Line 628, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 44791230744 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 44873730744 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
  UVM_INFO @ 47108730744 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 47156036714 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_auto_blk_key_output_vseq
  UVM_INFO @ 49154286714 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:76) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Starting the body from auto_blk_key_output_vseq

30.sysrst_ctrl_stress_all_with_rand_reset.78195741547271834660700525285044935927304405102256217690686975847884571784299
Line 715, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 401736410566 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 402523910566 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 402523910566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test sysrst_ctrl_ultra_low_pwr has 1 failures.

13.sysrst_ctrl_ultra_low_pwr.91244741699760671426229371968184448434691902105963224212146916684295459198007
Line 559, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 3662298947 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 3809798947 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
  UVM_INFO @ 5274798947 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
  UVM_INFO @ 7199798947 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 7210491267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

UVM_ERROR (sysrst_ctrl_auto_blk_key_output_vseq.sv:122) [sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key2_out_value == cfg.vif.key2_out (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all has 1 failures.

7.sysrst_ctrl_stress_all.112928932311311768813930194632923410335665662926435135196914608046702335341759
Line 561, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 4547818421 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key2_out_value == cfg.vif.key2_out (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 4647916861 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:88) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Debounce timer set for: 38
  UVM_INFO @ 5042818421 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:100) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Value of cycles:64
  UVM_INFO @ 5147916861 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:88) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Debounce timer set for: 42
  UVM_INFO @ 5532818421 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:100) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Value of cycles:67

UVM_ERROR (sysrst_ctrl_combo_detect_vseq.sv:277) virtual_sequencer [sysrst_ctrl_combo_detect_vseq] wkup_status.wakeup_sts set to * has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

16.sysrst_ctrl_stress_all_with_rand_reset.47900528582121456570671197065849024398220335596733709781170649456280123057357
Line 588, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 25125080785 ps: (sysrst_ctrl_combo_detect_vseq.sv:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_vseq] wkup_status.wakeup_sts set to 0
  UVM_INFO @ 25145541683 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Stress w/ reset is done for run 3/10
  UVM_INFO @ 25148837323 ps: (dv_base_reg.sv:325) [sysrst_ctrl_reg_block.regwen] lock_lockable_flds          1 val
  UVM_INFO @ 25149317323 ps: (cip_base_vseq.sv:717) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 4/10

UVM_ERROR (sysrst_ctrl_flash_wr_prot_vseq.sv:55) [sysrst_ctrl_flash_wr_prot_vseq] Check failed cfg.vif.flash_wp_l == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

23.sysrst_ctrl_stress_all_with_rand_reset.26450678201290535254338320501022132558484545985948838550150270820530413656219
Line 616, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 27515010354 ps: (sysrst_ctrl_flash_wr_prot_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_flash_wr_prot_vseq] Check failed cfg.vif.flash_wp_l == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 27520402885 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Stress w/ reset is done for run 5/10
  UVM_INFO @ 27523030020 ps: (dv_base_reg.sv:325) [sysrst_ctrl_reg_block.regwen] lock_lockable_flds          1 val
  UVM_INFO @ 27524771952 ps: (cip_base_vseq.sv:717) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 6/10

UVM_ERROR (sysrst_ctrl_ec_pwr_on_rst_vseq.sv:46) [sysrst_ctrl_ec_pwr_on_rst_vseq] Check failed cfg.vif.ec_rst_l_out == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

32.sysrst_ctrl_stress_all_with_rand_reset.106224330721256205715733283623028853102452474816627163760125484626094028687774
Line 575, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 9849096191 ps: (sysrst_ctrl_ec_pwr_on_rst_vseq.sv:46) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] Check failed cfg.vif.ec_rst_l_out == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 9860885886 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Stress w/ reset is done for run 2/5
  UVM_INFO @ 9861786627 ps: (dv_base_reg.sv:325) [sysrst_ctrl_reg_block.regwen] lock_lockable_flds          1 val
  UVM_INFO @ 9863316627 ps: (cip_base_vseq.sv:717) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 3/5

UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:109) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

35.sysrst_ctrl_stress_all_with_rand_reset.41893917533311624145147882206080151008922592580061154942667756732786393758891
Line 584, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 18503883665 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:109) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 18503883665 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:115) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key2_in == inv_key2_out (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 18503883665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(9) vs exp(4) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

36.sysrst_ctrl_combo_detect_with_pre_cond.26152320245435576526847240685827934027601501722177767560936860236588605729167
Line 613, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 60093712020 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(9) vs exp(4) +/-4
  UVM_INFO @ 60098712020 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:152) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_h2l_expected == 0
  UVM_INFO @ 60278712020 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
  UVM_INFO @ 60298712020 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
  UVM_INFO @ 70330252911 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x28

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

37.sysrst_ctrl_combo_detect_with_pre_cond.32081091530189140911759378905890817197870368717137911760361552609826913333385
Line 578, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 40180350022 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 50506741168 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2d
  UVM_INFO @ 50506821168 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0xe
  UVM_INFO @ 50965541168 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 1
  UVM_INFO @ 50965541168 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 2

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(7) vs exp(2) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

38.sysrst_ctrl_combo_detect_with_pre_cond.111018140678027490527057711308693844365521414147670856627913734229871610628629
Line 571, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 13455285670 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(7) vs exp(2) +/-4
  UVM_INFO @ 13640285670 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
  UVM_INFO @ 13660285670 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
  UVM_INFO @ 23746697564 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x28
  UVM_INFO @ 23746739668 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x22

UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:103) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

46.sysrst_ctrl_stress_all_with_rand_reset.87617625512435792428562007586717294013327685563760684255291887543594742377411
Line 645, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 33927233351 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:103) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 33927233351 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:109) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 33927233351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

51.sysrst_ctrl_combo_detect_with_pre_cond.26950029600935444363559593754033768770735142051573311809192163021197235128976
Line 566, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/51.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 14447785252 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 24785114000 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x32
  UVM_INFO @ 24785215010 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x2e
  UVM_INFO @ 26238102446 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 1
  UVM_INFO @ 26252785252 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= 1a

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(6) vs exp(2) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

55.sysrst_ctrl_combo_detect_with_pre_cond.55425948289249651524413710906105215038858579595488941965854542403257001299335
Line 568, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/55.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 16280371004 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(6) vs exp(2) +/-4
  UVM_ERROR @ 16280371004 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(6) vs exp(2) +/-4
  UVM_INFO @ 16280371004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

90.sysrst_ctrl_combo_detect_with_pre_cond.55904236472288216477292529975418526136645806773665758015130717620085015460031
Line 568, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/90.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 12836693490 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(10) vs exp(5) +/-4
  UVM_ERROR @ 12836693490 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(10) vs exp(5) +/-4
  UVM_INFO @ 12836693490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---