Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.46	91.46	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	91.46	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.46	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	7	55	88.71

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	7	24	77.42	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1687

1

T22

4

T17

3

T3

56

auto[1]

548

1

T17

7

T3

40

T7

12

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1672

1

T22

3

T3

96

T7

8

auto[1]

563

1

T22

1

T17

10

T7

12

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1666

1

T22

3

T17

3

T3

89

auto[1]

569

1

T22

1

T17

7

T3

7

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1684

1

T22

4

T17

7

T3

81

auto[1]

551

1

T17

3

T3

15

T7

11

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1999

1

T22

4

T17

10

T3

87

auto[1]

236

1

T3

9

T9

26

T12

8

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2069

1

T22

4

T17

10

T3

47

auto[1]

166

1

T3

49

T64

1

T254

2

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2067

1

T22

4

T17

10

T3

72

auto[1]

168

1

T3

24

T9

7

T64

1

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2005

1

T22

3

T17

10

T3

78

auto[1]

230

1

T22

1

T3

18

T9

13

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2036

1

T22

4

T17

10

T3

89

auto[1]

199

1

T3

7

T9

2

T254

1

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1632

1

T22

4

T17

10

T3

69

auto[1]

603

1

T3

27

T7

3

T9

16

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	7	24	77.42	7
Automatically Generated Cross Bins	31	7	24	77.42	7
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	727	1			T17	3		T7	20		T30	17
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	98	1			T9	11		T12	8		T254	3
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	84	1			T105	1		T255	2		T134	4
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	18	1			T259	4		T346	6		T347	1
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	103	1			T12	20		T255	1		T288	2
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	25	1			T9	8		T345	2		T102	6
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	18	1			T254	1		T232	2		T236	6
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	1	1			T348	1		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	38	1			T260	6		T232	3		T107	1
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	4	1			T341	4		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	34	1			T257	6		T102	4		T348	2
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	5	1			T9	2		T349	2		T350	1
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	19	1			T351	2		T102	6		T352	6
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	11	1			T9	5		T346	5		T347	1
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	2	1			T353	2		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	43	1			T288	2		T341	9		T258	4
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	6	1			T258	2		T251	1		T354	2
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	7	1			T3	7		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	4	1			T242	1		T355	3		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	32	1			T3	18		T254	2		T288	2
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	4	1			T351	4		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	27	1			T3	15		T190	3		T351	1
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	14	1			T3	9		T102	5		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	4	1			T251	1		T353	1		T347	2

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

72

1

T339

9

T236

3

T231

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

68

1

T3

9

T9

5

T271

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

92

1

T3

18

T30

4

T31

8

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

136

1

T141

12

T99

10

T261

14

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

52

1

T3

15

T270

5

T342

8

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

93

1

T9

11

T30

7

T29

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

26

1

T7

3

T116

1

T267

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

75

1

T99

9

T35

1

T260

15

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

57

1

T3

7

T7

5

T141

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

57

1

T99

8

T260

15

T251

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

15

1

T341

5

T354

2

T356

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

39

1

T100

2

T339

5

T287

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

9

1

T105

1

T339

1

T119

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

20

1

T30

4

T288

2

T231

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

9

1

T119

1

T267

2

T130

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

89

1

T9

8

T12

28

T236

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

49

1

T7

4

T31

6

T270

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

49

1

T287

5

T118

3

T190

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

31

1

T287

2

T234

3

T263

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

29

1

T17

3

T7

8

T9

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

19

1

T107

1

T357

1

T358

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

12

1

T341

4

T262

1

T359

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

12

1

T30

2

T31

1

T232

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

69

1

T29

8

T35

1

T254

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

42

1

T29

4

T255

2

T100

5

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

52

1

T254

3

T45

1

T342

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

7

1

T233

1

T262

2

T356

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

18

1

T31

2

T118

1

T233

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

9

1

T134

2

T272

1

T268

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

18

1

T260

15

T103

1

T274

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

3

1

T266

1

T282

1

T103

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded