Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

999

1

T4

9

T14

10

T47

10

auto[1]

1021

1

T4

11

T14

10

T47

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

512

1

T4

8

T14

5

T47

7

from_0to1

515

1

T4

8

T14

5

T47

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

991

1

T4

8

T14

11

T47

12

auto[1]

1029

1

T4

12

T14

9

T47

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

983

1

T4

12

T14

12

T47

10

auto[1]

1037

1

T4

8

T14

8

T47

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

58

1

T4

2

T14

2

T47

1

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T60

2

T61

3

T34

1

auto[0]

from_1to0

auto[1]

auto[0]

67

1

T4

1

T14

2

T47

1

auto[0]

from_1to0

auto[1]

auto[1]

68

1

T145

1

T60

1

T304

1

auto[0]

from_0to1

auto[0]

auto[0]

73

1

T4

2

T14

2

T47

4

auto[0]

from_0to1

auto[0]

auto[1]

63

1

T14

1

T60

1

T61

1

auto[0]

from_0to1

auto[1]

auto[0]

58

1

T4

1

T145

1

T60

1

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T4

2

T14

1

T47

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T4

2

T61

2

T304

1

auto[1]

from_1to0

auto[0]

auto[1]

59

1

T47

2

T145

1

T60

1

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T4

1

T47

1

T145

3

auto[1]

from_1to0

auto[1]

auto[1]

68

1

T4

2

T14

1

T47

2

auto[1]

from_0to1

auto[0]

auto[0]

60

1

T4

1

T145

2

T61

1

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T14

1

T47

1

T60

1

auto[1]

from_0to1

auto[1]

auto[0]

67

1

T4

1

T47

1

T145

1

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T4

1

T145

1

T60

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1040

1

T4

8

T14

10

T47

14

auto[1]

980

1

T4

12

T14

10

T47

6

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

470

1

T4

4

T14

5

T47

4

from_0to1

470

1

T4

3

T14

5

T47

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1028

1

T4

11

T14

15

T47

5

auto[1]

992

1

T4

9

T14

5

T47

15

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1053

1

T4

13

T14

10

T47

11

auto[1]

967

1

T4

7

T14

10

T47

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T14

1

T60

1

T35

1

auto[0]

from_1to0

auto[0]

auto[1]

54

1

T4

1

T145

2

T61

3

auto[0]

from_1to0

auto[1]

auto[0]

71

1

T4

1

T14

1

T47

3

auto[0]

from_1to0

auto[1]

auto[1]

49

1

T145

1

T60

1

T61

1

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T14

1

T47

1

T145

1

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T14

1

T47

1

T60

1

auto[0]

from_0to1

auto[1]

auto[0]

63

1

T145

2

T61

1

T304

2

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T14

1

T47

1

T145

2

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T14

1

T145

1

T61

2

auto[1]

from_1to0

auto[0]

auto[1]

49

1

T14

1

T61

1

T304

1

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T4

1

T14

1

T47

1

auto[1]

from_1to0

auto[1]

auto[1]

55

1

T4

1

T145

1

T60

1

auto[1]

from_0to1

auto[0]

auto[0]

52

1

T4

1

T60

1

T61

1

auto[1]

from_0to1

auto[0]

auto[1]

52

1

T14

1

T145

1

T61

3

auto[1]

from_0to1

auto[1]

auto[0]

53

1

T4

1

T35

5

T45

1

auto[1]

from_0to1

auto[1]

auto[1]

53

1

T4

1

T14

1

T47

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

999

1

T4

6

T14

10

T47

7

auto[1]

1021

1

T4

14

T14

10

T47

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

497

1

T4

5

T14

5

T47

7

from_0to1

496

1

T4

4

T14

4

T47

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1025

1

T4

12

T14

12

T47

12

auto[1]

995

1

T4

8

T14

8

T47

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1002

1

T4

6

T14

9

T47

8

auto[1]

1018

1

T4

14

T14

11

T47

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T60

1

T61

2

T304

1

auto[0]

from_1to0

auto[0]

auto[1]

52

1

T14

1

T47

1

T61

1

auto[0]

from_1to0

auto[1]

auto[0]

72

1

T47

1

T145

1

T61

2

auto[0]

from_1to0

auto[1]

auto[1]

56

1

T4

1

T14

1

T61

4

auto[0]

from_0to1

auto[0]

auto[0]

56

1

T4

1

T14

1

T47

1

auto[0]

from_0to1

auto[0]

auto[1]

64

1

T47

1

T61

3

T34

2

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T61

3

T35

1

T294

1

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T14

1

T47

1

T145

1

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T47

1

T61

1

T304

3

auto[1]

from_1to0

auto[0]

auto[1]

73

1

T4

2

T14

3

T47

1

auto[1]

from_1to0

auto[1]

auto[0]

61

1

T4

1

T47

1

T145

1

auto[1]

from_1to0

auto[1]

auto[1]

56

1

T4

1

T47

2

T145

1

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T4

1

T47

1

T145

1

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T4

1

T14

1

T47

1

auto[1]

from_0to1

auto[1]

auto[0]

50

1

T4

1

T14

1

T145

1

auto[1]

from_0to1

auto[1]

auto[1]

61

1

T47

2

T60

1

T61

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1004

1

T4

7

T14

12

T47

9

auto[1]

1016

1

T4

13

T14

8

T47

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

482

1

T4

5

T14

5

T47

5

from_0to1

480

1

T4

5

T14

5

T47

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1026

1

T4

11

T14

13

T47

11

auto[1]

994

1

T4

9

T14

7

T47

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1019

1

T4

11

T14

8

T47

10

auto[1]

1001

1

T4

9

T14

12

T47

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

54

1

T14

1

T145

2

T60

1

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T14

3

T47

1

T145

1

auto[0]

from_1to0

auto[1]

auto[0]

65

1

T4

1

T14

1

T61

1

auto[0]

from_1to0

auto[1]

auto[1]

53

1

T4

1

T145

1

T34

1

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T14

1

T47

1

T61

2

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T4

1

T145

1

T60

1

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T4

2

T47

1

T145

1

auto[0]

from_0to1

auto[1]

auto[1]

63

1

T14

1

T47

1

T145

1

auto[1]

from_1to0

auto[0]

auto[0]

72

1

T4

1

T47

1

T60

2

auto[1]

from_1to0

auto[0]

auto[1]

55

1

T4

1

T47

1

T145

1

auto[1]

from_1to0

auto[1]

auto[0]

56

1

T4

1

T47

2

T145

1

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T60

1

T61

2

T34

2

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T61

1

T34

1

T45

2

auto[1]

from_0to1

auto[0]

auto[1]

52

1

T14

1

T47

2

T60

1

auto[1]

from_0to1

auto[1]

auto[0]

52

1

T4

1

T60

1

T61

1

auto[1]

from_0to1

auto[1]

auto[1]

67

1

T4

1

T14

2

T145

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

966

1

T4

7

T14

13

T47

5

auto[1]

1054

1

T4

13

T14

7

T47

15

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

479

1

T4

5

T14

6

T47

6

from_0to1

476

1

T4

5

T14

5

T47

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1030

1

T4

12

T14

10

T47

9

auto[1]

990

1

T4

8

T14

10

T47

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

988

1

T4

10

T14

11

T47

8

auto[1]

1032

1

T4

10

T14

9

T47

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T14

1

T47

1

T35

1

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T4

2

T14

1

T61

2

auto[0]

from_1to0

auto[1]

auto[0]

52

1

T34

1

T35

3

T45

1

auto[0]

from_1to0

auto[1]

auto[1]

43

1

T47

1

T145

1

T60

2

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T14

1

T45

2

T67

1

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T4

2

T14

1

T145

1

auto[0]

from_0to1

auto[1]

auto[0]

50

1

T14

1

T145

1

T61

4

auto[0]

from_0to1

auto[1]

auto[1]

48

1

T14

1

T61

1

T35

1

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T4

1

T14

1

T60

2

auto[1]

from_1to0

auto[0]

auto[1]

72

1

T4

1

T14

1

T145

1

auto[1]

from_1to0

auto[1]

auto[0]

71

1

T47

2

T145

2

T34

1

auto[1]

from_1to0

auto[1]

auto[1]

57

1

T4

1

T14

2

T47

2

auto[1]

from_0to1

auto[0]

auto[0]

59

1

T4

2

T14

1

T47

2

auto[1]

from_0to1

auto[0]

auto[1]

56

1

T47

3

T34

2

T35

3

auto[1]

from_0to1

auto[1]

auto[0]

53

1

T4

1

T61

1

T34

1

auto[1]

from_0to1

auto[1]

auto[1]

71

1

T47

1

T145

1

T60

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1018

1

T4

13

T14

11

T47

11

auto[1]

1002

1

T4

7

T14

9

T47

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

487

1

T4

6

T14

5

T47

5

from_0to1

492

1

T4

6

T14

4

T47

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

995

1

T4

8

T14

9

T47

14

auto[1]

1025

1

T4

12

T14

11

T47

6

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1018

1

T4

11

T14

11

T47

11

auto[1]

1002

1

T4

9

T14

9

T47

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T4

1

T14

3

T294

1

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T47

1

T60

1

T61

1

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T4

1

T60

1

T61

2

auto[0]

from_1to0

auto[1]

auto[1]

58

1

T14

1

T47

1

T145

3

auto[0]

from_0to1

auto[0]

auto[0]

67

1

T47

3

T60

1

T61

2

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T4

1

T14

1

T60

1

auto[0]

from_0to1

auto[1]

auto[0]

57

1

T4

1

T14

1

T47

1

auto[0]

from_0to1

auto[1]

auto[1]

63

1

T4

1

T14

1

T145

2

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T4

3

T47

1

T34

1

auto[1]

from_1to0

auto[0]

auto[1]

56

1

T145

2

T60

2

T61

1

auto[1]

from_1to0

auto[1]

auto[0]

52

1

T4

1

T145

1

T61

1

auto[1]

from_1to0

auto[1]

auto[1]

61

1

T14

1

T47

2

T145

1

auto[1]

from_0to1

auto[0]

auto[0]

48

1

T4

1

T47

1

T61

3

auto[1]

from_0to1

auto[0]

auto[1]

71

1

T14

1

T145

2

T60

1

auto[1]

from_0to1

auto[1]

auto[0]

61

1

T4

1

T145

1

T60

1

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T4

1

T60

1

T61

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1022

1

T4

7

T14

11

T47

12

auto[1]

998

1

T4

13

T14

9

T47

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

493

1

T4

5

T14

6

T47

5

from_0to1

490

1

T4

5

T14

5

T47

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1030

1

T4

7

T14

11

T47

11

auto[1]

990

1

T4

13

T14

9

T47

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1008

1

T4

11

T14

10

T47

6

auto[1]

1012

1

T4

9

T14

10

T47

14

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T14

1

T47

1

T61

1

auto[0]

from_1to0

auto[0]

auto[1]

75

1

T4

1

T14

1

T47

1

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T4

2

T14

2

T145

1

auto[0]

from_1to0

auto[1]

auto[1]

56

1

T47

1

T145

1

T60

1

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T14

1

T47

1

T61

1

auto[0]

from_0to1

auto[0]

auto[1]

59

1

T304

1

T45

1

T305

1

auto[0]

from_0to1

auto[1]

auto[0]

75

1

T4

1

T60

2

T34

1

auto[0]

from_0to1

auto[1]

auto[1]

38

1

T4

1

T47

1

T60

1

auto[1]

from_1to0

auto[0]

auto[0]

48

1

T47

1

T305

2

T67

2

auto[1]

from_1to0

auto[0]

auto[1]

63

1

T14

1

T47

1

T145

2

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T4

1

T145

1

T60

1

auto[1]

from_1to0

auto[1]

auto[1]

71

1

T4

1

T14

1

T34

1

auto[1]

from_0to1

auto[0]

auto[0]

60

1

T14

1

T47

1

T145

1

auto[1]

from_0to1

auto[0]

auto[1]

73

1

T4

1

T14

1

T145

1

auto[1]

from_0to1

auto[1]

auto[0]

56

1

T4

2

T14

2

T47

1

auto[1]

from_0to1

auto[1]

auto[1]

59

1

T47

1

T145

2

T61

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

998

1

T4

6

T14

11

T47

13

auto[1]

1022

1

T4

14

T14

9

T47

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

484

1

T4

6

T14

5

T47

5

from_0to1

471

1

T4

5

T14

6

T47

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1031

1

T4

13

T14

11

T47

9

auto[1]

989

1

T4

7

T14

9

T47

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1024

1

T4

9

T14

10

T47

11

auto[1]

996

1

T4

11

T14

10

T47

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

55

1

T14

1

T60

1

T61

2

auto[0]

from_1to0

auto[0]

auto[1]

61

1

T4

2

T47

1

T145

2

auto[0]

from_1to0

auto[1]

auto[0]

67

1

T14

1

T47

3

T60

1

auto[0]

from_1to0

auto[1]

auto[1]

54

1

T4

1

T14

1

T60

1

auto[0]

from_0to1

auto[0]

auto[0]

48

1

T61

1

T34

1

T304

1

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T14

1

T61

1

T34

1

auto[0]

from_0to1

auto[1]

auto[0]

52

1

T47

2

T145

2

T61

1

auto[0]

from_0to1

auto[1]

auto[1]

54

1

T14

1

T60

2

T34

1

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T4

3

T14

2

T304

1

auto[1]

from_1to0

auto[0]

auto[1]

51

1

T60

2

T61

1

T304

2

auto[1]

from_1to0

auto[1]

auto[0]

64

1

T47

1

T61

1

T34

1

auto[1]

from_1to0

auto[1]

auto[1]

72

1

T145

3

T61

1

T34

1

auto[1]

from_0to1

auto[0]

auto[0]

75

1

T4

3

T14

1

T145

1

auto[1]

from_0to1

auto[0]

auto[1]

59

1

T4

1

T14

1

T47

1

auto[1]

from_0to1

auto[1]

auto[0]

61

1

T14

1

T145

1

T60

1

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T4

1

T14

1

T47

1