Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	149328	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

112691

1

T4

58

T5

84

T6

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	134759	1			T4	62		T5	76		T6	2
values[0x0]	63657	1			T4	29		T5	59		T6	9
values[0x1]	63603	1			T4	32		T5	75		T6	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	121373	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

140646

1

T4

65

T5

109

T6

4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	747	1			T4	3		T22	2		T16	1
valid_sources[0x01]	689	1			T4	1		T5	1		T22	6
valid_sources[0x02]	1240	1			T5	1		T16	3		T20	1
valid_sources[0x03]	992	1			T4	2		T22	1		T16	2
valid_sources[0x04]	772	1			T4	1		T5	1		T22	1
valid_sources[0x05]	904	1			T5	1		T22	6		T47	1
valid_sources[0x06]	1183	1			T22	8		T1	1		T51	23
valid_sources[0x07]	1094	1			T5	1		T22	6		T8	1
valid_sources[0x08]	974	1			T4	1		T22	2		T14	1
valid_sources[0x09]	1046	1			T4	1		T5	1		T14	3
valid_sources[0x0a]	889	1			T16	2		T8	2		T9	14
valid_sources[0x0b]	1675	1			T16	1		T47	1		T8	1
valid_sources[0x0c]	849	1			T4	1		T22	1		T1	2
valid_sources[0x0d]	807	1			T22	8		T47	4		T9	16
valid_sources[0x0e]	707	1			T5	1		T22	13		T14	1
valid_sources[0x0f]	788	1			T4	1		T22	4		T20	1
valid_sources[0x10]	1086	1			T5	1		T8	1		T51	1
valid_sources[0x11]	934	1			T5	1		T16	8		T9	4
valid_sources[0x12]	1657	1			T5	1		T22	1		T16	4
valid_sources[0x13]	1049	1			T5	6		T22	4		T14	1
valid_sources[0x14]	936	1			T5	3		T22	3		T20	1
valid_sources[0x15]	1086	1			T22	1		T14	1		T16	2
valid_sources[0x16]	780	1			T4	1		T22	8		T16	1
valid_sources[0x17]	819	1			T5	1		T22	4		T16	2
valid_sources[0x18]	1271	1			T22	2		T16	2		T9	11
valid_sources[0x19]	1094	1			T4	1		T5	1		T14	1
valid_sources[0x1a]	1027	1			T4	1		T5	1		T22	6
valid_sources[0x1b]	1578	1			T4	2		T22	1		T16	3
valid_sources[0x1c]	999	1			T4	1		T5	3		T16	1
valid_sources[0x1d]	1717	1			T4	1		T5	2		T22	6
valid_sources[0x1e]	847	1			T4	2		T5	2		T6	17
valid_sources[0x1f]	725	1			T5	1		T16	2		T9	1
valid_sources[0x20]	836	1			T4	1		T5	4		T22	4
valid_sources[0x21]	827	1			T4	1		T16	1		T47	1
valid_sources[0x22]	1104	1			T4	2		T22	5		T1	1
valid_sources[0x23]	947	1			T16	2		T20	1		T8	3
valid_sources[0x24]	640	1			T22	5		T16	1		T12	3
valid_sources[0x25]	1102	1			T14	2		T16	1		T9	9
valid_sources[0x26]	1276	1			T16	2		T47	2		T9	5
valid_sources[0x27]	993	1			T5	1		T22	14		T16	1
valid_sources[0x28]	721	1			T22	3		T47	3		T55	3
valid_sources[0x29]	758	1			T4	1		T22	2		T16	3
valid_sources[0x2a]	742	1			T22	4		T1	1		T16	2
valid_sources[0x2b]	732	1			T5	1		T20	1		T9	1
valid_sources[0x2c]	802	1			T22	2		T16	2		T20	1
valid_sources[0x2d]	868	1			T22	10		T9	5		T51	7
valid_sources[0x2e]	970	1			T4	2		T16	4		T9	3
valid_sources[0x2f]	884	1			T22	2		T16	2		T9	8
valid_sources[0x30]	989	1			T4	1		T5	2		T14	1
valid_sources[0x31]	1308	1			T4	1		T5	2		T14	2
valid_sources[0x32]	1048	1			T4	1		T16	1		T8	2
valid_sources[0x33]	1365	1			T5	3		T22	6		T1	1
valid_sources[0x34]	1076	1			T4	1		T22	3		T2	24
valid_sources[0x35]	938	1			T5	3		T1	1		T16	1
valid_sources[0x36]	781	1			T5	1		T22	5		T1	1
valid_sources[0x37]	855	1			T16	1		T47	3		T9	4
valid_sources[0x38]	801	1			T5	4		T22	2		T14	2
valid_sources[0x39]	856	1			T22	1		T47	1		T8	1
valid_sources[0x3a]	679	1			T4	2		T22	3		T14	1
valid_sources[0x3b]	1179	1			T22	2		T16	2		T9	2
valid_sources[0x3c]	784	1			T5	3		T9	5		T51	4
valid_sources[0x3d]	856	1			T5	1		T16	4		T9	2
valid_sources[0x3e]	1051	1			T22	7		T16	4		T9	5
valid_sources[0x3f]	799	1			T22	6		T14	3		T16	1
valid_sources[0x40]	1869	1			T5	1		T22	1		T16	1
valid_sources[0x41]	917	1			T4	1		T22	7		T16	1
valid_sources[0x42]	720	1			T5	1		T1	1		T9	11
valid_sources[0x43]	985	1			T4	2		T22	3		T14	3
valid_sources[0x44]	1623	1			T22	1		T1	1		T16	3
valid_sources[0x45]	841	1			T4	1		T5	1		T22	3
valid_sources[0x46]	1633	1			T5	3		T9	1		T12	4
valid_sources[0x47]	768	1			T5	2		T22	1		T14	6
valid_sources[0x48]	1228	1			T5	1		T22	16		T15	2
valid_sources[0x49]	3016	1			T4	2		T5	2		T22	2
valid_sources[0x4a]	807	1			T22	6		T1	1		T14	2
valid_sources[0x4b]	1294	1			T5	1		T22	1		T16	2
valid_sources[0x4c]	836	1			T4	1		T20	1		T8	2
valid_sources[0x4d]	1592	1			T22	4		T16	5		T20	1
valid_sources[0x4e]	853	1			T4	1		T22	7		T14	2
valid_sources[0x4f]	1064	1			T4	1		T5	2		T14	3
valid_sources[0x50]	1055	1			T22	4		T16	3		T8	1
valid_sources[0x51]	896	1			T5	1		T22	5		T16	2
valid_sources[0x52]	803	1			T4	1		T22	2		T14	3
valid_sources[0x53]	989	1			T4	1		T22	9		T14	2
valid_sources[0x54]	2155	1			T14	2		T3	1409		T20	1
valid_sources[0x55]	942	1			T5	1		T22	8		T14	5
valid_sources[0x56]	862	1			T4	1		T22	3		T1	1
valid_sources[0x57]	1318	1			T22	6		T14	5		T16	2
valid_sources[0x58]	1429	1			T5	2		T22	3		T1	1
valid_sources[0x59]	1020	1			T4	1		T5	1		T22	1
valid_sources[0x5a]	991	1			T5	3		T14	2		T16	2
valid_sources[0x5b]	964	1			T5	2		T22	6		T16	2
valid_sources[0x5c]	757	1			T4	1		T22	6		T8	1
valid_sources[0x5d]	866	1			T5	2		T22	3		T16	2
valid_sources[0x5e]	883	1			T22	1		T47	1		T9	1
valid_sources[0x5f]	870	1			T22	11		T14	2		T20	1
valid_sources[0x60]	761	1			T5	2		T22	9		T1	1
valid_sources[0x61]	797	1			T5	4		T16	1		T11	1
valid_sources[0x62]	1101	1			T4	3		T5	3		T8	2
valid_sources[0x63]	1061	1			T4	1		T16	2		T8	1
valid_sources[0x64]	1163	1			T8	1		T9	4		T12	9
valid_sources[0x65]	1063	1			T4	1		T22	6		T20	1
valid_sources[0x66]	778	1			T14	4		T16	5		T20	1
valid_sources[0x67]	738	1			T5	1		T22	2		T20	1
valid_sources[0x68]	717	1			T22	2		T20	1		T47	2
valid_sources[0x69]	981	1			T4	1		T5	2		T22	1
valid_sources[0x6a]	855	1			T22	1		T16	3		T9	4
valid_sources[0x6b]	758	1			T16	2		T20	2		T47	1
valid_sources[0x6c]	976	1			T4	2		T5	1		T22	8
valid_sources[0x6d]	885	1			T4	1		T16	1		T47	1
valid_sources[0x6e]	699	1			T4	1		T22	4		T47	1
valid_sources[0x6f]	957	1			T5	1		T16	3		T20	1
valid_sources[0x70]	758	1			T16	2		T9	12		T12	1
valid_sources[0x71]	691	1			T4	2		T22	5		T1	1
valid_sources[0x72]	928	1			T4	1		T5	1		T22	2
valid_sources[0x73]	1048	1			T5	1		T22	5		T9	9
valid_sources[0x74]	896	1			T4	2		T5	1		T22	5
valid_sources[0x75]	837	1			T22	2		T1	1		T16	2
valid_sources[0x76]	799	1			T5	1		T16	3		T8	1
valid_sources[0x77]	917	1			T4	1		T5	1		T22	7
valid_sources[0x78]	1107	1			T4	2		T5	4		T16	3
valid_sources[0x79]	890	1			T5	1		T14	1		T8	1
valid_sources[0x7a]	930	1			T9	4		T51	2		T145	1
valid_sources[0x7b]	935	1			T4	1		T22	17		T16	4
valid_sources[0x7c]	816	1			T4	1		T22	8		T16	7
valid_sources[0x7d]	1086	1			T22	6		T48	6		T8	1
valid_sources[0x7e]	1138	1			T5	1		T16	2		T20	1
valid_sources[0x7f]	851	1			T4	1		T5	2		T16	3
valid_sources[0x80]	1651	1			T5	1		T1	1		T16	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

61126

1

T4

36

T5

43

T21

15

values[0x0]

all_enables

biggest_size

30331

1

T4

11

T5

25

T6

3

values[0x1]

all_enables

biggest_size

21234

1

T4

11

T5

16

T22

51