Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1271962318	9672	0	0
auto_block_debounce_ctl_rd_A	1271962318	1554	0	0
auto_block_out_ctl_rd_A	1271962318	2052	0	0
com_det_ctl_0_rd_A	1271962318	3249	0	0
com_det_ctl_1_rd_A	1271962318	3265	0	0
com_det_ctl_2_rd_A	1271962318	3239	0	0
com_det_ctl_3_rd_A	1271962318	3186	0	0
com_out_ctl_0_rd_A	1271962318	3682	0	0
com_out_ctl_1_rd_A	1271962318	3736	0	0
com_out_ctl_2_rd_A	1271962318	3629	0	0
com_out_ctl_3_rd_A	1271962318	3617	0	0
com_pre_det_ctl_0_rd_A	1271962318	1204	0	0
com_pre_det_ctl_1_rd_A	1271962318	1202	0	0
com_pre_det_ctl_2_rd_A	1271962318	1311	0	0
com_pre_det_ctl_3_rd_A	1271962318	1321	0	0
com_pre_sel_ctl_0_rd_A	1271962318	3767	0	0
com_pre_sel_ctl_1_rd_A	1271962318	3661	0	0
com_pre_sel_ctl_2_rd_A	1271962318	3636	0	0
com_pre_sel_ctl_3_rd_A	1271962318	3833	0	0
com_sel_ctl_0_rd_A	1271962318	3873	0	0
com_sel_ctl_1_rd_A	1271962318	3832	0	0
com_sel_ctl_2_rd_A	1271962318	3905	0	0
com_sel_ctl_3_rd_A	1271962318	3692	0	0
ec_rst_ctl_rd_A	1271962318	2132	0	0
intr_enable_rd_A	1271962318	1842	0	0
key_intr_ctl_rd_A	1271962318	3371	0	0
key_intr_debounce_ctl_rd_A	1271962318	1271	0	0
key_invert_ctl_rd_A	1271962318	4284	0	0
pin_allowed_ctl_rd_A	1271962318	4503	0	0
pin_out_ctl_rd_A	1271962318	3380	0	0
pin_out_value_rd_A	1271962318	3445	0	0
regwen_rd_A	1271962318	1481	0	0
ulp_ac_debounce_ctl_rd_A	1271962318	1394	0	0
ulp_ctl_rd_A	1271962318	1421	0	0
ulp_lid_debounce_ctl_rd_A	1271962318	1381	0	0
ulp_pwrb_debounce_ctl_rd_A	1271962318	1520	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271962318	9672	0	0
T2	125378	3	0	0
T3	176486	0	0	0
T7	876480	0	0	0
T8	892722	0	0	0
T9	223487	0	0	0
T10	924668	0	0	0
T11	70646	0	0	0
T20	65958	0	0	0
T34	0	16	0	0
T35	0	7	0	0
T45	0	7	0	0
T47	30690	0	0	0
T48	250808	0	0	0
T67	0	7	0	0
T78	0	11	0	0
T86	0	8	0	0
T172	0	18	0	0
T231	0	24	0	0
T282	0	6	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271962318	1554	0	0
T1	249683	0	0	0
T5	378610	15	0	0
T6	50763	0	0	0
T14	130788	0	0	0
T15	195407	0	0	0
T16	859945	0	0	0
T17	331649	0	0	0
T18	172960	4	0	0
T21	598405	0	0	0
T22	475776	0	0	0
T35	0	17	0	0
T78	0	46	0	0
T116	0	16	0	0
T139	0	13	0	0
T283	0	5	0	0
T284	0	8	0	0
T285	0	14	0	0
T286	0	14	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271962318	2052	0	0
T1	249683	0	0	0
T5	378610	7	0	0
T6	50763	0	0	0
T14	130788	0	0	0
T15	195407	0	0	0
T16	859945	0	0	0
T17	331649	0	0	0
T18	172960	11	0	0
T21	598405	0	0	0
T22	475776	0	0	0
T35	0	32	0	0
T78	0	34	0	0
T116	0	4	0	0
T139	0	13	0	0
T283	0	16	0	0
T284	0	5	0	0
T285	0	15	0	0
T286	0	8	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271962318	3249	0	0
T2	125378	0	0	0
T3	176486	108	0	0
T7	876480	0	0	0
T8	892722	0	0	0
T17	331649	37	0	0
T18	172960	0	0	0
T19	132889	0	0	0
T20	65958	0	0	0
T35	0	42	0	0
T47	30690	0	0	0
T48	250808	0	0	0
T64	0	54	0	0
T99	0	74	0	0
T116	0	67	0	0
T141	0	60	0	0
T271	0	41	0	0
T287	0	50	0	0
T288	0	34	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271962318	3265	0	0
T2	125378	0	0	0
T3	176486	90	0	0
T7	876480	0	0	0
T8	892722	0	0	0
T17	331649	47	0	0
T18	172960	0	0	0
T19	132889	0	0	0
T20	65958	0	0	0
T35	0	45	0	0
T47	30690	0	0	0
T48	250808	0	0	0
T64	0	40	0	0
T99	0	61	0	0
T116	0	63	0	0
T141	0	70	0	0
T271	0	49	0	0
T287	0	40	0	0
T288	0	49	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271962318	3239	0	0
T2	125378	0	0	0
T3	176486	93	0	0
T7	876480	0	0	0
T8	892722	0	0	0
T17	331649	37	0	0
T18	172960	0	0	0
T19	132889	0	0	0
T20	65958	0	0	0
T35	0	37	0	0
T47	30690	0	0	0
T48	250808	0	0	0
T64	0	25	0	0
T99	0	76	0	0
T116	0	71	0	0
T141	0	93	0	0
T271	0	67	0	0
T287	0	36	0	0
T288	0	45	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271962318	3186	0	0
T2	125378	0	0	0
T3	176486	100	0	0
T7	876480	0	0	0
T8	892722	0	0	0
T17	331649	43	0	0
T18	172960	0	0	0
T19	132889	0	0	0
T20	65958	0	0	0
T35	0	35	0	0
T47	30690	0	0	0
T48	250808	0	0	0
T64	0	63	0	0
T99	0	55	0	0
T116	0	73	0	0
T141	0	68	0	0
T271	0	46	0	0
T287	0	45	0	0
T288	0	33	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271962318	3682	0	0
T2	125378	0	0	0
T3	176486	105	0	0
T7	876480	0	0	0
T8	892722	0	0	0
T17	331649	48	0	0
T18	172960	0	0	0
T19	132889	0	0	0
T20	65958	0	0	0
T35	0	78	0	0
T47	30690	0	0	0
T48	250808	0	0	0
T64	0	52	0	0
T99	0	52	0	0
T116	0	77	0	0
T141	0	72	0	0
T271	0	52	0	0
T287	0	51	0	0
T288	0	39	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271962318	3736	0	0
T2	125378	0	0	0
T3	176486	87	0	0
T7	876480	0	0	0
T8	892722	0	0	0
T17	331649	43	0	0
T18	172960	0	0	0
T19	132889	0	0	0
T20	65958	0	0	0
T35	0	39	0	0
T47	30690	0	0	0
T48	250808	0	0	0
T64	0	36	0	0
T99	0	82	0	0
T116	0	85	0	0
T141	0	71	0	0
T271	0	56	0	0
T287	0	32	0	0
T288	0	36	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271962318	3629	0	0
T2	125378	0	0	0
T3	176486	89	0	0
T7	876480	0	0	0
T8	892722	0	0	0
T17	331649	49	0	0
T18	172960	0	0	0
T19	132889	0	0	0
T20	65958	0	0	0
T35	0	56	0	0
T47	30690	0	0	0
T48	250808	0	0	0
T64	0	42	0	0
T99	0	62	0	0
T116	0	77	0	0
T141	0	67	0	0
T271	0	56	0	0
T287	0	28	0	0
T288	0	56	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271962318	3617	0	0
T2	125378	0	0	0
T3	176486	87	0	0
T7	876480	0	0	0
T8	892722	0	0	0
T17	331649	34	0	0
T18	172960	0	0	0
T19	132889	0	0	0
T20	65958	0	0	0
T35	0	37	0	0
T47	30690	0	0	0
T48	250808	0	0	0
T64	0	37	0	0
T99	0	76	0	0
T116	0	87	0	0
T141	0	44	0	0
T271	0	62	0	0
T287	0	42	0	0
T288	0	55	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271962318	1204	0	0
T24	0	2	0	0
T35	243891	10	0	0
T78	0	22	0	0
T81	0	10	0	0
T117	130033	0	0	0
T147	0	25	0	0
T148	0	20	0	0
T222	0	11	0	0
T265	0	15	0	0
T289	0	28	0	0
T290	0	6	0	0
T291	261292	0	0	0
T292	201244	0	0	0
T293	94595	0	0	0
T294	25763	0	0	0
T295	73359	0	0	0
T296	180311	0	0	0
T297	144212	0	0	0
T298	65180	0	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271962318	1202	0	0
T24	0	4	0	0
T35	243891	7	0	0
T78	0	24	0	0
T81	0	8	0	0
T117	130033	0	0	0
T147	0	30	0	0
T148	0	38	0	0
T222	0	14	0	0
T265	0	22	0	0
T289	0	22	0	0
T290	0	30	0	0
T291	261292	0	0	0
T292	201244	0	0	0
T293	94595	0	0	0
T294	25763	0	0	0
T295	73359	0	0	0
T296	180311	0	0	0
T297	144212	0	0	0
T298	65180	0	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271962318	1311	0	0
T25	0	34	0	0
T35	243891	16	0	0
T78	0	34	0	0
T81	0	13	0	0
T117	130033	0	0	0
T147	0	46	0	0
T148	0	37	0	0
T222	0	11	0	0
T265	0	18	0	0
T289	0	22	0	0
T290	0	15	0	0
T291	261292	0	0	0
T292	201244	0	0	0
T293	94595	0	0	0
T294	25763	0	0	0
T295	73359	0	0	0
T296	180311	0	0	0
T297	144212	0	0	0
T298	65180	0	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271962318	1321	0	0
T25	0	29	0	0
T35	243891	19	0	0
T78	0	33	0	0
T81	0	4	0	0
T117	130033	0	0	0
T147	0	28	0	0
T148	0	37	0	0
T222	0	11	0	0
T265	0	17	0	0
T289	0	25	0	0
T290	0	30	0	0
T291	261292	0	0	0
T292	201244	0	0	0
T293	94595	0	0	0
T294	25763	0	0	0
T295	73359	0	0	0
T296	180311	0	0	0
T297	144212	0	0	0
T298	65180	0	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271962318	3767	0	0
T2	125378	0	0	0
T3	176486	103	0	0
T7	876480	0	0	0
T8	892722	0	0	0
T17	331649	39	0	0
T18	172960	0	0	0
T19	132889	0	0	0
T20	65958	0	0	0
T35	0	37	0	0
T47	30690	0	0	0
T48	250808	0	0	0
T64	0	53	0	0
T99	0	63	0	0
T116	0	70	0	0
T141	0	58	0	0
T271	0	51	0	0
T287	0	47	0	0
T288	0	40	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271962318	3661	0	0
T2	125378	0	0	0
T3	176486	93	0	0
T7	876480	0	0	0
T8	892722	0	0	0
T17	331649	41	0	0
T18	172960	0	0	0
T19	132889	0	0	0
T20	65958	0	0	0
T35	0	47	0	0
T47	30690	0	0	0
T48	250808	0	0	0
T64	0	34	0	0
T99	0	84	0	0
T116	0	45	0	0
T141	0	54	0	0
T271	0	54	0	0
T287	0	53	0	0
T288	0	49	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271962318	3636	0	0
T2	125378	0	0	0
T3	176486	98	0	0
T7	876480	0	0	0
T8	892722	0	0	0
T17	331649	53	0	0
T18	172960	0	0	0
T19	132889	0	0	0
T20	65958	0	0	0
T35	0	45	0	0
T47	30690	0	0	0
T48	250808	0	0	0
T64	0	45	0	0
T99	0	48	0	0
T116	0	67	0	0
T141	0	68	0	0
T271	0	59	0	0
T287	0	17	0	0
T288	0	33	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271962318	3833	0	0
T2	125378	0	0	0
T3	176486	98	0	0
T7	876480	0	0	0
T8	892722	0	0	0
T17	331649	36	0	0
T18	172960	0	0	0
T19	132889	0	0	0
T20	65958	0	0	0
T35	0	42	0	0
T47	30690	0	0	0
T48	250808	0	0	0
T64	0	46	0	0
T99	0	76	0	0
T116	0	69	0	0
T141	0	73	0	0
T271	0	64	0	0
T287	0	33	0	0
T288	0	34	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271962318	3873	0	0
T2	125378	0	0	0
T3	176486	112	0	0
T7	876480	0	0	0
T8	892722	0	0	0
T17	331649	51	0	0
T18	172960	0	0	0
T19	132889	0	0	0
T20	65958	0	0	0
T35	0	52	0	0
T47	30690	0	0	0
T48	250808	0	0	0
T64	0	49	0	0
T99	0	64	0	0
T116	0	78	0	0
T141	0	53	0	0
T271	0	50	0	0
T287	0	37	0	0
T288	0	27	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271962318	3832	0	0
T2	125378	0	0	0
T3	176486	97	0	0
T7	876480	0	0	0
T8	892722	0	0	0
T17	331649	38	0	0
T18	172960	0	0	0
T19	132889	0	0	0
T20	65958	0	0	0
T35	0	45	0	0
T47	30690	0	0	0
T48	250808	0	0	0
T64	0	55	0	0
T99	0	56	0	0
T116	0	70	0	0
T141	0	80	0	0
T271	0	54	0	0
T287	0	66	0	0
T288	0	27	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271962318	3905	0	0
T2	125378	0	0	0
T3	176486	93	0	0
T7	876480	0	0	0
T8	892722	0	0	0
T17	331649	47	0	0
T18	172960	0	0	0
T19	132889	0	0	0
T20	65958	0	0	0
T35	0	43	0	0
T47	30690	0	0	0
T48	250808	0	0	0
T64	0	45	0	0
T99	0	90	0	0
T116	0	94	0	0
T141	0	53	0	0
T271	0	35	0	0
T287	0	65	0	0
T288	0	29	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271962318	3692	0	0
T2	125378	0	0	0
T3	176486	89	0	0
T7	876480	0	0	0
T8	892722	0	0	0
T17	331649	56	0	0
T18	172960	0	0	0
T19	132889	0	0	0
T20	65958	0	0	0
T35	0	37	0	0
T47	30690	0	0	0
T48	250808	0	0	0
T64	0	30	0	0
T99	0	70	0	0
T116	0	73	0	0
T141	0	94	0	0
T271	0	71	0	0
T287	0	79	0	0
T288	0	48	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271962318	2132	0	0
T2	125378	0	0	0
T3	176486	47	0	0
T7	876480	0	0	0
T8	892722	0	0	0
T10	0	2	0	0
T17	331649	4	0	0
T18	172960	0	0	0
T19	132889	0	0	0
T20	65958	0	0	0
T35	0	49	0	0
T47	30690	0	0	0
T48	250808	0	0	0
T50	0	9	0	0
T64	0	3	0	0
T99	0	31	0	0
T141	0	50	0	0
T202	0	2	0	0
T299	0	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271962318	1842	0	0
T1	249683	0	0	0
T5	378610	26	0	0
T6	50763	0	0	0
T14	130788	0	0	0
T15	195407	0	0	0
T16	859945	0	0	0
T17	331649	0	0	0
T18	172960	0	0	0
T21	598405	0	0	0
T22	475776	0	0	0
T35	0	63	0	0
T78	0	11	0	0
T147	0	59	0	0
T148	0	93	0	0
T179	0	10	0	0
T265	0	40	0	0
T283	0	31	0	0
T289	0	14	0	0
T300	0	37	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271962318	3371	0	0
T10	924668	4	0	0
T11	70646	1	0	0
T26	27891	0	0	0
T35	0	15	0	0
T39	889480	0	0	0
T50	288473	0	0	0
T51	247667	0	0	0
T55	237377	0	0	0
T78	0	13	0	0
T87	193438	0	0	0
T135	0	9	0	0
T145	48173	0	0	0
T162	30542	0	0	0
T170	0	5	0	0
T181	0	2	0	0
T184	0	7	0	0
T187	0	2	0	0
T204	0	7	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271962318	1271	0	0
T25	0	46	0	0
T35	243891	23	0	0
T78	0	14	0	0
T81	0	6	0	0
T117	130033	0	0	0
T147	0	45	0	0
T148	0	33	0	0
T222	0	12	0	0
T265	0	10	0	0
T289	0	15	0	0
T290	0	15	0	0
T291	261292	0	0	0
T292	201244	0	0	0
T293	94595	0	0	0
T294	25763	0	0	0
T295	73359	0	0	0
T296	180311	0	0	0
T297	144212	0	0	0
T298	65180	0	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271962318	4284	0	0
T1	249683	0	0	0
T5	378610	155	0	0
T6	50763	0	0	0
T10	0	88	0	0
T14	130788	0	0	0
T15	195407	0	0	0
T16	859945	0	0	0
T17	331649	0	0	0
T18	172960	0	0	0
T21	598405	0	0	0
T22	475776	0	0	0
T35	0	29	0	0
T57	0	65	0	0
T59	0	62	0	0
T78	0	111	0	0
T224	0	68	0	0
T301	0	61	0	0
T302	0	61	0	0
T303	0	55	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271962318	4503	0	0
T1	249683	0	0	0
T4	43358	28	0	0
T5	378610	0	0	0
T6	50763	0	0	0
T14	130788	0	0	0
T15	195407	0	0	0
T16	859945	0	0	0
T17	331649	0	0	0
T21	598405	0	0	0
T22	475776	0	0	0
T35	0	165	0	0
T78	0	10	0	0
T179	0	39	0	0
T304	0	53	0	0
T305	0	77	0	0
T306	0	89	0	0
T307	0	74	0	0
T308	0	79	0	0
T309	0	25	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271962318	3380	0	0
T1	249683	0	0	0
T4	43358	21	0	0
T5	378610	0	0	0
T6	50763	0	0	0
T14	130788	0	0	0
T15	195407	0	0	0
T16	859945	0	0	0
T17	331649	0	0	0
T21	598405	0	0	0
T22	475776	0	0	0
T35	0	145	0	0
T78	0	14	0	0
T179	0	37	0	0
T304	0	56	0	0
T305	0	69	0	0
T306	0	70	0	0
T307	0	56	0	0
T308	0	79	0	0
T309	0	21	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271962318	3445	0	0
T1	249683	0	0	0
T4	43358	54	0	0
T5	378610	0	0	0
T6	50763	0	0	0
T14	130788	0	0	0
T15	195407	0	0	0
T16	859945	0	0	0
T17	331649	0	0	0
T21	598405	0	0	0
T22	475776	0	0	0
T35	0	143	0	0
T78	0	16	0	0
T179	0	49	0	0
T304	0	36	0	0
T305	0	53	0	0
T306	0	75	0	0
T307	0	99	0	0
T308	0	85	0	0
T309	0	29	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271962318	1481	0	0
T25	0	18	0	0
T35	243891	29	0	0
T78	0	25	0	0
T81	0	18	0	0
T117	130033	0	0	0
T147	0	28	0	0
T148	0	31	0	0
T222	0	11	0	0
T265	0	16	0	0
T289	0	36	0	0
T290	0	27	0	0
T291	261292	0	0	0
T292	201244	0	0	0
T293	94595	0	0	0
T294	25763	0	0	0
T295	73359	0	0	0
T296	180311	0	0	0
T297	144212	0	0	0
T298	65180	0	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271962318	1394	0	0
T10	924668	3	0	0
T11	70646	0	0	0
T26	27891	0	0	0
T35	0	29	0	0
T39	889480	0	0	0
T50	288473	0	0	0
T51	247667	0	0	0
T52	0	1	0	0
T55	237377	0	0	0
T65	0	18	0	0
T78	0	12	0	0
T87	193438	0	0	0
T144	0	13	0	0
T145	48173	0	0	0
T162	30542	0	0	0
T163	0	4	0	0
T305	0	4	0	0
T310	0	6	0	0
T311	0	6	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271962318	1421	0	0
T10	924668	9	0	0
T11	70646	0	0	0
T26	27891	0	0	0
T35	0	24	0	0
T39	889480	0	0	0
T50	288473	0	0	0
T51	247667	0	0	0
T53	0	9	0	0
T55	237377	0	0	0
T65	0	17	0	0
T78	0	25	0	0
T87	193438	0	0	0
T144	0	11	0	0
T145	48173	0	0	0
T162	30542	0	0	0
T163	0	6	0	0
T305	0	4	0	0
T310	0	3	0	0
T311	0	4	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271962318	1381	0	0
T10	924668	10	0	0
T11	70646	0	0	0
T26	27891	0	0	0
T35	0	39	0	0
T39	889480	0	0	0
T50	288473	0	0	0
T51	247667	0	0	0
T52	0	2	0	0
T53	0	6	0	0
T55	237377	0	0	0
T65	0	9	0	0
T78	0	10	0	0
T87	193438	0	0	0
T145	48173	0	0	0
T162	30542	0	0	0
T163	0	3	0	0
T305	0	8	0	0
T310	0	3	0	0
T311	0	7	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271962318	1520	0	0
T10	924668	8	0	0
T11	70646	0	0	0
T26	27891	0	0	0
T35	0	35	0	0
T39	889480	0	0	0
T50	288473	0	0	0
T51	247667	0	0	0
T52	0	3	0	0
T53	0	9	0	0
T55	237377	0	0	0
T65	0	8	0	0
T78	0	32	0	0
T87	193438	0	0	0
T145	48173	0	0	0
T162	30542	0	0	0
T163	0	4	0	0
T305	0	1	0	0
T310	0	1	0	0
T311	0	9	0	0