Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.76	100.00	90.48		100.00	100.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.76	100.00	90.48		100.00	100.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T14,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T14,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T14,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T8,T9
1	0	Covered	T4,T5,T1
1	1	Covered	T14,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T8,T9
0	1	Covered	T119,T135
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T8,T58
0	1	Covered	T14,T8,T9
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T8,T58
1	-	Covered	T14,T8,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T8,T9
DetectSt	168	Covered	T14,T8,T9
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T14,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T8,T9
DebounceSt->IdleSt	163	Covered	T8,T9,T56
DetectSt->IdleSt	186	Covered	T119,T135
DetectSt->StableSt	191	Covered	T14,T8,T9
IdleSt->DebounceSt	148	Covered	T14,T8,T9
StableSt->IdleSt	206	Covered	T14,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T8,T9
0	1	Covered	T14,T8,T9
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T8,T9
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T116
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T9,T56
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T8,T9
DetectSt	-	-	-	-	1	-	-	Covered	T119,T135
DetectSt	-	-	-	-	0	1	-	Covered	T14,T8,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T8,T9
StableSt	-	-	-	-	-	-	0	Covered	T14,T8,T58
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8955184	284	0	0
CntIncr_A	8955184	200862	0	0
CntNoWrap_A	8955184	8306697	0	0
DetectStDropOut_A	8955184	2	0	0
DetectedOut_A	8955184	878	0	0
DetectedPulseOut_A	8955184	129	0	0
DisabledIdleSt_A	8955184	8099457	0	0
DisabledNoDetection_A	8955184	8101777	0	0
EnterDebounceSt_A	8955184	162	0	0
EnterDetectSt_A	8955184	131	0	0
EnterStableSt_A	8955184	129	0	0
PulseIsPulse_A	8955184	129	0	0
StayInStableSt	8955184	748	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8955184	6852	0	0
gen_low_level_sva.LowLevelEvent_A	8955184	8309358	0	0
gen_not_sticky_sva.StableStDropOut_A	8955184	128	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	284	0	0
T2	788	0	0	0
T3	38319	0	0	0
T8	0	7	0	0
T9	0	4	0	0
T14	719	2	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T19	523	0	0	0
T25	494	0	0	0
T27	522	0	0	0
T56	0	1	0	0
T58	0	2	0	0
T60	0	5	0	0
T61	0	13	0	0
T62	0	2	0	0
T128	0	2	0	0
T129	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	200862	0	0
T2	788	0	0	0
T3	38319	0	0	0
T8	0	198	0	0
T9	0	152	0	0
T14	719	44	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T19	523	0	0	0
T25	494	0	0	0
T27	522	0	0	0
T56	0	83	0	0
T58	0	60	0	0
T60	0	130	0	0
T61	0	441	0	0
T62	0	56	0	0
T128	0	28	0	0
T129	0	72	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8306697	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	316	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	2	0	0
T87	18561	0	0	0
T119	710	1	0	0
T130	5166	0	0	0
T135	0	1	0	0
T145	405	0	0	0
T146	522	0	0	0
T147	502	0	0	0
T148	506	0	0	0
T149	437	0	0	0
T150	506	0	0	0
T151	686	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	878	0	0
T2	788	0	0	0
T3	38319	0	0	0
T8	0	27	0	0
T9	0	1	0	0
T14	719	9	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T19	523	0	0	0
T25	494	0	0	0
T27	522	0	0	0
T58	0	10	0	0
T60	0	7	0	0
T61	0	47	0	0
T62	0	8	0	0
T128	0	12	0	0
T152	0	2	0	0
T153	0	7	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	129	0	0
T2	788	0	0	0
T3	38319	0	0	0
T8	0	3	0	0
T9	0	1	0	0
T14	719	1	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T19	523	0	0	0
T25	494	0	0	0
T27	522	0	0	0
T58	0	1	0	0
T60	0	2	0	0
T61	0	6	0	0
T62	0	1	0	0
T128	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8099457	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	223	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8101777	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	223	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	162	0	0
T2	788	0	0	0
T3	38319	0	0	0
T8	0	4	0	0
T9	0	3	0	0
T14	719	1	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T19	523	0	0	0
T25	494	0	0	0
T27	522	0	0	0
T56	0	1	0	0
T58	0	1	0	0
T60	0	3	0	0
T61	0	7	0	0
T62	0	1	0	0
T128	0	1	0	0
T129	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	131	0	0
T2	788	0	0	0
T3	38319	0	0	0
T8	0	3	0	0
T9	0	1	0	0
T14	719	1	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T19	523	0	0	0
T25	494	0	0	0
T27	522	0	0	0
T58	0	1	0	0
T60	0	2	0	0
T61	0	6	0	0
T62	0	1	0	0
T128	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	129	0	0
T2	788	0	0	0
T3	38319	0	0	0
T8	0	3	0	0
T9	0	1	0	0
T14	719	1	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T19	523	0	0	0
T25	494	0	0	0
T27	522	0	0	0
T58	0	1	0	0
T60	0	2	0	0
T61	0	6	0	0
T62	0	1	0	0
T128	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	129	0	0
T2	788	0	0	0
T3	38319	0	0	0
T8	0	3	0	0
T9	0	1	0	0
T14	719	1	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T19	523	0	0	0
T25	494	0	0	0
T27	522	0	0	0
T58	0	1	0	0
T60	0	2	0	0
T61	0	6	0	0
T62	0	1	0	0
T128	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	748	0	0
T2	788	0	0	0
T3	38319	0	0	0
T8	0	24	0	0
T14	719	8	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T19	523	0	0	0
T25	494	0	0	0
T27	522	0	0	0
T58	0	9	0	0
T60	0	5	0	0
T61	0	41	0	0
T62	0	7	0	0
T128	0	11	0	0
T152	0	1	0	0
T153	0	6	0	0
T154	0	17	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	6852	0	0
T1	8953	10	0	0
T2	788	4	0	0
T3	38319	12	0	0
T5	38517	17	0	0
T13	402	0	0	0
T14	719	3	0	0
T15	2162	9	0	0
T16	426	3	0	0
T17	454	6	0	0
T18	404	0	0	0
T19	0	6	0	0
T25	0	8	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8309358	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	128	0	0
T2	788	0	0	0
T3	38319	0	0	0
T8	0	3	0	0
T9	0	1	0	0
T14	719	1	0	0
T15	2162	0	0	0
T16	426	0	0	0
T17	454	0	0	0
T18	404	0	0	0
T19	523	0	0	0
T25	494	0	0	0
T27	522	0	0	0
T58	0	1	0	0
T60	0	2	0	0
T61	0	6	0	0
T62	0	1	0	0
T128	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T8,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T8,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T8,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T24
1	0	Covered	T4,T5,T1
1	1	Covered	T2,T8,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T24,T77
0	1	Covered	T2,T90,T126
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T24,T77
0	1	Unreachable
1	0	Covered	T8,T24,T77

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T8,T24
DetectSt	168	Covered	T2,T8,T24
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T8,T24,T77

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T8,T24
DebounceSt->IdleSt	163	Covered	T8,T90,T93
DetectSt->IdleSt	186	Covered	T2,T90,T126
DetectSt->StableSt	191	Covered	T8,T24,T77
IdleSt->DebounceSt	148	Covered	T2,T8,T24
StableSt->IdleSt	206	Covered	T8,T24,T77

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T8,T24
0	1	Covered	T2,T8,T24
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T24
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T8,T24
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T116
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T8,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T90,T93
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T8,T24
DetectSt	-	-	-	-	1	-	-	Covered	T2,T90,T126
DetectSt	-	-	-	-	0	1	-	Covered	T8,T24,T77
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T24,T77
StableSt	-	-	-	-	-	-	0	Covered	T8,T24,T77
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8955184	141	0	0
CntIncr_A	8955184	187664	0	0
CntNoWrap_A	8955184	8306840	0	0
DetectStDropOut_A	8955184	13	0	0
DetectedOut_A	8955184	823429	0	0
DetectedPulseOut_A	8955184	42	0	0
DisabledIdleSt_A	8955184	5479430	0	0
DisabledNoDetection_A	8955184	5481804	0	0
EnterDebounceSt_A	8955184	88	0	0
EnterDetectSt_A	8955184	55	0	0
EnterStableSt_A	8955184	42	0	0
PulseIsPulse_A	8955184	42	0	0
StayInStableSt	8955184	823387	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8955184	6852	0	0
gen_low_level_sva.LowLevelEvent_A	8955184	8309358	0	0
gen_sticky_sva.StableStDropOut_A	8955184	607326	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	141	0	0
T2	788	2	0	0
T3	38319	0	0	0
T6	659	0	0	0
T8	0	5	0	0
T18	404	0	0	0
T19	523	0	0	0
T24	0	2	0	0
T25	494	0	0	0
T26	495	0	0	0
T27	522	0	0	0
T34	656	0	0	0
T77	0	2	0	0
T81	502	0	0	0
T89	0	4	0	0
T90	0	11	0	0
T91	0	2	0	0
T92	0	4	0	0
T93	0	1	0	0
T94	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	187664	0	0
T2	788	57	0	0
T3	38319	0	0	0
T6	659	0	0	0
T8	0	245	0	0
T18	404	0	0	0
T19	523	0	0	0
T24	0	44200	0	0
T25	494	0	0	0
T26	495	0	0	0
T27	522	0	0	0
T34	656	0	0	0
T77	0	19	0	0
T81	502	0	0	0
T89	0	172	0	0
T90	0	336	0	0
T91	0	32	0	0
T92	0	29	0	0
T93	0	58	0	0
T94	0	194	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8306840	0	0
T1	8953	8545	0	0
T2	788	385	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	13	0	0
T2	788	1	0	0
T3	38319	0	0	0
T6	659	0	0	0
T18	404	0	0	0
T19	523	0	0	0
T25	494	0	0	0
T26	495	0	0	0
T27	522	0	0	0
T34	656	0	0	0
T81	502	0	0	0
T90	0	3	0	0
T126	0	3	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	823429	0	0
T8	18107	87	0	0
T9	12144	0	0	0
T10	32256	0	0	0
T24	0	201448	0	0
T71	319237	0	0	0
T72	750	0	0	0
T77	0	144	0	0
T78	495	0	0	0
T82	422	0	0	0
T89	0	451	0	0
T90	0	99	0	0
T91	0	65	0	0
T92	0	63	0	0
T94	0	293	0	0
T108	404	0	0	0
T115	0	455	0	0
T143	409	0	0	0
T144	402	0	0	0
T156	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	42	0	0
T8	18107	1	0	0
T9	12144	0	0	0
T10	32256	0	0	0
T24	0	1	0	0
T71	319237	0	0	0
T72	750	0	0	0
T77	0	1	0	0
T78	495	0	0	0
T82	422	0	0	0
T89	0	2	0	0
T90	0	1	0	0
T91	0	1	0	0
T92	0	2	0	0
T94	0	1	0	0
T108	404	0	0	0
T115	0	2	0	0
T143	409	0	0	0
T144	402	0	0	0
T156	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	5479430	0	0
T1	8953	8545	0	0
T2	788	281	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	5481804	0	0
T1	8953	8547	0	0
T2	788	282	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	88	0	0
T2	788	1	0	0
T3	38319	0	0	0
T6	659	0	0	0
T8	0	4	0	0
T18	404	0	0	0
T19	523	0	0	0
T24	0	1	0	0
T25	494	0	0	0
T26	495	0	0	0
T27	522	0	0	0
T34	656	0	0	0
T77	0	1	0	0
T81	502	0	0	0
T89	0	2	0	0
T90	0	7	0	0
T91	0	1	0	0
T92	0	2	0	0
T93	0	1	0	0
T94	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	55	0	0
T2	788	1	0	0
T3	38319	0	0	0
T6	659	0	0	0
T8	0	1	0	0
T18	404	0	0	0
T19	523	0	0	0
T24	0	1	0	0
T25	494	0	0	0
T26	495	0	0	0
T27	522	0	0	0
T34	656	0	0	0
T77	0	1	0	0
T81	502	0	0	0
T89	0	2	0	0
T90	0	4	0	0
T91	0	1	0	0
T92	0	2	0	0
T94	0	1	0	0
T156	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	42	0	0
T8	18107	1	0	0
T9	12144	0	0	0
T10	32256	0	0	0
T24	0	1	0	0
T71	319237	0	0	0
T72	750	0	0	0
T77	0	1	0	0
T78	495	0	0	0
T82	422	0	0	0
T89	0	2	0	0
T90	0	1	0	0
T91	0	1	0	0
T92	0	2	0	0
T94	0	1	0	0
T108	404	0	0	0
T115	0	2	0	0
T143	409	0	0	0
T144	402	0	0	0
T156	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	42	0	0
T8	18107	1	0	0
T9	12144	0	0	0
T10	32256	0	0	0
T24	0	1	0	0
T71	319237	0	0	0
T72	750	0	0	0
T77	0	1	0	0
T78	495	0	0	0
T82	422	0	0	0
T89	0	2	0	0
T90	0	1	0	0
T91	0	1	0	0
T92	0	2	0	0
T94	0	1	0	0
T108	404	0	0	0
T115	0	2	0	0
T143	409	0	0	0
T144	402	0	0	0
T156	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	823387	0	0
T8	18107	86	0	0
T9	12144	0	0	0
T10	32256	0	0	0
T24	0	201447	0	0
T71	319237	0	0	0
T72	750	0	0	0
T77	0	143	0	0
T78	495	0	0	0
T82	422	0	0	0
T89	0	449	0	0
T90	0	98	0	0
T91	0	64	0	0
T92	0	61	0	0
T94	0	292	0	0
T108	404	0	0	0
T115	0	453	0	0
T143	409	0	0	0
T144	402	0	0	0
T156	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	6852	0	0
T1	8953	10	0	0
T2	788	4	0	0
T3	38319	12	0	0
T5	38517	17	0	0
T13	402	0	0	0
T14	719	3	0	0
T15	2162	9	0	0
T16	426	3	0	0
T17	454	6	0	0
T18	404	0	0	0
T19	0	6	0	0
T25	0	8	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8309358	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	607326	0	0
T8	18107	134	0	0
T9	12144	0	0	0
T10	32256	0	0	0
T24	0	330	0	0
T71	319237	0	0	0
T72	750	0	0	0
T77	0	179	0	0
T78	495	0	0	0
T82	422	0	0	0
T89	0	99	0	0
T90	0	260776	0	0
T91	0	167	0	0
T92	0	635	0	0
T94	0	75	0	0
T108	404	0	0	0
T115	0	91	0	0
T143	409	0	0	0
T144	402	0	0	0
T156	0	341	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T15

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T15
1	1	Covered	T4,T5,T15

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T8,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T8,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T8,T77

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T24
1	0	Covered	T4,T5,T15
1	1	Covered	T2,T8,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T89
0	1	Covered	T77,T123,T125
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T89
0	1	Unreachable
1	0	Covered	T2,T8,T89

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T8,T24
DetectSt	168	Covered	T2,T8,T77
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T8,T89

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T8,T77
DebounceSt->IdleSt	163	Covered	T24,T77,T69
DetectSt->IdleSt	186	Covered	T77,T123,T125
DetectSt->StableSt	191	Covered	T2,T8,T89
IdleSt->DebounceSt	148	Covered	T2,T8,T24
StableSt->IdleSt	206	Covered	T2,T8,T89

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T8,T24
0	1	Covered	T2,T8,T24
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T77
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T8,T24
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T116
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T8,T77
DebounceSt	-	0	1	0	-	-	-	Covered	T24,T77,T115
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T8,T24
DetectSt	-	-	-	-	1	-	-	Covered	T77,T123,T125
DetectSt	-	-	-	-	0	1	-	Covered	T2,T8,T89
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T8,T89
StableSt	-	-	-	-	-	-	0	Covered	T2,T8,T89
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8955184	149	0	0
CntIncr_A	8955184	169294	0	0
CntNoWrap_A	8955184	8306832	0	0
DetectStDropOut_A	8955184	17	0	0
DetectedOut_A	8955184	198794	0	0
DetectedPulseOut_A	8955184	38	0	0
DisabledIdleSt_A	8955184	5479430	0	0
DisabledNoDetection_A	8955184	5481804	0	0
EnterDebounceSt_A	8955184	96	0	0
EnterDetectSt_A	8955184	55	0	0
EnterStableSt_A	8955184	38	0	0
PulseIsPulse_A	8955184	38	0	0
StayInStableSt	8955184	198756	0	0
gen_high_level_sva.HighLevelEvent_A	8955184	8309358	0	0
gen_sticky_sva.StableStDropOut_A	8955184	1994188	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	149	0	0
T2	788	2	0	0
T3	38319	0	0	0
T6	659	0	0	0
T8	0	4	0	0
T18	404	0	0	0
T19	523	0	0	0
T24	0	5	0	0
T25	494	0	0	0
T26	495	0	0	0
T27	522	0	0	0
T34	656	0	0	0
T77	0	8	0	0
T81	502	0	0	0
T89	0	4	0	0
T90	0	4	0	0
T91	0	2	0	0
T92	0	4	0	0
T93	0	2	0	0
T94	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	169294	0	0
T2	788	37	0	0
T3	38319	0	0	0
T6	659	0	0	0
T8	0	49	0	0
T18	404	0	0	0
T19	523	0	0	0
T24	0	375	0	0
T25	494	0	0	0
T26	495	0	0	0
T27	522	0	0	0
T34	656	0	0	0
T77	0	245	0	0
T81	502	0	0	0
T89	0	24	0	0
T90	0	74	0	0
T91	0	67	0	0
T92	0	93	0	0
T93	0	84	0	0
T94	0	32	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8306832	0	0
T1	8953	8545	0	0
T2	788	385	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	17	0	0
T40	15100	0	0	0
T77	1022	3	0	0
T123	0	3	0	0
T125	0	5	0	0
T129	698	0	0	0
T160	0	1	0	0
T161	0	3	0	0
T162	0	1	0	0
T163	0	1	0	0
T164	21865	0	0	0
T165	3568	0	0	0
T166	527	0	0	0
T167	489	0	0	0
T168	402	0	0	0
T169	727	0	0	0
T170	633	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	198794	0	0
T2	788	19	0	0
T3	38319	0	0	0
T6	659	0	0	0
T8	0	191	0	0
T18	404	0	0	0
T19	523	0	0	0
T25	494	0	0	0
T26	495	0	0	0
T27	522	0	0	0
T34	656	0	0	0
T81	502	0	0	0
T89	0	40	0	0
T90	0	517	0	0
T91	0	148	0	0
T92	0	254	0	0
T93	0	20	0	0
T94	0	239	0	0
T155	0	452	0	0
T156	0	215	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	38	0	0
T2	788	1	0	0
T3	38319	0	0	0
T6	659	0	0	0
T8	0	2	0	0
T18	404	0	0	0
T19	523	0	0	0
T25	494	0	0	0
T26	495	0	0	0
T27	522	0	0	0
T34	656	0	0	0
T81	502	0	0	0
T89	0	2	0	0
T90	0	2	0	0
T91	0	1	0	0
T92	0	2	0	0
T93	0	1	0	0
T94	0	1	0	0
T155	0	2	0	0
T156	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	5479430	0	0
T1	8953	8545	0	0
T2	788	281	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	5481804	0	0
T1	8953	8547	0	0
T2	788	282	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	96	0	0
T2	788	1	0	0
T3	38319	0	0	0
T6	659	0	0	0
T8	0	2	0	0
T18	404	0	0	0
T19	523	0	0	0
T24	0	5	0	0
T25	494	0	0	0
T26	495	0	0	0
T27	522	0	0	0
T34	656	0	0	0
T77	0	5	0	0
T81	502	0	0	0
T89	0	2	0	0
T90	0	2	0	0
T91	0	1	0	0
T92	0	2	0	0
T93	0	1	0	0
T94	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	55	0	0
T2	788	1	0	0
T3	38319	0	0	0
T6	659	0	0	0
T8	0	2	0	0
T18	404	0	0	0
T19	523	0	0	0
T25	494	0	0	0
T26	495	0	0	0
T27	522	0	0	0
T34	656	0	0	0
T77	0	3	0	0
T81	502	0	0	0
T89	0	2	0	0
T90	0	2	0	0
T91	0	1	0	0
T92	0	2	0	0
T93	0	1	0	0
T94	0	1	0	0
T155	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	38	0	0
T2	788	1	0	0
T3	38319	0	0	0
T6	659	0	0	0
T8	0	2	0	0
T18	404	0	0	0
T19	523	0	0	0
T25	494	0	0	0
T26	495	0	0	0
T27	522	0	0	0
T34	656	0	0	0
T81	502	0	0	0
T89	0	2	0	0
T90	0	2	0	0
T91	0	1	0	0
T92	0	2	0	0
T93	0	1	0	0
T94	0	1	0	0
T155	0	2	0	0
T156	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	38	0	0
T2	788	1	0	0
T3	38319	0	0	0
T6	659	0	0	0
T8	0	2	0	0
T18	404	0	0	0
T19	523	0	0	0
T25	494	0	0	0
T26	495	0	0	0
T27	522	0	0	0
T34	656	0	0	0
T81	502	0	0	0
T89	0	2	0	0
T90	0	2	0	0
T91	0	1	0	0
T92	0	2	0	0
T93	0	1	0	0
T94	0	1	0	0
T155	0	2	0	0
T156	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	198756	0	0
T2	788	18	0	0
T3	38319	0	0	0
T6	659	0	0	0
T8	0	189	0	0
T18	404	0	0	0
T19	523	0	0	0
T25	494	0	0	0
T26	495	0	0	0
T27	522	0	0	0
T34	656	0	0	0
T81	502	0	0	0
T89	0	38	0	0
T90	0	515	0	0
T91	0	147	0	0
T92	0	252	0	0
T93	0	19	0	0
T94	0	238	0	0
T155	0	450	0	0
T156	0	214	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8309358	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	1994188	0	0
T2	788	25	0	0
T3	38319	0	0	0
T6	659	0	0	0
T8	0	373	0	0
T18	404	0	0	0
T19	523	0	0	0
T25	494	0	0	0
T26	495	0	0	0
T27	522	0	0	0
T34	656	0	0	0
T81	502	0	0	0
T89	0	636	0	0
T90	0	782139	0	0
T91	0	49	0	0
T92	0	388	0	0
T93	0	25	0	0
T94	0	322	0	0
T155	0	667712	0	0
T156	0	86	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T8,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T8,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T8,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T24
1	0	Covered	T4,T5,T1
1	1	Covered	T2,T8,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T24
0	1	Covered	T8,T123,T124
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T24
0	1	Unreachable
1	0	Covered	T2,T8,T24

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T8,T24
DetectSt	168	Covered	T2,T8,T24
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T8,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T8,T24
DebounceSt->IdleSt	163	Covered	T8,T92,T93
DetectSt->IdleSt	186	Covered	T8,T123,T124
DetectSt->StableSt	191	Covered	T2,T8,T24
IdleSt->DebounceSt	148	Covered	T2,T8,T24
StableSt->IdleSt	206	Covered	T2,T8,T24

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T8,T24
0	1	Covered	T2,T8,T24
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T24
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T8,T24
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T116
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T8,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T92,T93
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T8,T24
DetectSt	-	-	-	-	1	-	-	Covered	T8,T123,T124
DetectSt	-	-	-	-	0	1	-	Covered	T2,T8,T24
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T8,T24
StableSt	-	-	-	-	-	-	0	Covered	T2,T8,T24
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8955184	137	0	0
CntIncr_A	8955184	234098	0	0
CntNoWrap_A	8955184	8306844	0	0
DetectStDropOut_A	8955184	10	0	0
DetectedOut_A	8955184	1228146	0	0
DetectedPulseOut_A	8955184	40	0	0
DisabledIdleSt_A	8955184	5479430	0	0
DisabledNoDetection_A	8955184	5481804	0	0
EnterDebounceSt_A	8955184	89	0	0
EnterDetectSt_A	8955184	50	0	0
EnterStableSt_A	8955184	40	0	0
PulseIsPulse_A	8955184	40	0	0
StayInStableSt	8955184	1228106	0	0
gen_high_event_sva.HighLevelEvent_A	8955184	8309358	0	0
gen_high_level_sva.HighLevelEvent_A	8955184	8309358	0	0
gen_sticky_sva.StableStDropOut_A	8955184	1128581	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	137	0	0
T2	788	2	0	0
T3	38319	0	0	0
T6	659	0	0	0
T8	0	6	0	0
T18	404	0	0	0
T19	523	0	0	0
T24	0	2	0	0
T25	494	0	0	0
T26	495	0	0	0
T27	522	0	0	0
T34	656	0	0	0
T77	0	2	0	0
T81	502	0	0	0
T89	0	4	0	0
T90	0	4	0	0
T91	0	2	0	0
T92	0	5	0	0
T93	0	1	0	0
T94	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	234098	0	0
T2	788	43	0	0
T3	38319	0	0	0
T6	659	0	0	0
T8	0	196	0	0
T18	404	0	0	0
T19	523	0	0	0
T24	0	97	0	0
T25	494	0	0	0
T26	495	0	0	0
T27	522	0	0	0
T34	656	0	0	0
T77	0	12	0	0
T81	502	0	0	0
T89	0	150	0	0
T90	0	115350	0	0
T91	0	42	0	0
T92	0	405	0	0
T93	0	30	0	0
T94	0	56	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8306844	0	0
T1	8953	8545	0	0
T2	788	385	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	10	0	0
T8	18107	1	0	0
T9	12144	0	0	0
T10	32256	0	0	0
T71	319237	0	0	0
T72	750	0	0	0
T78	495	0	0	0
T82	422	0	0	0
T108	404	0	0	0
T123	0	3	0	0
T124	0	2	0	0
T143	409	0	0	0
T144	402	0	0	0
T157	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	1228146	0	0
T2	788	5	0	0
T3	38319	0	0	0
T6	659	0	0	0
T8	0	35	0	0
T18	404	0	0	0
T19	523	0	0	0
T24	0	487	0	0
T25	494	0	0	0
T26	495	0	0	0
T27	522	0	0	0
T34	656	0	0	0
T77	0	94	0	0
T81	502	0	0	0
T89	0	339	0	0
T90	0	667304	0	0
T91	0	62	0	0
T94	0	366	0	0
T155	0	553890	0	0
T156	0	61	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	40	0	0
T2	788	1	0	0
T3	38319	0	0	0
T6	659	0	0	0
T8	0	1	0	0
T18	404	0	0	0
T19	523	0	0	0
T24	0	1	0	0
T25	494	0	0	0
T26	495	0	0	0
T27	522	0	0	0
T34	656	0	0	0
T77	0	1	0	0
T81	502	0	0	0
T89	0	2	0	0
T90	0	2	0	0
T91	0	1	0	0
T94	0	1	0	0
T155	0	2	0	0
T156	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	5479430	0	0
T1	8953	8545	0	0
T2	788	281	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	5481804	0	0
T1	8953	8547	0	0
T2	788	282	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	89	0	0
T2	788	1	0	0
T3	38319	0	0	0
T6	659	0	0	0
T8	0	4	0	0
T18	404	0	0	0
T19	523	0	0	0
T24	0	1	0	0
T25	494	0	0	0
T26	495	0	0	0
T27	522	0	0	0
T34	656	0	0	0
T77	0	1	0	0
T81	502	0	0	0
T89	0	2	0	0
T90	0	2	0	0
T91	0	1	0	0
T92	0	5	0	0
T93	0	1	0	0
T94	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	50	0	0
T2	788	1	0	0
T3	38319	0	0	0
T6	659	0	0	0
T8	0	2	0	0
T18	404	0	0	0
T19	523	0	0	0
T24	0	1	0	0
T25	494	0	0	0
T26	495	0	0	0
T27	522	0	0	0
T34	656	0	0	0
T77	0	1	0	0
T81	502	0	0	0
T89	0	2	0	0
T90	0	2	0	0
T91	0	1	0	0
T94	0	1	0	0
T155	0	2	0	0
T156	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	40	0	0
T2	788	1	0	0
T3	38319	0	0	0
T6	659	0	0	0
T8	0	1	0	0
T18	404	0	0	0
T19	523	0	0	0
T24	0	1	0	0
T25	494	0	0	0
T26	495	0	0	0
T27	522	0	0	0
T34	656	0	0	0
T77	0	1	0	0
T81	502	0	0	0
T89	0	2	0	0
T90	0	2	0	0
T91	0	1	0	0
T94	0	1	0	0
T155	0	2	0	0
T156	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	40	0	0
T2	788	1	0	0
T3	38319	0	0	0
T6	659	0	0	0
T8	0	1	0	0
T18	404	0	0	0
T19	523	0	0	0
T24	0	1	0	0
T25	494	0	0	0
T26	495	0	0	0
T27	522	0	0	0
T34	656	0	0	0
T77	0	1	0	0
T81	502	0	0	0
T89	0	2	0	0
T90	0	2	0	0
T91	0	1	0	0
T94	0	1	0	0
T155	0	2	0	0
T156	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	1228106	0	0
T2	788	4	0	0
T3	38319	0	0	0
T6	659	0	0	0
T8	0	34	0	0
T18	404	0	0	0
T19	523	0	0	0
T24	0	486	0	0
T25	494	0	0	0
T26	495	0	0	0
T27	522	0	0	0
T34	656	0	0	0
T77	0	93	0	0
T81	502	0	0	0
T89	0	337	0	0
T90	0	667302	0	0
T91	0	61	0	0
T94	0	365	0	0
T155	0	553888	0	0
T156	0	60	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8309358	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8309358	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	1128581	0	0
T2	788	51	0	0
T3	38319	0	0	0
T6	659	0	0	0
T8	0	201	0	0
T18	404	0	0	0
T19	523	0	0	0
T24	0	245412	0	0
T25	494	0	0	0
T26	495	0	0	0
T27	522	0	0	0
T34	656	0	0	0
T77	0	254	0	0
T81	502	0	0	0
T89	0	239	0	0
T90	0	108	0	0
T91	0	171	0	0
T94	0	182	0	0
T155	0	254	0	0
T156	0	319	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T41,T38,T51

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T41,T38,T51

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T41,T38,T51

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T50,T41
1	0	Covered	T4,T5,T1
1	1	Covered	T41,T38,T51

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T41,T38,T51
0	1	Not Covered
1	0	Covered	T69

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T41,T38,T51
0	1	Covered	T41,T24,T42
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T41,T38,T51
1	-	Covered	T41,T24,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T41,T38,T51
DetectSt	168	Covered	T41,T38,T51
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T41,T38,T51

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T41,T38,T51
DebounceSt->IdleSt	163	Covered	T174,T116
DetectSt->IdleSt	186	Covered	T69
DetectSt->StableSt	191	Covered	T41,T38,T51
IdleSt->DebounceSt	148	Covered	T41,T38,T51
StableSt->IdleSt	206	Covered	T41,T51,T24

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T41,T38,T51
0	1	Covered	T41,T38,T51
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T41,T38,T51
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T41,T38,T51
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T116
DebounceSt	-	0	1	1	-	-	-	Covered	T41,T38,T51
DebounceSt	-	0	1	0	-	-	-	Covered	T174
DebounceSt	-	0	0	-	-	-	-	Covered	T41,T38,T51
DetectSt	-	-	-	-	1	-	-	Covered	T69
DetectSt	-	-	-	-	0	1	-	Covered	T41,T38,T51
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T41,T24,T42
StableSt	-	-	-	-	-	-	0	Covered	T41,T38,T51
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8955184	76	0	0
CntIncr_A	8955184	33340	0	0
CntNoWrap_A	8955184	8306905	0	0
DetectStDropOut_A	8955184	0	0	0
DetectedOut_A	8955184	2867	0	0
DetectedPulseOut_A	8955184	36	0	0
DisabledIdleSt_A	8955184	8153025	0	0
DisabledNoDetection_A	8955184	8155353	0	0
EnterDebounceSt_A	8955184	39	0	0
EnterDetectSt_A	8955184	37	0	0
EnterStableSt_A	8955184	36	0	0
PulseIsPulse_A	8955184	36	0	0
StayInStableSt	8955184	2811	0	0
gen_high_level_sva.HighLevelEvent_A	8955184	8309358	0	0
gen_not_sticky_sva.StableStDropOut_A	8955184	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	76	0	0
T24	0	4	0	0
T38	1061	2	0	0
T40	0	2	0	0
T41	2749	2	0	0
T42	0	2	0	0
T43	0	2	0	0
T51	0	2	0	0
T58	2064	0	0	0
T70	19045	0	0	0
T93	0	2	0	0
T175	0	2	0	0
T176	0	2	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	33340	0	0
T24	0	134	0	0
T38	1061	63	0	0
T40	0	78	0	0
T41	2749	83	0	0
T42	0	43	0	0
T43	0	68	0	0
T51	0	79	0	0
T58	2064	0	0	0
T70	19045	0	0	0
T93	0	11	0	0
T175	0	12	0	0
T176	0	26	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8306905	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	2867	0	0
T24	0	82	0	0
T38	1061	42	0	0
T40	0	366	0	0
T41	2749	40	0	0
T42	0	113	0	0
T43	0	25	0	0
T51	0	40	0	0
T58	2064	0	0	0
T70	19045	0	0	0
T93	0	74	0	0
T175	0	46	0	0
T176	0	111	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	36	0	0
T24	0	2	0	0
T38	1061	1	0	0
T40	0	1	0	0
T41	2749	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T51	0	1	0	0
T58	2064	0	0	0
T70	19045	0	0	0
T93	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8153025	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8155353	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	39	0	0
T24	0	2	0	0
T38	1061	1	0	0
T40	0	1	0	0
T41	2749	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T51	0	1	0	0
T58	2064	0	0	0
T70	19045	0	0	0
T93	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	37	0	0
T24	0	2	0	0
T38	1061	1	0	0
T40	0	1	0	0
T41	2749	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T51	0	1	0	0
T58	2064	0	0	0
T70	19045	0	0	0
T93	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	36	0	0
T24	0	2	0	0
T38	1061	1	0	0
T40	0	1	0	0
T41	2749	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T51	0	1	0	0
T58	2064	0	0	0
T70	19045	0	0	0
T93	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	36	0	0
T24	0	2	0	0
T38	1061	1	0	0
T40	0	1	0	0
T41	2749	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T51	0	1	0	0
T58	2064	0	0	0
T70	19045	0	0	0
T93	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	2811	0	0
T24	0	79	0	0
T38	1061	40	0	0
T40	0	364	0	0
T41	2749	39	0	0
T42	0	112	0	0
T43	0	24	0	0
T51	0	38	0	0
T58	2064	0	0	0
T70	19045	0	0	0
T93	0	72	0	0
T175	0	44	0	0
T176	0	110	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8309358	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	16	0	0
T24	0	1	0	0
T38	1061	0	0	0
T41	2749	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T58	2064	0	0	0
T70	19045	0	0	0
T176	0	1	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0
T183	0	1	0	0
T184	0	2	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T49,T50,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T49,T50,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T49,T50,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T49,T50,T41
1	0	Covered	T4,T5,T1
1	1	Covered	T49,T50,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T49,T50,T41
0	1	Covered	T51,T188
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T49,T50,T41
0	1	Covered	T49,T38,T24
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T49,T50,T41
1	-	Covered	T49,T38,T24

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T49,T50,T41
DetectSt	168	Covered	T49,T50,T41
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T49,T50,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T49,T50,T41
DebounceSt->IdleSt	163	Covered	T41,T40,T69
DetectSt->IdleSt	186	Covered	T51,T188
DetectSt->StableSt	191	Covered	T49,T50,T41
IdleSt->DebounceSt	148	Covered	T49,T50,T41
StableSt->IdleSt	206	Covered	T49,T38,T47

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T49,T50,T41
0	1	Covered	T49,T50,T41
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T49,T50,T41
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T49,T50,T41
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T116
DebounceSt	-	0	1	1	-	-	-	Covered	T49,T50,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T41,T40,T189
DebounceSt	-	0	0	-	-	-	-	Covered	T49,T50,T41
DetectSt	-	-	-	-	1	-	-	Covered	T51,T188
DetectSt	-	-	-	-	0	1	-	Covered	T49,T50,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T49,T38,T24
StableSt	-	-	-	-	-	-	0	Covered	T49,T50,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8955184	126	0	0
CntIncr_A	8955184	162993	0	0
CntNoWrap_A	8955184	8306855	0	0
DetectStDropOut_A	8955184	2	0	0
DetectedOut_A	8955184	54226	0	0
DetectedPulseOut_A	8955184	58	0	0
DisabledIdleSt_A	8955184	7849856	0	0
DisabledNoDetection_A	8955184	7852178	0	0
EnterDebounceSt_A	8955184	67	0	0
EnterDetectSt_A	8955184	60	0	0
EnterStableSt_A	8955184	58	0	0
PulseIsPulse_A	8955184	58	0	0
StayInStableSt	8955184	54140	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8955184	2676	0	0
gen_low_level_sva.LowLevelEvent_A	8955184	8309358	0	0
gen_not_sticky_sva.StableStDropOut_A	8955184	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	126	0	0
T24	0	4	0	0
T35	2380	0	0	0
T38	0	2	0	0
T40	0	1	0	0
T41	2749	3	0	0
T47	0	2	0	0
T49	638	2	0	0
T50	477	2	0	0
T51	0	2	0	0
T56	768	0	0	0
T57	660	0	0	0
T75	1102	0	0	0
T127	12054	0	0	0
T175	0	2	0	0
T177	422	0	0	0
T190	0	2	0	0
T191	435	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	162993	0	0
T24	0	134	0	0
T35	2380	0	0	0
T38	0	63	0	0
T40	0	23	0	0
T41	2749	166	0	0
T47	0	70	0	0
T49	638	90	0	0
T50	477	21	0	0
T51	0	79	0	0
T56	768	0	0	0
T57	660	0	0	0
T75	1102	0	0	0
T127	12054	0	0	0
T175	0	12	0	0
T177	422	0	0	0
T190	0	18	0	0
T191	435	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8306855	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	2	0	0
T37	44323	0	0	0
T47	1935	0	0	0
T51	6409	1	0	0
T54	18017	0	0	0
T59	4966	0	0	0
T60	645	0	0	0
T76	946	0	0	0
T188	0	1	0	0
T192	6214	0	0	0
T193	423	0	0	0
T194	641	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	54226	0	0
T24	0	334	0	0
T35	2380	0	0	0
T38	0	155	0	0
T41	2749	136	0	0
T43	0	81	0	0
T47	0	111	0	0
T49	638	6	0	0
T50	477	45	0	0
T56	768	0	0	0
T57	660	0	0	0
T75	1102	0	0	0
T127	12054	0	0	0
T175	0	53	0	0
T177	422	0	0	0
T190	0	121	0	0
T191	435	0	0	0
T195	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	58	0	0
T24	0	2	0	0
T35	2380	0	0	0
T38	0	1	0	0
T41	2749	1	0	0
T43	0	2	0	0
T47	0	1	0	0
T49	638	1	0	0
T50	477	1	0	0
T56	768	0	0	0
T57	660	0	0	0
T75	1102	0	0	0
T127	12054	0	0	0
T175	0	1	0	0
T177	422	0	0	0
T190	0	1	0	0
T191	435	0	0	0
T195	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	7849856	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	7852178	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	67	0	0
T24	0	2	0	0
T35	2380	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	2749	2	0	0
T47	0	1	0	0
T49	638	1	0	0
T50	477	1	0	0
T51	0	1	0	0
T56	768	0	0	0
T57	660	0	0	0
T75	1102	0	0	0
T127	12054	0	0	0
T175	0	1	0	0
T177	422	0	0	0
T190	0	1	0	0
T191	435	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	60	0	0
T24	0	2	0	0
T35	2380	0	0	0
T38	0	1	0	0
T41	2749	1	0	0
T47	0	1	0	0
T49	638	1	0	0
T50	477	1	0	0
T51	0	1	0	0
T56	768	0	0	0
T57	660	0	0	0
T75	1102	0	0	0
T127	12054	0	0	0
T175	0	1	0	0
T177	422	0	0	0
T190	0	1	0	0
T191	435	0	0	0
T195	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	58	0	0
T24	0	2	0	0
T35	2380	0	0	0
T38	0	1	0	0
T41	2749	1	0	0
T43	0	2	0	0
T47	0	1	0	0
T49	638	1	0	0
T50	477	1	0	0
T56	768	0	0	0
T57	660	0	0	0
T75	1102	0	0	0
T127	12054	0	0	0
T175	0	1	0	0
T177	422	0	0	0
T190	0	1	0	0
T191	435	0	0	0
T195	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	58	0	0
T24	0	2	0	0
T35	2380	0	0	0
T38	0	1	0	0
T41	2749	1	0	0
T43	0	2	0	0
T47	0	1	0	0
T49	638	1	0	0
T50	477	1	0	0
T56	768	0	0	0
T57	660	0	0	0
T75	1102	0	0	0
T127	12054	0	0	0
T175	0	1	0	0
T177	422	0	0	0
T190	0	1	0	0
T191	435	0	0	0
T195	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	54140	0	0
T24	0	332	0	0
T35	2380	0	0	0
T38	0	154	0	0
T41	2749	134	0	0
T43	0	78	0	0
T47	0	109	0	0
T49	638	5	0	0
T50	477	43	0	0
T56	768	0	0	0
T57	660	0	0	0
T75	1102	0	0	0
T127	12054	0	0	0
T175	0	52	0	0
T177	422	0	0	0
T190	0	119	0	0
T191	435	0	0	0
T195	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	2676	0	0
T1	8953	0	0	0
T2	788	0	0	0
T4	407	1	0	0
T5	38517	14	0	0
T6	0	1	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	3	0	0
T17	454	5	0	0
T18	404	0	0	0
T19	0	8	0	0
T25	0	4	0	0
T26	0	4	0	0
T27	0	7	0	0
T81	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8309358	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	30	0	0
T24	0	2	0	0
T35	2380	0	0	0
T38	0	1	0	0
T41	2749	0	0	0
T43	0	1	0	0
T49	638	1	0	0
T50	477	0	0	0
T56	768	0	0	0
T57	660	0	0	0
T75	1102	0	0	0
T127	12054	0	0	0
T174	0	1	0	0
T175	0	1	0	0
T177	422	0	0	0
T185	0	1	0	0
T191	435	0	0	0
T196	0	1	0	0
T197	0	2	0	0
T198	0	1	0	0