Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.85	100.00	90.48		100.00	100.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.85	100.00	90.48		100.00	100.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.85	100.00	90.48		100.00	100.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.85	100.00	90.48		100.00	100.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T50,T41,T48

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T50,T41,T48

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T50,T41,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T50,T41,T48
1	0	Covered	T4,T5,T1
1	1	Covered	T50,T41,T48

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T50,T41,T48
0	1	Covered	T199
1	0	Covered	T69

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T50,T41,T48
0	1	Covered	T48,T24,T175
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T50,T41,T48
1	-	Covered	T48,T24,T175

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T50,T41,T48
DetectSt	168	Covered	T50,T41,T48
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T50,T41,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T50,T41,T48
DebounceSt->IdleSt	163	Covered	T116,T200
DetectSt->IdleSt	186	Covered	T199,T69
DetectSt->StableSt	191	Covered	T50,T41,T48
IdleSt->DebounceSt	148	Covered	T50,T41,T48
StableSt->IdleSt	206	Covered	T48,T61,T24

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T50,T41,T48
0	1	Covered	T50,T41,T48
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T50,T41,T48
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T50,T41,T48
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T116
DebounceSt	-	0	1	1	-	-	-	Covered	T50,T41,T48
DebounceSt	-	0	1	0	-	-	-	Covered	T200
DebounceSt	-	0	0	-	-	-	-	Covered	T50,T41,T48
DetectSt	-	-	-	-	1	-	-	Covered	T199,T69
DetectSt	-	-	-	-	0	1	-	Covered	T50,T41,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T48,T24,T175
StableSt	-	-	-	-	-	-	0	Covered	T50,T41,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8955184	72	0	0
CntIncr_A	8955184	61522	0	0
CntNoWrap_A	8955184	8306909	0	0
DetectStDropOut_A	8955184	1	0	0
DetectedOut_A	8955184	5437	0	0
DetectedPulseOut_A	8955184	33	0	0
DisabledIdleSt_A	8955184	7851697	0	0
DisabledNoDetection_A	8955184	7854030	0	0
EnterDebounceSt_A	8955184	37	0	0
EnterDetectSt_A	8955184	35	0	0
EnterStableSt_A	8955184	33	0	0
PulseIsPulse_A	8955184	33	0	0
StayInStableSt	8955184	5386	0	0
gen_high_level_sva.HighLevelEvent_A	8955184	8309358	0	0
gen_not_sticky_sva.StableStDropOut_A	8955184	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	72	0	0
T24	0	2	0	0
T38	1061	0	0	0
T41	2749	2	0	0
T42	0	2	0	0
T46	0	2	0	0
T48	0	2	0	0
T50	477	2	0	0
T57	660	0	0	0
T58	2064	0	0	0
T61	0	2	0	0
T93	0	2	0	0
T175	0	2	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T201	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	61522	0	0
T24	0	67	0	0
T38	1061	0	0	0
T41	2749	83	0	0
T42	0	43	0	0
T46	0	86	0	0
T48	0	75	0	0
T50	477	21	0	0
T57	660	0	0	0
T58	2064	0	0	0
T61	0	78	0	0
T93	0	11	0	0
T175	0	12	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T201	0	58	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8306909	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	1	0	0
T199	6753	1	0	0
T202	40977	0	0	0
T203	436	0	0	0
T204	540	0	0	0
T205	15065	0	0	0
T206	447	0	0	0
T207	445	0	0	0
T208	5646	0	0	0
T209	564	0	0	0
T210	404	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	5437	0	0
T24	0	41	0	0
T38	1061	0	0	0
T41	2749	51	0	0
T42	0	38	0	0
T46	0	43	0	0
T48	0	42	0	0
T50	477	45	0	0
T57	660	0	0	0
T58	2064	0	0	0
T61	0	40	0	0
T93	0	61	0	0
T175	0	40	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T201	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	33	0	0
T24	0	1	0	0
T38	1061	0	0	0
T41	2749	1	0	0
T42	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T50	477	1	0	0
T57	660	0	0	0
T58	2064	0	0	0
T61	0	1	0	0
T93	0	1	0	0
T175	0	1	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T201	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	7851697	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	7854030	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	37	0	0
T24	0	1	0	0
T38	1061	0	0	0
T41	2749	1	0	0
T42	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T50	477	1	0	0
T57	660	0	0	0
T58	2064	0	0	0
T61	0	1	0	0
T93	0	1	0	0
T175	0	1	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T201	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	35	0	0
T24	0	1	0	0
T38	1061	0	0	0
T41	2749	1	0	0
T42	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T50	477	1	0	0
T57	660	0	0	0
T58	2064	0	0	0
T61	0	1	0	0
T93	0	1	0	0
T175	0	1	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T201	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	33	0	0
T24	0	1	0	0
T38	1061	0	0	0
T41	2749	1	0	0
T42	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T50	477	1	0	0
T57	660	0	0	0
T58	2064	0	0	0
T61	0	1	0	0
T93	0	1	0	0
T175	0	1	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T201	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	33	0	0
T24	0	1	0	0
T38	1061	0	0	0
T41	2749	1	0	0
T42	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T50	477	1	0	0
T57	660	0	0	0
T58	2064	0	0	0
T61	0	1	0	0
T93	0	1	0	0
T175	0	1	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T201	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	5386	0	0
T24	0	40	0	0
T38	1061	0	0	0
T41	2749	49	0	0
T42	0	36	0	0
T46	0	41	0	0
T48	0	41	0	0
T50	477	43	0	0
T57	660	0	0	0
T58	2064	0	0	0
T61	0	38	0	0
T93	0	59	0	0
T175	0	39	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T201	0	38	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8309358	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	15	0	0
T24	0	1	0	0
T29	9157	0	0	0
T37	44323	0	0	0
T48	3719	1	0	0
T51	6409	0	0	0
T59	4966	0	0	0
T60	645	0	0	0
T76	946	0	0	0
T175	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0
T188	0	1	0	0
T192	6214	0	0	0
T200	0	1	0	0
T211	0	2	0	0
T212	0	1	0	0
T213	0	2	0	0
T214	488	0	0	0
T215	526	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T8,T38,T48

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T8,T38,T48

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T8,T38,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T38,T48
1	0	Covered	T4,T5,T1
1	1	Covered	T8,T38,T48

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T38,T48
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T38,T48
0	1	Covered	T38,T48,T24
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T38,T48
1	-	Covered	T38,T48,T24

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T38,T48
DetectSt	168	Covered	T8,T38,T48
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T8,T38,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T38,T48
DebounceSt->IdleSt	163	Covered	T201,T185,T69
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T8,T38,T48
IdleSt->DebounceSt	148	Covered	T8,T38,T48
StableSt->IdleSt	206	Covered	T8,T38,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T38,T48
0	1	Covered	T8,T38,T48
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T38,T48
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T38,T48
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T116
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T38,T48
DebounceSt	-	0	1	0	-	-	-	Covered	T201,T185,T211
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T38,T48
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T8,T38,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T38,T48,T24
StableSt	-	-	-	-	-	-	0	Covered	T8,T38,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8955184	103	0	0
CntIncr_A	8955184	3107	0	0
CntNoWrap_A	8955184	8306878	0	0
DetectStDropOut_A	8955184	0	0	0
DetectedOut_A	8955184	4721	0	0
DetectedPulseOut_A	8955184	49	0	0
DisabledIdleSt_A	8955184	8153054	0	0
DisabledNoDetection_A	8955184	8155384	0	0
EnterDebounceSt_A	8955184	54	0	0
EnterDetectSt_A	8955184	49	0	0
EnterStableSt_A	8955184	49	0	0
PulseIsPulse_A	8955184	49	0	0
StayInStableSt	8955184	4649	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8955184	3079	0	0
gen_low_level_sva.LowLevelEvent_A	8955184	8309358	0	0
gen_not_sticky_sva.StableStDropOut_A	8955184	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	103	0	0
T8	18107	2	0	0
T9	12144	0	0	0
T10	32256	0	0	0
T24	0	4	0	0
T38	0	2	0	0
T42	0	2	0	0
T44	0	4	0	0
T48	0	4	0	0
T71	319237	0	0	0
T72	750	0	0	0
T78	495	0	0	0
T82	422	0	0	0
T108	404	0	0	0
T143	409	0	0	0
T144	402	0	0	0
T175	0	4	0	0
T195	0	2	0	0
T201	0	1	0	0
T216	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	3107	0	0
T8	18107	56	0	0
T9	12144	0	0	0
T10	32256	0	0	0
T24	0	134	0	0
T38	0	63	0	0
T42	0	43	0	0
T44	0	98	0	0
T48	0	150	0	0
T71	319237	0	0	0
T72	750	0	0	0
T78	495	0	0	0
T82	422	0	0	0
T108	404	0	0	0
T143	409	0	0	0
T144	402	0	0	0
T175	0	24	0	0
T195	0	36	0	0
T201	0	58	0	0
T216	0	92	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8306878	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	4721	0	0
T8	18107	45	0	0
T9	12144	0	0	0
T10	32256	0	0	0
T24	0	443	0	0
T38	0	44	0	0
T42	0	192	0	0
T43	0	62	0	0
T44	0	83	0	0
T48	0	175	0	0
T71	319237	0	0	0
T72	750	0	0	0
T78	495	0	0	0
T82	422	0	0	0
T108	404	0	0	0
T143	409	0	0	0
T144	402	0	0	0
T175	0	47	0	0
T195	0	103	0	0
T216	0	143	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	49	0	0
T8	18107	1	0	0
T9	12144	0	0	0
T10	32256	0	0	0
T24	0	2	0	0
T38	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T48	0	2	0	0
T71	319237	0	0	0
T72	750	0	0	0
T78	495	0	0	0
T82	422	0	0	0
T108	404	0	0	0
T143	409	0	0	0
T144	402	0	0	0
T175	0	2	0	0
T195	0	1	0	0
T216	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8153054	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8155384	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	54	0	0
T8	18107	1	0	0
T9	12144	0	0	0
T10	32256	0	0	0
T24	0	2	0	0
T38	0	1	0	0
T42	0	1	0	0
T44	0	2	0	0
T48	0	2	0	0
T71	319237	0	0	0
T72	750	0	0	0
T78	495	0	0	0
T82	422	0	0	0
T108	404	0	0	0
T143	409	0	0	0
T144	402	0	0	0
T175	0	2	0	0
T195	0	1	0	0
T201	0	1	0	0
T216	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	49	0	0
T8	18107	1	0	0
T9	12144	0	0	0
T10	32256	0	0	0
T24	0	2	0	0
T38	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T48	0	2	0	0
T71	319237	0	0	0
T72	750	0	0	0
T78	495	0	0	0
T82	422	0	0	0
T108	404	0	0	0
T143	409	0	0	0
T144	402	0	0	0
T175	0	2	0	0
T195	0	1	0	0
T216	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	49	0	0
T8	18107	1	0	0
T9	12144	0	0	0
T10	32256	0	0	0
T24	0	2	0	0
T38	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T48	0	2	0	0
T71	319237	0	0	0
T72	750	0	0	0
T78	495	0	0	0
T82	422	0	0	0
T108	404	0	0	0
T143	409	0	0	0
T144	402	0	0	0
T175	0	2	0	0
T195	0	1	0	0
T216	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	49	0	0
T8	18107	1	0	0
T9	12144	0	0	0
T10	32256	0	0	0
T24	0	2	0	0
T38	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T48	0	2	0	0
T71	319237	0	0	0
T72	750	0	0	0
T78	495	0	0	0
T82	422	0	0	0
T108	404	0	0	0
T143	409	0	0	0
T144	402	0	0	0
T175	0	2	0	0
T195	0	1	0	0
T216	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	4649	0	0
T8	18107	43	0	0
T9	12144	0	0	0
T10	32256	0	0	0
T24	0	440	0	0
T38	0	43	0	0
T42	0	191	0	0
T43	0	60	0	0
T44	0	80	0	0
T48	0	172	0	0
T71	319237	0	0	0
T72	750	0	0	0
T78	495	0	0	0
T82	422	0	0	0
T108	404	0	0	0
T143	409	0	0	0
T144	402	0	0	0
T175	0	44	0	0
T195	0	101	0	0
T216	0	141	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	3079	0	0
T1	8953	0	0	0
T2	788	0	0	0
T4	407	1	0	0
T5	38517	13	0	0
T6	0	1	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	2	0	0
T17	454	6	0	0
T18	404	0	0	0
T19	0	6	0	0
T25	0	4	0	0
T26	0	4	0	0
T27	0	5	0	0
T81	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8309358	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	26	0	0
T24	0	1	0	0
T29	9157	0	0	0
T38	1061	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T48	3719	1	0	0
T58	2064	0	0	0
T70	19045	0	0	0
T93	0	1	0	0
T175	0	1	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0
T214	488	0	0	0
T215	526	0	0	0
T217	0	1	0	0
T218	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T5,T1,T15
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T7,T51

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T6,T7,T51

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T7,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T50
1	0	Covered	T4,T5,T1
1	1	Covered	T6,T7,T51

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T42
0	1	Covered	T47
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T42
0	1	Covered	T6,T7,T175
1	0	Covered	T69

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T7,T42
1	-	Covered	T6,T7,T175

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T7,T51
DetectSt	168	Covered	T6,T7,T47
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T6,T7,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T7,T47
DebounceSt->IdleSt	163	Covered	T51,T201,T116
DetectSt->IdleSt	186	Covered	T47
DetectSt->StableSt	191	Covered	T6,T7,T42
IdleSt->DebounceSt	148	Covered	T6,T7,T51
StableSt->IdleSt	206	Covered	T6,T7,T175

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T7,T51
0	1	Covered	T6,T7,T51
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T47
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T7,T51
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T116
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T7,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T51,T201,T219
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T7,T51
DetectSt	-	-	-	-	1	-	-	Covered	T47
DetectSt	-	-	-	-	0	1	-	Covered	T6,T7,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T7,T175
StableSt	-	-	-	-	-	-	0	Covered	T6,T7,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8955184	105	0	0
CntIncr_A	8955184	2927	0	0
CntNoWrap_A	8955184	8306876	0	0
DetectStDropOut_A	8955184	1	0	0
DetectedOut_A	8955184	4304	0	0
DetectedPulseOut_A	8955184	49	0	0
DisabledIdleSt_A	8955184	8155636	0	0
DisabledNoDetection_A	8955184	8157965	0	0
EnterDebounceSt_A	8955184	55	0	0
EnterDetectSt_A	8955184	50	0	0
EnterStableSt_A	8955184	49	0	0
PulseIsPulse_A	8955184	49	0	0
StayInStableSt	8955184	4229	0	0
gen_high_level_sva.HighLevelEvent_A	8955184	8309358	0	0
gen_not_sticky_sva.StableStDropOut_A	8955184	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	105	0	0
T6	659	2	0	0
T7	1131	2	0	0
T8	18107	0	0	0
T9	12144	0	0	0
T26	495	0	0	0
T34	656	0	0	0
T42	0	2	0	0
T43	0	2	0	0
T47	0	2	0	0
T51	0	1	0	0
T73	770	0	0	0
T78	495	0	0	0
T81	502	0	0	0
T82	422	0	0	0
T175	0	4	0	0
T201	0	1	0	0
T216	0	2	0	0
T220	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	2927	0	0
T6	659	72	0	0
T7	1131	78	0	0
T8	18107	0	0	0
T9	12144	0	0	0
T26	495	0	0	0
T34	656	0	0	0
T42	0	43	0	0
T43	0	68	0	0
T47	0	70	0	0
T51	0	79	0	0
T73	770	0	0	0
T78	495	0	0	0
T81	502	0	0	0
T82	422	0	0	0
T175	0	24	0	0
T201	0	58	0	0
T216	0	92	0	0
T220	0	35	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8306876	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	1	0	0
T39	625	0	0	0
T47	1935	1	0	0
T54	18017	0	0	0
T61	3859	0	0	0
T62	32198	0	0	0
T193	423	0	0	0
T194	641	0	0	0
T221	431	0	0	0
T222	493	0	0	0
T223	44316	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	4304	0	0
T6	659	59	0	0
T7	1131	151	0	0
T8	18107	0	0	0
T9	12144	0	0	0
T26	495	0	0	0
T34	656	0	0	0
T42	0	274	0	0
T43	0	243	0	0
T46	0	43	0	0
T73	770	0	0	0
T78	495	0	0	0
T81	502	0	0	0
T82	422	0	0	0
T93	0	236	0	0
T175	0	93	0	0
T216	0	1	0	0
T220	0	40	0	0
T224	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	49	0	0
T6	659	1	0	0
T7	1131	1	0	0
T8	18107	0	0	0
T9	12144	0	0	0
T26	495	0	0	0
T34	656	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T46	0	1	0	0
T73	770	0	0	0
T78	495	0	0	0
T81	502	0	0	0
T82	422	0	0	0
T93	0	2	0	0
T175	0	2	0	0
T216	0	1	0	0
T220	0	1	0	0
T224	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8155636	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8157965	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	55	0	0
T6	659	1	0	0
T7	1131	1	0	0
T8	18107	0	0	0
T9	12144	0	0	0
T26	495	0	0	0
T34	656	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T47	0	1	0	0
T51	0	1	0	0
T73	770	0	0	0
T78	495	0	0	0
T81	502	0	0	0
T82	422	0	0	0
T175	0	2	0	0
T201	0	1	0	0
T216	0	1	0	0
T220	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	50	0	0
T6	659	1	0	0
T7	1131	1	0	0
T8	18107	0	0	0
T9	12144	0	0	0
T26	495	0	0	0
T34	656	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T73	770	0	0	0
T78	495	0	0	0
T81	502	0	0	0
T82	422	0	0	0
T175	0	2	0	0
T216	0	1	0	0
T220	0	1	0	0
T224	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	49	0	0
T6	659	1	0	0
T7	1131	1	0	0
T8	18107	0	0	0
T9	12144	0	0	0
T26	495	0	0	0
T34	656	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T46	0	1	0	0
T73	770	0	0	0
T78	495	0	0	0
T81	502	0	0	0
T82	422	0	0	0
T93	0	2	0	0
T175	0	2	0	0
T216	0	1	0	0
T220	0	1	0	0
T224	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	49	0	0
T6	659	1	0	0
T7	1131	1	0	0
T8	18107	0	0	0
T9	12144	0	0	0
T26	495	0	0	0
T34	656	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T46	0	1	0	0
T73	770	0	0	0
T78	495	0	0	0
T81	502	0	0	0
T82	422	0	0	0
T93	0	2	0	0
T175	0	2	0	0
T216	0	1	0	0
T220	0	1	0	0
T224	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	4229	0	0
T6	659	58	0	0
T7	1131	150	0	0
T8	18107	0	0	0
T9	12144	0	0	0
T26	495	0	0	0
T34	656	0	0	0
T42	0	272	0	0
T43	0	241	0	0
T46	0	41	0	0
T73	770	0	0	0
T78	495	0	0	0
T81	502	0	0	0
T82	422	0	0	0
T93	0	232	0	0
T175	0	90	0	0
T220	0	39	0	0
T224	0	36	0	0
T225	0	35	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8309358	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	22	0	0
T6	659	1	0	0
T7	1131	1	0	0
T8	18107	0	0	0
T9	12144	0	0	0
T26	495	0	0	0
T34	656	0	0	0
T73	770	0	0	0
T78	495	0	0	0
T81	502	0	0	0
T82	422	0	0	0
T175	0	1	0	0
T185	0	1	0	0
T197	0	1	0	0
T216	0	1	0	0
T218	0	1	0	0
T220	0	1	0	0
T226	0	2	0	0
T227	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T15
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T38,T47

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T7,T38,T47

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T38,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T50
1	0	Covered	T4,T5,T1
1	1	Covered	T7,T38,T47

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T38,T47
0	1	Not Covered
1	0	Covered	T69

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T38,T47
0	1	Covered	T45,T196,T184
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T38,T47
1	-	Covered	T45,T196,T184

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T38,T47
DetectSt	168	Covered	T7,T38,T47
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T7,T38,T47

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T38,T47
DebounceSt->IdleSt	163	Covered	T189,T116,T228
DetectSt->IdleSt	186	Covered	T69
DetectSt->StableSt	191	Covered	T7,T38,T47
IdleSt->DebounceSt	148	Covered	T7,T38,T47
StableSt->IdleSt	206	Covered	T47,T45,T196

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T38,T47
0	1	Covered	T7,T38,T47
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T38,T47
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T38,T47
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T116
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T38,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T189,T228
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T38,T47
DetectSt	-	-	-	-	1	-	-	Covered	T69
DetectSt	-	-	-	-	0	1	-	Covered	T7,T38,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T45,T196,T184
StableSt	-	-	-	-	-	-	0	Covered	T7,T38,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8955184	59	0	0
CntIncr_A	8955184	51590	0	0
CntNoWrap_A	8955184	8306922	0	0
DetectStDropOut_A	8955184	0	0	0
DetectedOut_A	8955184	1837	0	0
DetectedPulseOut_A	8955184	27	0	0
DisabledIdleSt_A	8955184	7954364	0	0
DisabledNoDetection_A	8955184	7956694	0	0
EnterDebounceSt_A	8955184	31	0	0
EnterDetectSt_A	8955184	28	0	0
EnterStableSt_A	8955184	27	0	0
PulseIsPulse_A	8955184	27	0	0
StayInStableSt	8955184	1791	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8955184	6621	0	0
gen_low_level_sva.LowLevelEvent_A	8955184	8309358	0	0
gen_not_sticky_sva.StableStDropOut_A	8955184	8	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	59	0	0
T7	1131	2	0	0
T8	18107	0	0	0
T9	12144	0	0	0
T10	32256	0	0	0
T38	0	2	0	0
T45	0	2	0	0
T47	0	2	0	0
T69	0	2	0	0
T71	319237	0	0	0
T78	495	0	0	0
T82	422	0	0	0
T108	404	0	0	0
T143	409	0	0	0
T144	402	0	0	0
T184	0	2	0	0
T196	0	4	0	0
T216	0	2	0	0
T220	0	2	0	0
T226	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	51590	0	0
T7	1131	78	0	0
T8	18107	0	0	0
T9	12144	0	0	0
T10	32256	0	0	0
T38	0	63	0	0
T45	0	15	0	0
T47	0	70	0	0
T69	0	43	0	0
T71	319237	0	0	0
T78	495	0	0	0
T82	422	0	0	0
T108	404	0	0	0
T143	409	0	0	0
T144	402	0	0	0
T184	0	54	0	0
T196	0	34	0	0
T216	0	92	0	0
T220	0	35	0	0
T226	0	158	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8306922	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	1837	0	0
T7	1131	45	0	0
T8	18107	0	0	0
T9	12144	0	0	0
T10	32256	0	0	0
T38	0	261	0	0
T45	0	4	0	0
T47	0	40	0	0
T71	319237	0	0	0
T78	495	0	0	0
T82	422	0	0	0
T108	404	0	0	0
T143	409	0	0	0
T144	402	0	0	0
T184	0	16	0	0
T196	0	81	0	0
T216	0	50	0	0
T218	0	45	0	0
T220	0	134	0	0
T226	0	81	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	27	0	0
T7	1131	1	0	0
T8	18107	0	0	0
T9	12144	0	0	0
T10	32256	0	0	0
T38	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T71	319237	0	0	0
T78	495	0	0	0
T82	422	0	0	0
T108	404	0	0	0
T143	409	0	0	0
T144	402	0	0	0
T184	0	1	0	0
T196	0	2	0	0
T216	0	1	0	0
T218	0	1	0	0
T220	0	1	0	0
T226	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	7954364	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	7956694	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	31	0	0
T7	1131	1	0	0
T8	18107	0	0	0
T9	12144	0	0	0
T10	32256	0	0	0
T38	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T69	0	1	0	0
T71	319237	0	0	0
T78	495	0	0	0
T82	422	0	0	0
T108	404	0	0	0
T143	409	0	0	0
T144	402	0	0	0
T184	0	1	0	0
T196	0	2	0	0
T216	0	1	0	0
T220	0	1	0	0
T226	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	28	0	0
T7	1131	1	0	0
T8	18107	0	0	0
T9	12144	0	0	0
T10	32256	0	0	0
T38	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T69	0	1	0	0
T71	319237	0	0	0
T78	495	0	0	0
T82	422	0	0	0
T108	404	0	0	0
T143	409	0	0	0
T144	402	0	0	0
T184	0	1	0	0
T196	0	2	0	0
T216	0	1	0	0
T220	0	1	0	0
T226	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	27	0	0
T7	1131	1	0	0
T8	18107	0	0	0
T9	12144	0	0	0
T10	32256	0	0	0
T38	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T71	319237	0	0	0
T78	495	0	0	0
T82	422	0	0	0
T108	404	0	0	0
T143	409	0	0	0
T144	402	0	0	0
T184	0	1	0	0
T196	0	2	0	0
T216	0	1	0	0
T218	0	1	0	0
T220	0	1	0	0
T226	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	27	0	0
T7	1131	1	0	0
T8	18107	0	0	0
T9	12144	0	0	0
T10	32256	0	0	0
T38	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T71	319237	0	0	0
T78	495	0	0	0
T82	422	0	0	0
T108	404	0	0	0
T143	409	0	0	0
T144	402	0	0	0
T184	0	1	0	0
T196	0	2	0	0
T216	0	1	0	0
T218	0	1	0	0
T220	0	1	0	0
T226	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	1791	0	0
T7	1131	43	0	0
T8	18107	0	0	0
T9	12144	0	0	0
T10	32256	0	0	0
T38	0	259	0	0
T45	0	3	0	0
T47	0	38	0	0
T71	319237	0	0	0
T78	495	0	0	0
T82	422	0	0	0
T108	404	0	0	0
T143	409	0	0	0
T144	402	0	0	0
T184	0	15	0	0
T196	0	78	0	0
T216	0	48	0	0
T218	0	43	0	0
T220	0	132	0	0
T226	0	78	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	6621	0	0
T1	8953	15	0	0
T2	788	4	0	0
T3	0	15	0	0
T4	407	1	0	0
T5	38517	17	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	9	0	0
T16	426	1	0	0
T17	454	7	0	0
T18	404	0	0	0
T19	0	3	0	0
T25	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8309358	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8	0	0
T45	644	1	0	0
T91	95705	0	0	0
T133	5420	0	0	0
T184	0	1	0	0
T195	549	0	0	0
T196	0	1	0	0
T201	535	0	0	0
T212	0	1	0	0
T220	11239	0	0	0
T226	0	1	0	0
T228	0	1	0	0
T229	0	1	0	0
T230	0	1	0	0
T231	23205	0	0	0
T232	495	0	0	0
T233	8033	0	0	0
T234	718	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T7,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T6,T7,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T7,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T4,T5,T1
1	1	Covered	T6,T7,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T93,T235
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T7,T24,T40
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T7,T8
1	-	Covered	T7,T24,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T7,T8
DetectSt	168	Covered	T6,T7,T8
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T6,T7,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T7,T8
DebounceSt->IdleSt	163	Covered	T92,T69,T211
DetectSt->IdleSt	186	Covered	T93,T235
DetectSt->StableSt	191	Covered	T6,T7,T8
IdleSt->DebounceSt	148	Covered	T6,T7,T8
StableSt->IdleSt	206	Covered	T7,T8,T24

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T7,T8
0	1	Covered	T6,T7,T8
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T7,T8
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T116
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T7,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T92,T211,T219
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T7,T8
DetectSt	-	-	-	-	1	-	-	Covered	T93,T235
DetectSt	-	-	-	-	0	1	-	Covered	T6,T7,T8
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T24,T40
StableSt	-	-	-	-	-	-	0	Covered	T6,T7,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8955184	123	0	0
CntIncr_A	8955184	84024	0	0
CntNoWrap_A	8955184	8306858	0	0
DetectStDropOut_A	8955184	2	0	0
DetectedOut_A	8955184	209527	0	0
DetectedPulseOut_A	8955184	57	0	0
DisabledIdleSt_A	8955184	7953684	0	0
DisabledNoDetection_A	8955184	7956008	0	0
EnterDebounceSt_A	8955184	64	0	0
EnterDetectSt_A	8955184	59	0	0
EnterStableSt_A	8955184	57	0	0
PulseIsPulse_A	8955184	57	0	0
StayInStableSt	8955184	209441	0	0
gen_high_level_sva.HighLevelEvent_A	8955184	8309358	0	0
gen_not_sticky_sva.StableStDropOut_A	8955184	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	123	0	0
T6	659	2	0	0
T7	1131	2	0	0
T8	18107	2	0	0
T9	12144	0	0	0
T24	0	4	0	0
T26	495	0	0	0
T34	656	0	0	0
T40	0	6	0	0
T41	0	2	0	0
T42	0	2	0	0
T45	0	4	0	0
T73	770	0	0	0
T78	495	0	0	0
T81	502	0	0	0
T82	422	0	0	0
T175	0	2	0	0
T201	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	84024	0	0
T6	659	72	0	0
T7	1131	78	0	0
T8	18107	56	0	0
T9	12144	0	0	0
T24	0	134	0	0
T26	495	0	0	0
T34	656	0	0	0
T40	0	179	0	0
T41	0	83	0	0
T42	0	43	0	0
T45	0	30	0	0
T73	770	0	0	0
T78	495	0	0	0
T81	502	0	0	0
T82	422	0	0	0
T175	0	12	0	0
T201	0	58	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8306858	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	2	0	0
T93	18580	1	0	0
T217	1009	0	0	0
T225	9991	0	0	0
T235	0	1	0	0
T236	812	0	0	0
T237	5268	0	0	0
T238	422	0	0	0
T239	533	0	0	0
T240	448	0	0	0
T241	675	0	0	0
T242	505	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	209527	0	0
T6	659	44	0	0
T7	1131	198	0	0
T8	18107	45	0	0
T9	12144	0	0	0
T24	0	338	0	0
T26	495	0	0	0
T34	656	0	0	0
T40	0	236	0	0
T41	0	136	0	0
T42	0	39	0	0
T45	0	78	0	0
T73	770	0	0	0
T78	495	0	0	0
T81	502	0	0	0
T82	422	0	0	0
T175	0	62	0	0
T201	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	57	0	0
T6	659	1	0	0
T7	1131	1	0	0
T8	18107	1	0	0
T9	12144	0	0	0
T24	0	2	0	0
T26	495	0	0	0
T34	656	0	0	0
T40	0	3	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	2	0	0
T73	770	0	0	0
T78	495	0	0	0
T81	502	0	0	0
T82	422	0	0	0
T175	0	1	0	0
T201	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	7953684	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	7956008	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	64	0	0
T6	659	1	0	0
T7	1131	1	0	0
T8	18107	1	0	0
T9	12144	0	0	0
T24	0	2	0	0
T26	495	0	0	0
T34	656	0	0	0
T40	0	3	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	2	0	0
T73	770	0	0	0
T78	495	0	0	0
T81	502	0	0	0
T82	422	0	0	0
T175	0	1	0	0
T201	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	59	0	0
T6	659	1	0	0
T7	1131	1	0	0
T8	18107	1	0	0
T9	12144	0	0	0
T24	0	2	0	0
T26	495	0	0	0
T34	656	0	0	0
T40	0	3	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	2	0	0
T73	770	0	0	0
T78	495	0	0	0
T81	502	0	0	0
T82	422	0	0	0
T175	0	1	0	0
T201	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	57	0	0
T6	659	1	0	0
T7	1131	1	0	0
T8	18107	1	0	0
T9	12144	0	0	0
T24	0	2	0	0
T26	495	0	0	0
T34	656	0	0	0
T40	0	3	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	2	0	0
T73	770	0	0	0
T78	495	0	0	0
T81	502	0	0	0
T82	422	0	0	0
T175	0	1	0	0
T201	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	57	0	0
T6	659	1	0	0
T7	1131	1	0	0
T8	18107	1	0	0
T9	12144	0	0	0
T24	0	2	0	0
T26	495	0	0	0
T34	656	0	0	0
T40	0	3	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	2	0	0
T73	770	0	0	0
T78	495	0	0	0
T81	502	0	0	0
T82	422	0	0	0
T175	0	1	0	0
T201	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	209441	0	0
T6	659	42	0	0
T7	1131	197	0	0
T8	18107	43	0	0
T9	12144	0	0	0
T24	0	335	0	0
T26	495	0	0	0
T34	656	0	0	0
T40	0	231	0	0
T41	0	134	0	0
T42	0	37	0	0
T45	0	75	0	0
T73	770	0	0	0
T78	495	0	0	0
T81	502	0	0	0
T82	422	0	0	0
T175	0	61	0	0
T201	0	39	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8309358	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	28	0	0
T7	1131	1	0	0
T8	18107	0	0	0
T9	12144	0	0	0
T10	32256	0	0	0
T24	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T71	319237	0	0	0
T78	495	0	0	0
T82	422	0	0	0
T93	0	1	0	0
T108	404	0	0	0
T143	409	0	0	0
T144	402	0	0	0
T175	0	1	0	0
T199	0	2	0	0
T217	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T40,T45,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T40,T45,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T40,T45,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T48
1	0	Covered	T5,T1,T16
1	1	Covered	T40,T45,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T40,T45,T46
0	1	Not Covered
1	0	Covered	T69

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T40,T45,T46
0	1	Covered	T40,T45,T217
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T40,T45,T46
1	-	Covered	T40,T45,T217

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T40,T45,T46
DetectSt	168	Covered	T40,T45,T46
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T40,T45,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T40,T45,T46
DebounceSt->IdleSt	163	Covered	T116,T200
DetectSt->IdleSt	186	Covered	T69
DetectSt->StableSt	191	Covered	T40,T45,T46
IdleSt->DebounceSt	148	Covered	T40,T45,T46
StableSt->IdleSt	206	Covered	T40,T45,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T40,T45,T46
0	1	Covered	T40,T45,T46
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T40,T45,T46
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T40,T45,T46
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T116
DebounceSt	-	0	1	1	-	-	-	Covered	T40,T45,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T200
DebounceSt	-	0	0	-	-	-	-	Covered	T40,T45,T46
DetectSt	-	-	-	-	1	-	-	Covered	T69
DetectSt	-	-	-	-	0	1	-	Covered	T40,T45,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T45,T217
StableSt	-	-	-	-	-	-	0	Covered	T40,T45,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8955184	49	0	0
CntIncr_A	8955184	91731	0	0
CntNoWrap_A	8955184	8306932	0	0
DetectStDropOut_A	8955184	0	0	0
DetectedOut_A	8955184	23137	0	0
DetectedPulseOut_A	8955184	22	0	0
DisabledIdleSt_A	8955184	7715918	0	0
DisabledNoDetection_A	8955184	7718254	0	0
EnterDebounceSt_A	8955184	26	0	0
EnterDetectSt_A	8955184	23	0	0
EnterStableSt_A	8955184	22	0	0
PulseIsPulse_A	8955184	22	0	0
StayInStableSt	8955184	23104	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8955184	6213	0	0
gen_low_level_sva.LowLevelEvent_A	8955184	8309358	0	0
gen_not_sticky_sva.StableStDropOut_A	8955184	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	49	0	0
T40	15100	2	0	0
T42	726	0	0	0
T45	0	2	0	0
T46	0	2	0	0
T69	0	2	0	0
T85	9381	0	0	0
T89	1192	0	0	0
T93	0	2	0	0
T152	675	0	0	0
T169	727	0	0	0
T170	633	0	0	0
T190	570	0	0	0
T197	0	6	0	0
T217	0	2	0	0
T243	0	4	0	0
T244	0	2	0	0
T245	0	2	0	0
T246	1462	0	0	0
T247	494	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	91731	0	0
T40	15100	78	0	0
T42	726	0	0	0
T45	0	15	0	0
T46	0	86	0	0
T69	0	43	0	0
T85	9381	0	0	0
T89	1192	0	0	0
T93	0	31	0	0
T152	675	0	0	0
T169	727	0	0	0
T170	633	0	0	0
T190	570	0	0	0
T197	0	60	0	0
T217	0	84	0	0
T243	0	24	0	0
T244	0	52	0	0
T245	0	31081	0	0
T246	1462	0	0	0
T247	494	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8306932	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	23137	0	0
T40	15100	241	0	0
T42	726	0	0	0
T45	0	4	0	0
T46	0	43	0	0
T85	9381	0	0	0
T89	1192	0	0	0
T93	0	59	0	0
T152	675	0	0	0
T169	727	0	0	0
T170	633	0	0	0
T190	570	0	0	0
T197	0	127	0	0
T198	0	42	0	0
T217	0	41	0	0
T243	0	89	0	0
T244	0	112	0	0
T245	0	21640	0	0
T246	1462	0	0	0
T247	494	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	22	0	0
T40	15100	1	0	0
T42	726	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T85	9381	0	0	0
T89	1192	0	0	0
T93	0	1	0	0
T152	675	0	0	0
T169	727	0	0	0
T170	633	0	0	0
T190	570	0	0	0
T197	0	3	0	0
T198	0	1	0	0
T217	0	1	0	0
T243	0	2	0	0
T244	0	1	0	0
T245	0	1	0	0
T246	1462	0	0	0
T247	494	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	7715918	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	7718254	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	26	0	0
T40	15100	1	0	0
T42	726	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T69	0	1	0	0
T85	9381	0	0	0
T89	1192	0	0	0
T93	0	1	0	0
T152	675	0	0	0
T169	727	0	0	0
T170	633	0	0	0
T190	570	0	0	0
T197	0	3	0	0
T217	0	1	0	0
T243	0	2	0	0
T244	0	1	0	0
T245	0	1	0	0
T246	1462	0	0	0
T247	494	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	23	0	0
T40	15100	1	0	0
T42	726	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T69	0	1	0	0
T85	9381	0	0	0
T89	1192	0	0	0
T93	0	1	0	0
T152	675	0	0	0
T169	727	0	0	0
T170	633	0	0	0
T190	570	0	0	0
T197	0	3	0	0
T217	0	1	0	0
T243	0	2	0	0
T244	0	1	0	0
T245	0	1	0	0
T246	1462	0	0	0
T247	494	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	22	0	0
T40	15100	1	0	0
T42	726	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T85	9381	0	0	0
T89	1192	0	0	0
T93	0	1	0	0
T152	675	0	0	0
T169	727	0	0	0
T170	633	0	0	0
T190	570	0	0	0
T197	0	3	0	0
T198	0	1	0	0
T217	0	1	0	0
T243	0	2	0	0
T244	0	1	0	0
T245	0	1	0	0
T246	1462	0	0	0
T247	494	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	22	0	0
T40	15100	1	0	0
T42	726	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T85	9381	0	0	0
T89	1192	0	0	0
T93	0	1	0	0
T152	675	0	0	0
T169	727	0	0	0
T170	633	0	0	0
T190	570	0	0	0
T197	0	3	0	0
T198	0	1	0	0
T217	0	1	0	0
T243	0	2	0	0
T244	0	1	0	0
T245	0	1	0	0
T246	1462	0	0	0
T247	494	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	23104	0	0
T40	15100	240	0	0
T42	726	0	0	0
T45	0	3	0	0
T46	0	41	0	0
T85	9381	0	0	0
T89	1192	0	0	0
T93	0	57	0	0
T152	675	0	0	0
T169	727	0	0	0
T170	633	0	0	0
T190	570	0	0	0
T197	0	123	0	0
T198	0	40	0	0
T217	0	40	0	0
T243	0	86	0	0
T244	0	110	0	0
T245	0	21638	0	0
T246	1462	0	0	0
T247	494	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	6213	0	0
T1	8953	12	0	0
T2	788	0	0	0
T3	38319	11	0	0
T5	38517	22	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	4	0	0
T17	454	5	0	0
T18	404	0	0	0
T19	0	4	0	0
T25	0	5	0	0
T26	0	6	0	0
T27	0	6	0	0
T81	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8309358	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	11	0	0
T40	15100	1	0	0
T42	726	0	0	0
T45	0	1	0	0
T85	9381	0	0	0
T89	1192	0	0	0
T152	675	0	0	0
T169	727	0	0	0
T170	633	0	0	0
T190	570	0	0	0
T197	0	2	0	0
T213	0	2	0	0
T217	0	1	0	0
T218	0	1	0	0
T228	0	1	0	0
T230	0	1	0	0
T243	0	1	0	0
T246	1462	0	0	0
T247	494	0	0	0