Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.41	97.83	90.48		100.00	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.41	97.83	90.48		100.00	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T50,T41,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T50,T41,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T50,T41,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T50,T41
1	0	Covered	T4,T5,T1
1	1	Covered	T50,T41,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T50,T41,T38
0	1	Covered	T39,T217,T229
1	0	Covered	T69

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T50,T41,T38
0	1	Covered	T41,T38,T48
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T50,T41,T38
1	-	Covered	T41,T38,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T50,T41,T38
DetectSt	168	Covered	T50,T41,T38
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T50,T41,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T50,T41,T38
DebounceSt->IdleSt	163	Covered	T211,T116,T248
DetectSt->IdleSt	186	Covered	T39,T217,T69
DetectSt->StableSt	191	Covered	T50,T41,T38
IdleSt->DebounceSt	148	Covered	T50,T41,T38
StableSt->IdleSt	206	Covered	T41,T38,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T50,T41,T38
0	1	Covered	T50,T41,T38
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T50,T41,T38
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T50,T41,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T116
DebounceSt	-	0	1	1	-	-	-	Covered	T50,T41,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T211,T248,T249
DebounceSt	-	0	0	-	-	-	-	Covered	T50,T41,T38
DetectSt	-	-	-	-	1	-	-	Covered	T39,T217,T69
DetectSt	-	-	-	-	0	1	-	Covered	T50,T41,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T41,T38,T48
StableSt	-	-	-	-	-	-	0	Covered	T50,T41,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8955184	127	0	0
CntIncr_A	8955184	103176	0	0
CntNoWrap_A	8955184	8306854	0	0
DetectStDropOut_A	8955184	3	0	0
DetectedOut_A	8955184	5283	0	0
DetectedPulseOut_A	8955184	57	0	0
DisabledIdleSt_A	8955184	8090548	0	0
DisabledNoDetection_A	8955184	8092872	0	0
EnterDebounceSt_A	8955184	66	0	0
EnterDetectSt_A	8955184	61	0	0
EnterStableSt_A	8955184	57	0	0
PulseIsPulse_A	8955184	57	0	0
StayInStableSt	8955184	5199	0	0
gen_high_level_sva.HighLevelEvent_A	8955184	8309358	0	0
gen_not_sticky_sva.StableStDropOut_A	8955184	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	127	0	0
T24	0	4	0	0
T38	1061	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	2749	2	0	0
T42	0	2	0	0
T45	0	4	0	0
T48	0	4	0	0
T50	477	2	0	0
T57	660	0	0	0
T58	2064	0	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T201	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	103176	0	0
T24	0	134	0	0
T38	1061	63	0	0
T39	0	86	0	0
T40	0	78	0	0
T41	2749	83	0	0
T42	0	43	0	0
T45	0	30	0	0
T48	0	150	0	0
T50	477	21	0	0
T57	660	0	0	0
T58	2064	0	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T201	0	58	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8306854	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	3	0	0
T24	264652	0	0	0
T39	625	1	0	0
T44	781	0	0	0
T52	10853	0	0	0
T62	32198	0	0	0
T217	0	1	0	0
T222	493	0	0	0
T223	44316	0	0	0
T229	0	1	0	0
T250	886	0	0	0
T251	1771	0	0	0
T252	444	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	5283	0	0
T24	0	443	0	0
T38	1061	144	0	0
T40	0	242	0	0
T41	2749	40	0	0
T42	0	109	0	0
T45	0	110	0	0
T48	0	217	0	0
T50	477	45	0	0
T57	660	0	0	0
T58	2064	0	0	0
T92	0	40	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T201	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	57	0	0
T24	0	2	0	0
T38	1061	1	0	0
T40	0	1	0	0
T41	2749	1	0	0
T42	0	1	0	0
T45	0	2	0	0
T48	0	2	0	0
T50	477	1	0	0
T57	660	0	0	0
T58	2064	0	0	0
T92	0	1	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T201	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8090548	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8092872	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	66	0	0
T24	0	2	0	0
T38	1061	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	2749	1	0	0
T42	0	1	0	0
T45	0	2	0	0
T48	0	2	0	0
T50	477	1	0	0
T57	660	0	0	0
T58	2064	0	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T201	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	61	0	0
T24	0	2	0	0
T38	1061	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	2749	1	0	0
T42	0	1	0	0
T45	0	2	0	0
T48	0	2	0	0
T50	477	1	0	0
T57	660	0	0	0
T58	2064	0	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T201	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	57	0	0
T24	0	2	0	0
T38	1061	1	0	0
T40	0	1	0	0
T41	2749	1	0	0
T42	0	1	0	0
T45	0	2	0	0
T48	0	2	0	0
T50	477	1	0	0
T57	660	0	0	0
T58	2064	0	0	0
T92	0	1	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T201	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	57	0	0
T24	0	2	0	0
T38	1061	1	0	0
T40	0	1	0	0
T41	2749	1	0	0
T42	0	1	0	0
T45	0	2	0	0
T48	0	2	0	0
T50	477	1	0	0
T57	660	0	0	0
T58	2064	0	0	0
T92	0	1	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T201	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	5199	0	0
T24	0	440	0	0
T38	1061	143	0	0
T40	0	241	0	0
T41	2749	39	0	0
T42	0	107	0	0
T45	0	108	0	0
T48	0	214	0	0
T50	477	43	0	0
T57	660	0	0	0
T58	2064	0	0	0
T92	0	38	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T201	0	39	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8309358	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	30	0	0
T24	0	1	0	0
T38	1061	1	0	0
T40	0	1	0	0
T41	2749	1	0	0
T45	0	2	0	0
T48	0	1	0	0
T58	2064	0	0	0
T70	19045	0	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0
T196	0	2	0	0
T199	0	1	0	0
T217	0	1	0	0
T226	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T38,T48,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T38,T48,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T38,T48,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T50,T38
1	0	Covered	T5,T1,T16
1	1	Covered	T38,T48,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T38,T39,T44
0	1	Covered	T48
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T38,T39,T44
0	1	Covered	T196,T176,T184
1	0	Covered	T69

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T38,T39,T44
1	-	Covered	T196,T176,T184

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T38,T48,T39
DetectSt	168	Covered	T38,T48,T39
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T38,T39,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T38,T48,T39
DebounceSt->IdleSt	163	Covered	T116,T200
DetectSt->IdleSt	186	Covered	T48
DetectSt->StableSt	191	Covered	T38,T39,T44
IdleSt->DebounceSt	148	Covered	T38,T48,T39
StableSt->IdleSt	206	Covered	T40,T196,T176

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T38,T48,T39
0	1	Covered	T38,T48,T39
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T38,T48,T39
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T38,T48,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T116
DebounceSt	-	0	1	1	-	-	-	Covered	T38,T48,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T200
DebounceSt	-	0	0	-	-	-	-	Covered	T38,T48,T39
DetectSt	-	-	-	-	1	-	-	Covered	T48
DetectSt	-	-	-	-	0	1	-	Covered	T38,T39,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T196,T176,T184
StableSt	-	-	-	-	-	-	0	Covered	T38,T39,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8955184	64	0	0
CntIncr_A	8955184	1744	0	0
CntNoWrap_A	8955184	8306917	0	0
DetectStDropOut_A	8955184	1	0	0
DetectedOut_A	8955184	1864	0	0
DetectedPulseOut_A	8955184	30	0	0
DisabledIdleSt_A	8955184	8154229	0	0
DisabledNoDetection_A	8955184	8156559	0	0
EnterDebounceSt_A	8955184	33	0	0
EnterDetectSt_A	8955184	31	0	0
EnterStableSt_A	8955184	30	0	0
PulseIsPulse_A	8955184	30	0	0
StayInStableSt	8955184	1818	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8955184	6187	0	0
gen_low_level_sva.LowLevelEvent_A	8955184	8309358	0	0
gen_not_sticky_sva.StableStDropOut_A	8955184	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	64	0	0
T29	9157	0	0	0
T38	1061	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T44	0	2	0	0
T48	3719	2	0	0
T58	2064	0	0	0
T70	19045	0	0	0
T176	0	4	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0
T184	0	4	0	0
T196	0	4	0	0
T199	0	2	0	0
T214	488	0	0	0
T215	526	0	0	0
T226	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	1744	0	0
T29	9157	0	0	0
T38	1061	63	0	0
T39	0	86	0	0
T40	0	23	0	0
T44	0	49	0	0
T48	3719	75	0	0
T58	2064	0	0	0
T70	19045	0	0	0
T176	0	52	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0
T184	0	108	0	0
T196	0	34	0	0
T199	0	25	0	0
T214	488	0	0	0
T215	526	0	0	0
T226	0	79	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8306917	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	1	0	0
T29	9157	0	0	0
T37	44323	0	0	0
T48	3719	1	0	0
T51	6409	0	0	0
T59	4966	0	0	0
T60	645	0	0	0
T76	946	0	0	0
T192	6214	0	0	0
T214	488	0	0	0
T215	526	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	1864	0	0
T29	9157	0	0	0
T38	1061	157	0	0
T39	0	43	0	0
T40	0	46	0	0
T44	0	135	0	0
T48	3719	0	0	0
T58	2064	0	0	0
T69	0	1	0	0
T70	19045	0	0	0
T176	0	127	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0
T184	0	46	0	0
T196	0	81	0	0
T199	0	4	0	0
T214	488	0	0	0
T215	526	0	0	0
T226	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	30	0	0
T29	9157	0	0	0
T38	1061	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T44	0	1	0	0
T48	3719	0	0	0
T58	2064	0	0	0
T69	0	1	0	0
T70	19045	0	0	0
T176	0	2	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0
T184	0	2	0	0
T196	0	2	0	0
T199	0	1	0	0
T214	488	0	0	0
T215	526	0	0	0
T226	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8154229	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8156559	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	33	0	0
T29	9157	0	0	0
T38	1061	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T44	0	1	0	0
T48	3719	1	0	0
T58	2064	0	0	0
T70	19045	0	0	0
T176	0	2	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0
T184	0	2	0	0
T196	0	2	0	0
T199	0	1	0	0
T214	488	0	0	0
T215	526	0	0	0
T226	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	31	0	0
T29	9157	0	0	0
T38	1061	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T44	0	1	0	0
T48	3719	1	0	0
T58	2064	0	0	0
T70	19045	0	0	0
T176	0	2	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0
T184	0	2	0	0
T196	0	2	0	0
T199	0	1	0	0
T214	488	0	0	0
T215	526	0	0	0
T226	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	30	0	0
T29	9157	0	0	0
T38	1061	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T44	0	1	0	0
T48	3719	0	0	0
T58	2064	0	0	0
T69	0	1	0	0
T70	19045	0	0	0
T176	0	2	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0
T184	0	2	0	0
T196	0	2	0	0
T199	0	1	0	0
T214	488	0	0	0
T215	526	0	0	0
T226	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	30	0	0
T29	9157	0	0	0
T38	1061	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T44	0	1	0	0
T48	3719	0	0	0
T58	2064	0	0	0
T69	0	1	0	0
T70	19045	0	0	0
T176	0	2	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0
T184	0	2	0	0
T196	0	2	0	0
T199	0	1	0	0
T214	488	0	0	0
T215	526	0	0	0
T226	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	1818	0	0
T29	9157	0	0	0
T38	1061	155	0	0
T39	0	41	0	0
T40	0	44	0	0
T44	0	133	0	0
T48	3719	0	0	0
T58	2064	0	0	0
T70	19045	0	0	0
T115	0	38	0	0
T176	0	124	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0
T184	0	44	0	0
T196	0	78	0	0
T199	0	3	0	0
T214	488	0	0	0
T215	526	0	0	0
T226	0	38	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	6187	0	0
T1	8953	11	0	0
T2	788	0	0	0
T3	38319	8	0	0
T5	38517	15	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	3	0	0
T17	454	7	0	0
T18	404	0	0	0
T19	0	3	0	0
T25	0	8	0	0
T26	0	9	0	0
T27	0	4	0	0
T81	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8309358	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	13	0	0
T93	18580	0	0	0
T115	0	1	0	0
T134	23863	0	0	0
T174	0	1	0	0
T176	0	1	0	0
T184	0	2	0	0
T196	587	1	0	0
T199	0	1	0	0
T226	0	1	0	0
T228	0	1	0	0
T236	812	0	0	0
T237	5268	0	0	0
T238	422	0	0	0
T253	0	1	0	0
T254	0	1	0	0
T255	427	0	0	0
T256	1330	0	0	0
T257	453	0	0	0
T258	505	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T49,T38,T48

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T49,T38,T48

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T49,T38,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T49,T38
1	0	Covered	T4,T5,T1
1	1	Covered	T49,T38,T48

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T49,T38,T48
0	1	Covered	T253
1	0	Covered	T69

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T49,T38,T48
0	1	Covered	T61,T24,T44
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T49,T38,T48
1	-	Covered	T61,T24,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T49,T38,T48
DetectSt	168	Covered	T49,T38,T48
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T49,T38,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T49,T38,T48
DebounceSt->IdleSt	163	Covered	T218,T116,T254
DetectSt->IdleSt	186	Covered	T69,T253
DetectSt->StableSt	191	Covered	T49,T38,T48
IdleSt->DebounceSt	148	Covered	T49,T38,T48
StableSt->IdleSt	206	Covered	T48,T47,T61

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T49,T38,T48
0	1	Covered	T49,T38,T48
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T49,T38,T48
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T49,T38,T48
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T116
DebounceSt	-	0	1	1	-	-	-	Covered	T49,T38,T48
DebounceSt	-	0	1	0	-	-	-	Covered	T218,T254,T248
DebounceSt	-	0	0	-	-	-	-	Covered	T49,T38,T48
DetectSt	-	-	-	-	1	-	-	Covered	T69,T253
DetectSt	-	-	-	-	0	1	-	Covered	T49,T38,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T61,T24,T44
StableSt	-	-	-	-	-	-	0	Covered	T49,T38,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8955184	128	0	0
CntIncr_A	8955184	193685	0	0
CntNoWrap_A	8955184	8306853	0	0
DetectStDropOut_A	8955184	1	0	0
DetectedOut_A	8955184	61332	0	0
DetectedPulseOut_A	8955184	60	0	0
DisabledIdleSt_A	8955184	7711210	0	0
DisabledNoDetection_A	8955184	7713531	0	0
EnterDebounceSt_A	8955184	66	0	0
EnterDetectSt_A	8955184	62	0	0
EnterStableSt_A	8955184	60	0	0
PulseIsPulse_A	8955184	60	0	0
StayInStableSt	8955184	61243	0	0
gen_high_level_sva.HighLevelEvent_A	8955184	8309358	0	0
gen_not_sticky_sva.StableStDropOut_A	8955184	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	128	0	0
T24	0	2	0	0
T35	2380	0	0	0
T38	0	2	0	0
T39	0	2	0	0
T41	2749	0	0	0
T42	0	4	0	0
T44	0	2	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	638	2	0	0
T50	477	0	0	0
T56	768	0	0	0
T57	660	0	0	0
T61	0	2	0	0
T75	1102	0	0	0
T127	12054	0	0	0
T177	422	0	0	0
T191	435	0	0	0
T201	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	193685	0	0
T24	0	67	0	0
T35	2380	0	0	0
T38	0	63	0	0
T39	0	86	0	0
T41	2749	0	0	0
T42	0	86	0	0
T44	0	49	0	0
T47	0	70	0	0
T48	0	75	0	0
T49	638	90	0	0
T50	477	0	0	0
T56	768	0	0	0
T57	660	0	0	0
T61	0	78	0	0
T75	1102	0	0	0
T127	12054	0	0	0
T177	422	0	0	0
T191	435	0	0	0
T201	0	58	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8306853	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	1	0	0
T159	55592	0	0	0
T253	660	1	0	0
T259	1960	0	0	0
T260	12404	0	0	0
T261	1308	0	0	0
T262	524	0	0	0
T263	534	0	0	0
T264	32778	0	0	0
T265	1932	0	0	0
T266	662	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	61332	0	0
T24	0	383	0	0
T35	2380	0	0	0
T38	0	366	0	0
T39	0	130	0	0
T41	2749	0	0	0
T42	0	61	0	0
T44	0	232	0	0
T47	0	112	0	0
T48	0	244	0	0
T49	638	138	0	0
T50	477	0	0	0
T56	768	0	0	0
T57	660	0	0	0
T61	0	42	0	0
T75	1102	0	0	0
T127	12054	0	0	0
T177	422	0	0	0
T191	435	0	0	0
T201	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	60	0	0
T24	0	1	0	0
T35	2380	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	2749	0	0	0
T42	0	2	0	0
T44	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	638	1	0	0
T50	477	0	0	0
T56	768	0	0	0
T57	660	0	0	0
T61	0	1	0	0
T75	1102	0	0	0
T127	12054	0	0	0
T177	422	0	0	0
T191	435	0	0	0
T201	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	7711210	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	7713531	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	66	0	0
T24	0	1	0	0
T35	2380	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	2749	0	0	0
T42	0	2	0	0
T44	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	638	1	0	0
T50	477	0	0	0
T56	768	0	0	0
T57	660	0	0	0
T61	0	1	0	0
T75	1102	0	0	0
T127	12054	0	0	0
T177	422	0	0	0
T191	435	0	0	0
T201	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	62	0	0
T24	0	1	0	0
T35	2380	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	2749	0	0	0
T42	0	2	0	0
T44	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	638	1	0	0
T50	477	0	0	0
T56	768	0	0	0
T57	660	0	0	0
T61	0	1	0	0
T75	1102	0	0	0
T127	12054	0	0	0
T177	422	0	0	0
T191	435	0	0	0
T201	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	60	0	0
T24	0	1	0	0
T35	2380	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	2749	0	0	0
T42	0	2	0	0
T44	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	638	1	0	0
T50	477	0	0	0
T56	768	0	0	0
T57	660	0	0	0
T61	0	1	0	0
T75	1102	0	0	0
T127	12054	0	0	0
T177	422	0	0	0
T191	435	0	0	0
T201	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	60	0	0
T24	0	1	0	0
T35	2380	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	2749	0	0	0
T42	0	2	0	0
T44	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	638	1	0	0
T50	477	0	0	0
T56	768	0	0	0
T57	660	0	0	0
T61	0	1	0	0
T75	1102	0	0	0
T127	12054	0	0	0
T177	422	0	0	0
T191	435	0	0	0
T201	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	61243	0	0
T24	0	382	0	0
T35	2380	0	0	0
T38	0	364	0	0
T39	0	128	0	0
T41	2749	0	0	0
T42	0	59	0	0
T44	0	231	0	0
T47	0	110	0	0
T48	0	242	0	0
T49	638	136	0	0
T50	477	0	0	0
T56	768	0	0	0
T57	660	0	0	0
T61	0	41	0	0
T75	1102	0	0	0
T127	12054	0	0	0
T177	422	0	0	0
T191	435	0	0	0
T201	0	39	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8309358	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	31	0	0
T24	264652	1	0	0
T39	625	0	0	0
T42	0	2	0	0
T44	781	1	0	0
T52	10853	0	0	0
T61	3859	1	0	0
T62	32198	0	0	0
T93	0	1	0	0
T115	0	1	0	0
T176	0	2	0	0
T185	0	1	0	0
T196	0	1	0	0
T220	0	1	0	0
T222	493	0	0	0
T223	44316	0	0	0
T250	886	0	0	0
T251	1771	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T41,T42,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T41,T42,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T41,T42,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T50,T41
1	0	Covered	T4,T5,T1
1	1	Covered	T41,T42,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T41,T42,T43
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T41,T42,T43
0	1	Covered	T42,T183,T267
1	0	Covered	T69

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T41,T42,T43
1	-	Covered	T42,T183,T267

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T41,T42,T43
DetectSt	168	Covered	T41,T42,T43
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T41,T42,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T41,T42,T43
DebounceSt->IdleSt	163	Covered	T116,T268
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T41,T42,T43
IdleSt->DebounceSt	148	Covered	T41,T42,T43
StableSt->IdleSt	206	Covered	T42,T93,T183

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T41,T42,T43
0	1	Covered	T41,T42,T43
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T41,T42,T43
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T116
DebounceSt	-	0	1	1	-	-	-	Covered	T41,T42,T43
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T41,T42,T43
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T41,T42,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T42,T183,T69
StableSt	-	-	-	-	-	-	0	Covered	T41,T42,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8955184	55	0	0
CntIncr_A	8955184	60952	0	0
CntNoWrap_A	8955184	8306926	0	0
DetectStDropOut_A	8955184	0	0	0
DetectedOut_A	8955184	1469	0	0
DetectedPulseOut_A	8955184	27	0	0
DisabledIdleSt_A	8955184	7915243	0	0
DisabledNoDetection_A	8955184	7917575	0	0
EnterDebounceSt_A	8955184	29	0	0
EnterDetectSt_A	8955184	27	0	0
EnterStableSt_A	8955184	27	0	0
PulseIsPulse_A	8955184	27	0	0
StayInStableSt	8955184	1425	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8955184	6163	0	0
gen_low_level_sva.LowLevelEvent_A	8955184	8309358	0	0
gen_not_sticky_sva.StableStDropOut_A	8955184	9	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	55	0	0
T38	1061	0	0	0
T41	2749	2	0	0
T42	0	4	0	0
T43	0	2	0	0
T58	2064	0	0	0
T69	0	2	0	0
T70	19045	0	0	0
T93	0	2	0	0
T115	0	2	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0
T183	0	2	0	0
T185	0	2	0	0
T217	0	2	0	0
T267	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	60952	0	0
T38	1061	0	0	0
T41	2749	83	0	0
T42	0	86	0	0
T43	0	68	0	0
T58	2064	0	0	0
T69	0	43	0	0
T70	19045	0	0	0
T93	0	11	0	0
T115	0	27	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0
T183	0	35	0	0
T185	0	73	0	0
T217	0	84	0	0
T267	0	44	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8306926	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	1469	0	0
T38	1061	0	0	0
T41	2749	135	0	0
T42	0	81	0	0
T43	0	39	0	0
T58	2064	0	0	0
T69	0	1	0	0
T70	19045	0	0	0
T93	0	74	0	0
T115	0	44	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0
T183	0	25	0	0
T185	0	117	0	0
T217	0	126	0	0
T267	0	60	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	27	0	0
T38	1061	0	0	0
T41	2749	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T58	2064	0	0	0
T69	0	1	0	0
T70	19045	0	0	0
T93	0	1	0	0
T115	0	1	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0
T183	0	1	0	0
T185	0	1	0	0
T217	0	1	0	0
T267	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	7915243	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	7917575	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	29	0	0
T38	1061	0	0	0
T41	2749	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T58	2064	0	0	0
T69	0	1	0	0
T70	19045	0	0	0
T93	0	1	0	0
T115	0	1	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0
T183	0	1	0	0
T185	0	1	0	0
T217	0	1	0	0
T267	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	27	0	0
T38	1061	0	0	0
T41	2749	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T58	2064	0	0	0
T69	0	1	0	0
T70	19045	0	0	0
T93	0	1	0	0
T115	0	1	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0
T183	0	1	0	0
T185	0	1	0	0
T217	0	1	0	0
T267	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	27	0	0
T38	1061	0	0	0
T41	2749	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T58	2064	0	0	0
T69	0	1	0	0
T70	19045	0	0	0
T93	0	1	0	0
T115	0	1	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0
T183	0	1	0	0
T185	0	1	0	0
T217	0	1	0	0
T267	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	27	0	0
T38	1061	0	0	0
T41	2749	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T58	2064	0	0	0
T69	0	1	0	0
T70	19045	0	0	0
T93	0	1	0	0
T115	0	1	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0
T183	0	1	0	0
T185	0	1	0	0
T217	0	1	0	0
T267	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	1425	0	0
T38	1061	0	0	0
T41	2749	133	0	0
T42	0	78	0	0
T43	0	37	0	0
T58	2064	0	0	0
T70	19045	0	0	0
T93	0	72	0	0
T115	0	42	0	0
T177	422	0	0	0
T178	504	0	0	0
T179	436	0	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0
T183	0	24	0	0
T185	0	115	0	0
T217	0	124	0	0
T267	0	57	0	0
T269	0	155	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	6163	0	0
T1	8953	8	0	0
T2	788	0	0	0
T3	38319	16	0	0
T5	38517	24	0	0
T13	402	0	0	0
T14	719	0	0	0
T15	2162	0	0	0
T16	426	2	0	0
T17	454	3	0	0
T18	404	0	0	0
T19	0	4	0	0
T25	0	4	0	0
T26	0	7	0	0
T27	0	6	0	0
T81	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8309358	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	9	0	0
T42	726	1	0	0
T101	10854	0	0	0
T153	731	0	0	0
T175	534	0	0	0
T183	0	1	0	0
T190	570	0	0	0
T211	0	1	0	0
T218	0	1	0	0
T228	0	1	0	0
T229	0	1	0	0
T267	0	1	0	0
T269	0	1	0	0
T270	0	1	0	0
T271	2461	0	0	0
T272	422	0	0	0
T273	430	0	0	0
T274	428	0	0	0
T275	497	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T49,T50

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T7,T49,T50

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T49,T50

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T49
1	0	Covered	T4,T5,T1
1	1	Covered	T7,T49,T50

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T49,T50
0	1	Covered	T260
1	0	Covered	T69

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T49,T50
0	1	Covered	T38,T61,T40
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T49,T50
1	-	Covered	T38,T61,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T49,T50
DetectSt	168	Covered	T7,T49,T50
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T7,T49,T50

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T49,T50
DebounceSt->IdleSt	163	Covered	T217,T185,T276
DetectSt->IdleSt	186	Covered	T69,T260
DetectSt->StableSt	191	Covered	T7,T49,T50
IdleSt->DebounceSt	148	Covered	T7,T49,T50
StableSt->IdleSt	206	Covered	T38,T47,T61

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T49,T50
0	1	Covered	T7,T49,T50
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T49,T50
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T49,T50
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T116
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T49,T50
DebounceSt	-	0	1	0	-	-	-	Covered	T217,T185,T276
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T49,T50
DetectSt	-	-	-	-	1	-	-	Covered	T69,T260
DetectSt	-	-	-	-	0	1	-	Covered	T7,T49,T50
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T38,T61,T40
StableSt	-	-	-	-	-	-	0	Covered	T7,T49,T50
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8955184	105	0	0
CntIncr_A	8955184	112409	0	0
CntNoWrap_A	8955184	8306876	0	0
DetectStDropOut_A	8955184	1	0	0
DetectedOut_A	8955184	118036	0	0
DetectedPulseOut_A	8955184	48	0	0
DisabledIdleSt_A	8955184	7851826	0	0
DisabledNoDetection_A	8955184	7854159	0	0
EnterDebounceSt_A	8955184	55	0	0
EnterDetectSt_A	8955184	50	0	0
EnterStableSt_A	8955184	48	0	0
PulseIsPulse_A	8955184	48	0	0
StayInStableSt	8955184	117964	0	0
gen_high_level_sva.HighLevelEvent_A	8955184	8309358	0	0
gen_not_sticky_sva.StableStDropOut_A	8955184	24	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	105	0	0
T7	1131	2	0	0
T8	18107	0	0	0
T9	12144	0	0	0
T10	32256	0	0	0
T38	0	2	0	0
T40	0	6	0	0
T44	0	2	0	0
T47	0	2	0	0
T49	0	2	0	0
T50	0	2	0	0
T61	0	4	0	0
T71	319237	0	0	0
T78	495	0	0	0
T82	422	0	0	0
T92	0	2	0	0
T108	404	0	0	0
T143	409	0	0	0
T144	402	0	0	0
T220	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	112409	0	0
T7	1131	78	0	0
T8	18107	0	0	0
T9	12144	0	0	0
T10	32256	0	0	0
T38	0	63	0	0
T40	0	179	0	0
T44	0	49	0	0
T47	0	70	0	0
T49	0	90	0	0
T50	0	21	0	0
T61	0	156	0	0
T71	319237	0	0	0
T78	495	0	0	0
T82	422	0	0	0
T92	0	66	0	0
T108	404	0	0	0
T143	409	0	0	0
T144	402	0	0	0
T220	0	35	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8306876	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	1	0	0
T159	55592	0	0	0
T260	12404	1	0	0
T261	1308	0	0	0
T262	524	0	0	0
T263	534	0	0	0
T264	32778	0	0	0
T265	1932	0	0	0
T266	662	0	0	0
T277	670	0	0	0
T278	652	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	118036	0	0
T7	1131	643	0	0
T8	18107	0	0	0
T9	12144	0	0	0
T10	32256	0	0	0
T38	0	366	0	0
T40	0	87	0	0
T44	0	322	0	0
T47	0	111	0	0
T49	0	42	0	0
T50	0	46	0	0
T61	0	81	0	0
T71	319237	0	0	0
T78	495	0	0	0
T82	422	0	0	0
T92	0	41	0	0
T108	404	0	0	0
T143	409	0	0	0
T144	402	0	0	0
T220	0	90	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	48	0	0
T7	1131	1	0	0
T8	18107	0	0	0
T9	12144	0	0	0
T10	32256	0	0	0
T38	0	1	0	0
T40	0	3	0	0
T44	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T61	0	2	0	0
T71	319237	0	0	0
T78	495	0	0	0
T82	422	0	0	0
T92	0	1	0	0
T108	404	0	0	0
T143	409	0	0	0
T144	402	0	0	0
T220	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	7851826	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	7854159	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	55	0	0
T7	1131	1	0	0
T8	18107	0	0	0
T9	12144	0	0	0
T10	32256	0	0	0
T38	0	1	0	0
T40	0	3	0	0
T44	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T61	0	2	0	0
T71	319237	0	0	0
T78	495	0	0	0
T82	422	0	0	0
T92	0	1	0	0
T108	404	0	0	0
T143	409	0	0	0
T144	402	0	0	0
T220	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	50	0	0
T7	1131	1	0	0
T8	18107	0	0	0
T9	12144	0	0	0
T10	32256	0	0	0
T38	0	1	0	0
T40	0	3	0	0
T44	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T61	0	2	0	0
T71	319237	0	0	0
T78	495	0	0	0
T82	422	0	0	0
T92	0	1	0	0
T108	404	0	0	0
T143	409	0	0	0
T144	402	0	0	0
T220	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	48	0	0
T7	1131	1	0	0
T8	18107	0	0	0
T9	12144	0	0	0
T10	32256	0	0	0
T38	0	1	0	0
T40	0	3	0	0
T44	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T61	0	2	0	0
T71	319237	0	0	0
T78	495	0	0	0
T82	422	0	0	0
T92	0	1	0	0
T108	404	0	0	0
T143	409	0	0	0
T144	402	0	0	0
T220	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	48	0	0
T7	1131	1	0	0
T8	18107	0	0	0
T9	12144	0	0	0
T10	32256	0	0	0
T38	0	1	0	0
T40	0	3	0	0
T44	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T61	0	2	0	0
T71	319237	0	0	0
T78	495	0	0	0
T82	422	0	0	0
T92	0	1	0	0
T108	404	0	0	0
T143	409	0	0	0
T144	402	0	0	0
T220	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	117964	0	0
T7	1131	641	0	0
T8	18107	0	0	0
T9	12144	0	0	0
T10	32256	0	0	0
T38	0	365	0	0
T40	0	83	0	0
T44	0	320	0	0
T47	0	109	0	0
T49	0	40	0	0
T50	0	44	0	0
T61	0	78	0	0
T71	319237	0	0	0
T78	495	0	0	0
T82	422	0	0	0
T92	0	39	0	0
T108	404	0	0	0
T143	409	0	0	0
T144	402	0	0	0
T220	0	89	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8309358	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	24	0	0
T29	9157	0	0	0
T38	1061	1	0	0
T40	0	2	0	0
T48	3719	0	0	0
T58	2064	0	0	0
T61	0	1	0	0
T70	19045	0	0	0
T176	0	2	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0
T185	0	1	0	0
T196	0	1	0	0
T197	0	1	0	0
T199	0	1	0	0
T214	488	0	0	0
T215	526	0	0	0
T217	0	1	0	0
T220	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T38,T39,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T38,T39,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T38,T39,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T4,T5,T1
1	1	Covered	T38,T39,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T38,T39,T40
0	1	Not Covered
1	0	Covered	T69

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T38,T39,T40
0	1	Covered	T40,T190,T175
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T38,T39,T40
1	-	Covered	T40,T190,T175

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T38,T39,T40
DetectSt	168	Covered	T38,T39,T40
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T38,T39,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T38,T39,T40
DebounceSt->IdleSt	163	Covered	T116
DetectSt->IdleSt	186	Covered	T69
DetectSt->StableSt	191	Covered	T38,T39,T40
IdleSt->DebounceSt	148	Covered	T38,T39,T40
StableSt->IdleSt	206	Covered	T40,T190,T175

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T38,T39,T40
0	1	Covered	T38,T39,T40
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T38,T39,T40
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T116
DebounceSt	-	0	1	1	-	-	-	Covered	T38,T39,T40
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T38,T39,T40
DetectSt	-	-	-	-	1	-	-	Covered	T69
DetectSt	-	-	-	-	0	1	-	Covered	T38,T39,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T190,T175
StableSt	-	-	-	-	-	-	0	Covered	T38,T39,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8955184	61	0	0
CntIncr_A	8955184	60847	0	0
CntNoWrap_A	8955184	8306920	0	0
DetectStDropOut_A	8955184	0	0	0
DetectedOut_A	8955184	2013	0	0
DetectedPulseOut_A	8955184	29	0	0
DisabledIdleSt_A	8955184	7712365	0	0
DisabledNoDetection_A	8955184	7714692	0	0
EnterDebounceSt_A	8955184	31	0	0
EnterDetectSt_A	8955184	30	0	0
EnterStableSt_A	8955184	29	0	0
PulseIsPulse_A	8955184	29	0	0
StayInStableSt	8955184	1968	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8955184	6852	0	0
gen_low_level_sva.LowLevelEvent_A	8955184	8309358	0	0
gen_not_sticky_sva.StableStDropOut_A	8955184	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	61	0	0
T29	9157	0	0	0
T38	1061	2	0	0
T39	0	2	0	0
T40	0	4	0	0
T48	3719	0	0	0
T58	2064	0	0	0
T70	19045	0	0	0
T93	0	2	0	0
T175	0	2	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0
T190	0	2	0	0
T196	0	2	0	0
T214	488	0	0	0
T215	526	0	0	0
T217	0	4	0	0
T220	0	2	0	0
T243	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	60847	0	0
T29	9157	0	0	0
T38	1061	63	0	0
T39	0	86	0	0
T40	0	156	0	0
T48	3719	0	0	0
T58	2064	0	0	0
T70	19045	0	0	0
T93	0	31	0	0
T175	0	12	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0
T190	0	18	0	0
T196	0	17	0	0
T214	488	0	0	0
T215	526	0	0	0
T217	0	168	0	0
T220	0	35	0	0
T243	0	24	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8306920	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	2013	0	0
T29	9157	0	0	0
T38	1061	42	0	0
T39	0	42	0	0
T40	0	311	0	0
T48	3719	0	0	0
T58	2064	0	0	0
T70	19045	0	0	0
T93	0	41	0	0
T175	0	47	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0
T190	0	40	0	0
T196	0	133	0	0
T214	488	0	0	0
T215	526	0	0	0
T217	0	133	0	0
T220	0	84	0	0
T243	0	109	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	29	0	0
T29	9157	0	0	0
T38	1061	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T48	3719	0	0	0
T58	2064	0	0	0
T70	19045	0	0	0
T93	0	1	0	0
T175	0	1	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0
T190	0	1	0	0
T196	0	1	0	0
T214	488	0	0	0
T215	526	0	0	0
T217	0	2	0	0
T220	0	1	0	0
T243	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	7712365	0	0
T1	8953	8545	0	0
T2	788	387	0	0
T4	407	6	0	0
T5	38517	36005	0	0
T13	402	1	0	0
T14	719	318	0	0
T15	2162	1761	0	0
T16	426	25	0	0
T17	454	53	0	0
T18	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	7714692	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	31	0	0
T29	9157	0	0	0
T38	1061	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T48	3719	0	0	0
T58	2064	0	0	0
T70	19045	0	0	0
T93	0	1	0	0
T175	0	1	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0
T190	0	1	0	0
T196	0	1	0	0
T214	488	0	0	0
T215	526	0	0	0
T217	0	2	0	0
T220	0	1	0	0
T243	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	30	0	0
T29	9157	0	0	0
T38	1061	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T48	3719	0	0	0
T58	2064	0	0	0
T70	19045	0	0	0
T93	0	1	0	0
T175	0	1	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0
T190	0	1	0	0
T196	0	1	0	0
T214	488	0	0	0
T215	526	0	0	0
T217	0	2	0	0
T220	0	1	0	0
T243	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	29	0	0
T29	9157	0	0	0
T38	1061	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T48	3719	0	0	0
T58	2064	0	0	0
T70	19045	0	0	0
T93	0	1	0	0
T175	0	1	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0
T190	0	1	0	0
T196	0	1	0	0
T214	488	0	0	0
T215	526	0	0	0
T217	0	2	0	0
T220	0	1	0	0
T243	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	29	0	0
T29	9157	0	0	0
T38	1061	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T48	3719	0	0	0
T58	2064	0	0	0
T70	19045	0	0	0
T93	0	1	0	0
T175	0	1	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0
T190	0	1	0	0
T196	0	1	0	0
T214	488	0	0	0
T215	526	0	0	0
T217	0	2	0	0
T220	0	1	0	0
T243	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	1968	0	0
T29	9157	0	0	0
T38	1061	40	0	0
T39	0	40	0	0
T40	0	308	0	0
T48	3719	0	0	0
T58	2064	0	0	0
T70	19045	0	0	0
T93	0	40	0	0
T175	0	46	0	0
T180	420	0	0	0
T181	448	0	0	0
T182	493	0	0	0
T190	0	39	0	0
T196	0	131	0	0
T214	488	0	0	0
T215	526	0	0	0
T217	0	130	0	0
T220	0	82	0	0
T243	0	106	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	6852	0	0
T1	8953	10	0	0
T2	788	4	0	0
T3	38319	12	0	0
T5	38517	17	0	0
T13	402	0	0	0
T14	719	3	0	0
T15	2162	9	0	0
T16	426	3	0	0
T17	454	6	0	0
T18	404	0	0	0
T19	0	6	0	0
T25	0	8	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	8309358	0	0
T1	8953	8547	0	0
T2	788	388	0	0
T4	407	7	0	0
T5	38517	36025	0	0
T13	402	2	0	0
T14	719	319	0	0
T15	2162	1762	0	0
T16	426	26	0	0
T17	454	54	0	0
T18	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8955184	13	0	0
T40	15100	1	0	0
T42	726	0	0	0
T85	9381	0	0	0
T89	1192	0	0	0
T93	0	1	0	0
T152	675	0	0	0
T169	727	0	0	0
T170	633	0	0	0
T174	0	1	0	0
T175	0	1	0	0
T184	0	1	0	0
T190	570	1	0	0
T197	0	1	0	0
T217	0	1	0	0
T243	0	1	0	0
T246	1462	0	0	0
T247	494	0	0	0
T260	0	1	0	0