Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2037

1

T4

22

T2

25

T10

15

auto[1]

544

1

T4

2

T10

7

T11

6

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1924

1

T4

21

T2

25

T10

9

auto[1]

657

1

T4

3

T10

13

T11

9

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2035

1

T4

19

T2

13

T10

20

auto[1]

546

1

T4

5

T2

12

T10

2

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1928

1

T4

22

T2

25

T10

18

auto[1]

653

1

T4

2

T10

4

T31

8

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2357

1

T4

16

T2

25

T10

22

auto[1]

224

1

T4

8

T44

1

T32

2

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2402

1

T4

22

T2

25

T10

22

auto[1]

179

1

T4

2

T32

2

T34

3

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2404

1

T4

19

T2

25

T10

22

auto[1]

177

1

T4

5

T32

5

T33

1

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2364

1

T4

24

T2

25

T10

22

auto[1]

217

1

T32

4

T45

5

T33

4

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2389

1

T4

24

T2

25

T10

22

auto[1]

192

1

T44

3

T32

7

T45

5

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2052

1

T4

21

T2

12

T10

15

auto[1]

529

1

T4

3

T2

13

T10

7

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	949	1			T2	25		T10	22		T11	9
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	85	1			T4	5		T33	7		T245	12
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	71	1			T44	2		T32	7		T33	6
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	30	1			T44	1		T245	9		T137	2
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	71	1			T34	5		T194	2		T247	7
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	21	1			T32	2		T79	2		T340	8
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	26	1			T33	4		T247	4		T261	6
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	5	1			T45	5		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	78	1			T32	5		T33	1		T245	10
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	9	1			T4	3		T34	1		T75	1
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	6	1			T248	5		T341	1		-	-
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	2	1			T342	2		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	21	1			T343	10		T335	3		T344	8
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	6	1			T345	2		T344	3		T346	1
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	4	1			T75	3		T80	1		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	58	1			T192	11		T343	9		T347	7
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	31	1			T192	2		T247	2		T137	2
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	11	1			T192	8		T194	1		T348	1
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	5	1			T192	2		T343	2		T349	1
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	31	1			T32	2		T34	3		T92	6
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	4	1			T350	4		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	3	1			T351	3		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	7	1			T4	2		T79	3		T76	2
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	2	1			T76	2		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	10	1			T352	2		T353	8		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	5	1			T80	3		T333	2		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

94

1

T33

1

T89

7

T112

10

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

102

1

T2

13

T250

14

T92

6

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

57

1

T10

5

T79

3

T42

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

130

1

T32

7

T33

7

T34

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

91

1

T4

2

T31

2

T292

7

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

69

1

T10

2

T30

4

T242

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

18

1

T95

2

T227

2

T117

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

128

1

T4

5

T2

12

T33

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

40

1

T34

3

T198

4

T161

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

46

1

T32

4

T34

5

T264

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

28

1

T250

1

T172

5

T229

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

67

1

T30

3

T111

7

T112

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

31

1

T10

2

T194

1

T215

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

14

1

T49

1

T137

3

T354

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

20

1

T251

1

T172

2

T347

7

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

244

1

T10

13

T44

1

T45

5

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

57

1

T112

6

T138

1

T261

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

50

1

T4

3

T32

5

T95

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

23

1

T11

4

T245

10

T355

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

92

1

T31

6

T154

6

T97

8

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

7

1

T126

1

T356

2

T98

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

9

1

T242

4

T126

1

T357

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

2

1

T229

1

T85

1

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

25

1

T255

4

T265

5

T358

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

7

1

T44

2

T359

4

T360

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

27

1

T11

3

T112

2

T328

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

8

1

T11

2

T96

1

T266

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

27

1

T33

6

T179

5

T292

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

10

1

T39

1

T77

1

T347

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

19

1

T245

12

T98

1

T101

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

9

1

T251

1

T331

1

T361

4

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded