Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

939

1

T9

17

T67

6

T68

11

auto[1]

903

1

T9

23

T67

14

T68

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

445

1

T9

8

T67

6

T68

5

from_0to1

449

1

T9

7

T67

6

T68

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

960

1

T9

22

T67

13

T68

9

auto[1]

882

1

T9

18

T67

7

T68

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

917

1

T9

17

T67

7

T68

9

auto[1]

925

1

T9

23

T67

13

T68

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T9

1

T68

1

T39

2

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T67

1

T68

1

T39

1

auto[0]

from_1to0

auto[1]

auto[0]

43

1

T67

1

T68

1

T69

1

auto[0]

from_1to0

auto[1]

auto[1]

55

1

T9

2

T39

1

T191

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T9

2

T68

1

T39

1

auto[0]

from_0to1

auto[0]

auto[1]

52

1

T9

2

T67

1

T68

1

auto[0]

from_0to1

auto[1]

auto[0]

73

1

T9

1

T67

1

T68

1

auto[0]

from_0to1

auto[1]

auto[1]

53

1

T9

1

T39

1

T372

1

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T9

1

T67

1

T69

1

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T9

1

T69

4

T191

2

auto[1]

from_1to0

auto[1]

auto[0]

57

1

T9

2

T67

1

T68

1

auto[1]

from_1to0

auto[1]

auto[1]

43

1

T9

1

T67

2

T68

1

auto[1]

from_0to1

auto[0]

auto[0]

50

1

T67

1

T39

2

T69

2

auto[1]

from_0to1

auto[0]

auto[1]

56

1

T67

3

T39

1

T69

1

auto[1]

from_0to1

auto[1]

auto[0]

50

1

T68

1

T39

1

T191

1

auto[1]

from_0to1

auto[1]

auto[1]

52

1

T9

1

T68

1

T59

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

909

1

T9

19

T67

11

T68

12

auto[1]

933

1

T9

21

T67

9

T68

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

449

1

T9

7

T67

4

T68

5

from_0to1

439

1

T9

8

T67

3

T68

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

974

1

T9

16

T67

12

T68

9

auto[1]

868

1

T9

24

T67

8

T68

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

971

1

T9

18

T67

16

T68

15

auto[1]

871

1

T9

22

T67

4

T68

5

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

49

1

T69

1

T373

1

T298

1

auto[0]

from_1to0

auto[0]

auto[1]

58

1

T68

1

T69

1

T191

1

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T9

2

T68

1

T191

1

auto[0]

from_1to0

auto[1]

auto[1]

46

1

T9

1

T68

1

T39

2

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T9

2

T67

1

T68

2

auto[0]

from_0to1

auto[0]

auto[1]

51

1

T67

1

T69

1

T59

1

auto[0]

from_0to1

auto[1]

auto[0]

45

1

T68

2

T39

2

T372

1

auto[0]

from_0to1

auto[1]

auto[1]

43

1

T9

2

T68

1

T39

1

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T9

1

T67

2

T69

1

auto[1]

from_1to0

auto[0]

auto[1]

49

1

T67

1

T39

1

T372

1

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T67

1

T68

2

T39

1

auto[1]

from_1to0

auto[1]

auto[1]

50

1

T9

3

T191

1

T298

2

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T9

1

T67

1

T191

1

auto[1]

from_0to1

auto[0]

auto[1]

53

1

T9

1

T39

1

T59

1

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T9

1

T372

1

T191

1

auto[1]

from_0to1

auto[1]

auto[1]

54

1

T9

1

T68

1

T39

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

948

1

T9

16

T67

7

T68

12

auto[1]

894

1

T9

24

T67

13

T68

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

436

1

T9

11

T67

4

T68

7

from_0to1

440

1

T9

10

T67

5

T68

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

914

1

T9

25

T67

10

T68

9

auto[1]

928

1

T9

15

T67

10

T68

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

926

1

T9

26

T67

9

T68

10

auto[1]

916

1

T9

14

T67

11

T68

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

67

1

T9

2

T68

1

T39

3

auto[0]

from_1to0

auto[0]

auto[1]

53

1

T9

2

T67

1

T68

2

auto[0]

from_1to0

auto[1]

auto[0]

50

1

T69

2

T297

2

T142

1

auto[0]

from_1to0

auto[1]

auto[1]

58

1

T9

1

T68

1

T39

2

auto[0]

from_0to1

auto[0]

auto[0]

58

1

T67

1

T68

1

T372

1

auto[0]

from_0to1

auto[0]

auto[1]

53

1

T67

1

T68

1

T39

1

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T9

3

T67

1

T68

2

auto[0]

from_0to1

auto[1]

auto[1]

51

1

T9

2

T39

1

T372

2

auto[1]

from_1to0

auto[0]

auto[0]

49

1

T9

1

T68

1

T372

2

auto[1]

from_1to0

auto[0]

auto[1]

49

1

T9

1

T67

2

T69

1

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T9

4

T67

1

T68

1

auto[1]

from_1to0

auto[1]

auto[1]

50

1

T68

1

T39

1

T59

1

auto[1]

from_0to1

auto[0]

auto[0]

51

1

T9

4

T67

1

T68

1

auto[1]

from_0to1

auto[0]

auto[1]

67

1

T9

1

T67

1

T191

1

auto[1]

from_0to1

auto[1]

auto[0]

50

1

T39

1

T372

1

T87

2

auto[1]

from_0to1

auto[1]

auto[1]

46

1

T68

2

T39

1

T69

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

870

1

T9

22

T67

9

T68

9

auto[1]

972

1

T9

18

T67

11

T68

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

437

1

T9

11

T67

4

T68

4

from_0to1

434

1

T9

12

T67

4

T68

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

940

1

T9

21

T67

8

T68

11

auto[1]

902

1

T9

19

T67

12

T68

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

939

1

T9

19

T67

12

T68

7

auto[1]

903

1

T9

21

T67

8

T68

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

51

1

T67

1

T69

1

T191

1

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T9

1

T69

2

T372

1

auto[0]

from_1to0

auto[1]

auto[0]

46

1

T9

1

T68

1

T69

2

auto[0]

from_1to0

auto[1]

auto[1]

54

1

T9

2

T67

1

T68

1

auto[0]

from_0to1

auto[0]

auto[0]

52

1

T9

2

T39

1

T69

1

auto[0]

from_0to1

auto[0]

auto[1]

53

1

T69

1

T178

1

T297

1

auto[0]

from_0to1

auto[1]

auto[0]

40

1

T9

2

T67

1

T69

1

auto[0]

from_0to1

auto[1]

auto[1]

55

1

T9

1

T67

1

T68

1

auto[1]

from_1to0

auto[0]

auto[0]

55

1

T9

3

T67

1

T68

1

auto[1]

from_1to0

auto[0]

auto[1]

63

1

T39

1

T372

1

T59

3

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T9

2

T191

1

T178

1

auto[1]

from_1to0

auto[1]

auto[1]

46

1

T9

2

T67

1

T68

1

auto[1]

from_0to1

auto[0]

auto[0]

56

1

T9

1

T67

1

T39

1

auto[1]

from_0to1

auto[0]

auto[1]

59

1

T9

3

T68

3

T39

1

auto[1]

from_0to1

auto[1]

auto[0]

62

1

T9

2

T67

1

T69

2

auto[1]

from_0to1

auto[1]

auto[1]

57

1

T9

1

T39

1

T69

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

925

1

T9

25

T67

7

T68

6

auto[1]

917

1

T9

15

T67

13

T68

14

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

448

1

T9

9

T67

5

T68

4

from_0to1

446

1

T9

10

T67

5

T68

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

906

1

T9

21

T67

10

T68

8

auto[1]

936

1

T9

19

T67

10

T68

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

910

1

T9

17

T67

11

T68

12

auto[1]

932

1

T9

23

T67

9

T68

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

52

1

T9

1

T191

1

T297

1

auto[0]

from_1to0

auto[0]

auto[1]

44

1

T9

1

T67

1

T68

1

auto[0]

from_1to0

auto[1]

auto[0]

54

1

T68

1

T39

1

T372

2

auto[0]

from_1to0

auto[1]

auto[1]

73

1

T9

3

T67

1

T69

2

auto[0]

from_0to1

auto[0]

auto[0]

76

1

T9

1

T67

2

T69

1

auto[0]

from_0to1

auto[0]

auto[1]

56

1

T9

1

T68

2

T69

1

auto[0]

from_0to1

auto[1]

auto[0]

39

1

T9

1

T69

2

T372

1

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T9

4

T68

1

T39

1

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T9

2

T67

1

T68

1

auto[1]

from_1to0

auto[0]

auto[1]

54

1

T9

1

T67

1

T39

1

auto[1]

from_1to0

auto[1]

auto[0]

52

1

T191

1

T59

1

T178

1

auto[1]

from_1to0

auto[1]

auto[1]

61

1

T9

1

T67

1

T68

1

auto[1]

from_0to1

auto[0]

auto[0]

51

1

T9

1

T67

1

T68

1

auto[1]

from_0to1

auto[0]

auto[1]

55

1

T68

1

T39

1

T372

1

auto[1]

from_0to1

auto[1]

auto[0]

53

1

T9

2

T67

1

T39

1

auto[1]

from_0to1

auto[1]

auto[1]

51

1

T67

1

T39

1

T191

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

948

1

T9

16

T67

10

T68

9

auto[1]

894

1

T9

24

T67

10

T68

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

431

1

T9

11

T67

6

T68

3

from_0to1

433

1

T9

11

T67

6

T68

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

914

1

T9

23

T67

10

T68

9

auto[1]

928

1

T9

17

T67

10

T68

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

900

1

T9

20

T67

10

T68

12

auto[1]

942

1

T9

20

T67

10

T68

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

60

1

T9

1

T67

2

T191

1

auto[0]

from_1to0

auto[0]

auto[1]

48

1

T9

3

T67

2

T68

1

auto[0]

from_1to0

auto[1]

auto[0]

49

1

T9

1

T67

1

T68

1

auto[0]

from_1to0

auto[1]

auto[1]

68

1

T69

1

T372

3

T191

2

auto[0]

from_0to1

auto[0]

auto[0]

54

1

T68

1

T69

1

T87

2

auto[0]

from_0to1

auto[0]

auto[1]

52

1

T9

1

T178

1

T297

1

auto[0]

from_0to1

auto[1]

auto[0]

56

1

T67

1

T68

1

T39

1

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T9

1

T67

1

T178

2

auto[1]

from_1to0

auto[0]

auto[0]

49

1

T9

3

T68

1

T39

1

auto[1]

from_1to0

auto[0]

auto[1]

58

1

T67

1

T59

2

T178

1

auto[1]

from_1to0

auto[1]

auto[0]

40

1

T39

1

T69

1

T372

1

auto[1]

from_1to0

auto[1]

auto[1]

59

1

T9

3

T39

1

T69

1

auto[1]

from_0to1

auto[0]

auto[0]

49

1

T9

3

T372

1

T191

1

auto[1]

from_0to1

auto[0]

auto[1]

48

1

T9

2

T67

2

T68

1

auto[1]

from_0to1

auto[1]

auto[0]

51

1

T9

1

T39

1

T372

2

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T9

3

T67

2

T68

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

923

1

T9

24

T67

8

T68

12

auto[1]

919

1

T9

16

T67

12

T68

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

444

1

T9

10

T67

6

T68

4

from_0to1

448

1

T9

10

T67

6

T68

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

922

1

T9

21

T67

8

T68

11

auto[1]

920

1

T9

19

T67

12

T68

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

940

1

T9

21

T67

6

T68

8

auto[1]

902

1

T9

19

T67

14

T68

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

58

1

T9

4

T67

1

T191

1

auto[0]

from_1to0

auto[0]

auto[1]

50

1

T9

1

T39

2

T178

1

auto[0]

from_1to0

auto[1]

auto[0]

44

1

T9

2

T69

1

T59

1

auto[0]

from_1to0

auto[1]

auto[1]

46

1

T67

1

T39

2

T69

1

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T9

2

T67

1

T298

1

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T9

1

T68

2

T39

1

auto[0]

from_0to1

auto[1]

auto[0]

53

1

T68

2

T69

1

T372

1

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T9

2

T67

1

T39

2

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T67

1

T59

1

T178

1

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T67

2

T68

2

T39

1

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T9

2

T68

1

T39

1

auto[1]

from_1to0

auto[1]

auto[1]

55

1

T9

1

T67

1

T68

1

auto[1]

from_0to1

auto[0]

auto[0]

56

1

T39

1

T191

3

T87

1

auto[1]

from_0to1

auto[0]

auto[1]

45

1

T9

1

T59

1

T178

1

auto[1]

from_0to1

auto[1]

auto[0]

52

1

T9

2

T67

2

T39

1

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T9

2

T67

2

T39

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

928

1

T9

25

T67

10

T68

14

auto[1]

914

1

T9

15

T67

10

T68

6

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

428

1

T9

12

T67

2

T68

5

from_0to1

427

1

T9

11

T67

2

T68

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

918

1

T9

21

T67

8

T68

10

auto[1]

924

1

T9

19

T67

12

T68

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

931

1

T9

19

T67

13

T68

8

auto[1]

911

1

T9

21

T67

7

T68

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T9

2

T39

1

T178

1

auto[0]

from_1to0

auto[0]

auto[1]

52

1

T9

4

T68

1

T372

1

auto[0]

from_1to0

auto[1]

auto[0]

55

1

T9

3

T68

2

T39

1

auto[0]

from_1to0

auto[1]

auto[1]

51

1

T9

1

T68

1

T39

1

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T9

2

T67

1

T68

1

auto[0]

from_0to1

auto[0]

auto[1]

54

1

T9

1

T68

2

T69

2

auto[0]

from_0to1

auto[1]

auto[0]

49

1

T9

3

T39

1

T59

2

auto[0]

from_0to1

auto[1]

auto[1]

43

1

T9

1

T372

2

T191

4

auto[1]

from_1to0

auto[0]

auto[0]

47

1

T67

2

T39

1

T59

1

auto[1]

from_1to0

auto[0]

auto[1]

42

1

T9

1

T69

2

T191

1

auto[1]

from_1to0

auto[1]

auto[0]

64

1

T69

1

T372

2

T178

1

auto[1]

from_1to0

auto[1]

auto[1]

58

1

T9

1

T68

1

T69

1

auto[1]

from_0to1

auto[0]

auto[0]

61

1

T9

1

T67

1

T68

1

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T9

1

T39

2

T69

2

auto[1]

from_0to1

auto[1]

auto[0]

47

1

T9

1

T68

1

T372

1

auto[1]

from_0to1

auto[1]

auto[1]

54

1

T9

1

T39

1

T69

2