Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	150214	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

113178

1

T4

398

T5

4

T1

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	135820	1			T4	313		T5	2		T1	6
values[0x0]	63498	1			T4	342		T5	6		T1	3
values[0x1]	64074	1			T4	364		T5	9		T1	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	121664	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

141728

1

T4

505

T5

5

T1

7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	872	1			T4	4		T7	2		T9	5
valid_sources[0x01]	847	1			T4	6		T6	1		T9	1
valid_sources[0x02]	1232	1			T4	3		T8	1		T9	4
valid_sources[0x03]	787	1			T4	1		T9	5		T10	2
valid_sources[0x04]	1043	1			T4	2		T5	2		T9	3
valid_sources[0x05]	675	1			T4	1		T5	1		T8	1
valid_sources[0x06]	739	1			T4	3		T9	8		T10	1
valid_sources[0x07]	779	1			T4	1		T13	1		T9	3
valid_sources[0x08]	989	1			T4	2		T9	6		T23	1
valid_sources[0x09]	963	1			T4	2		T14	1		T3	1
valid_sources[0x0a]	1997	1			T4	2		T3	1		T9	4
valid_sources[0x0b]	1006	1			T4	8		T5	4		T9	4
valid_sources[0x0c]	812	1			T4	2		T13	1		T9	5
valid_sources[0x0d]	840	1			T4	3		T9	1		T10	3
valid_sources[0x0e]	746	1			T4	4		T6	1		T9	8
valid_sources[0x0f]	1259	1			T4	4		T15	112		T10	6
valid_sources[0x10]	1014	1			T4	7		T6	1		T9	1
valid_sources[0x11]	857	1			T4	8		T9	1		T26	10
valid_sources[0x12]	810	1			T4	4		T9	5		T10	1
valid_sources[0x13]	969	1			T9	5		T23	4		T10	4
valid_sources[0x14]	959	1			T4	5		T9	7		T10	1
valid_sources[0x15]	1956	1			T4	2		T9	5		T10	5
valid_sources[0x16]	1231	1			T4	2		T9	2		T11	2
valid_sources[0x17]	809	1			T4	1		T9	1		T23	1
valid_sources[0x18]	1109	1			T4	5		T9	3		T10	2
valid_sources[0x19]	1101	1			T4	3		T9	3		T23	1
valid_sources[0x1a]	1709	1			T4	4		T9	11		T10	3
valid_sources[0x1b]	1299	1			T4	10		T13	2		T9	1
valid_sources[0x1c]	769	1			T4	3		T9	2		T10	3
valid_sources[0x1d]	733	1			T4	3		T9	2		T10	2
valid_sources[0x1e]	1670	1			T4	2		T8	1		T9	6
valid_sources[0x1f]	1230	1			T4	2		T13	2		T9	3
valid_sources[0x20]	1019	1			T4	1		T9	5		T10	1
valid_sources[0x21]	951	1			T4	8		T9	3		T23	1
valid_sources[0x22]	760	1			T4	9		T9	3		T23	1
valid_sources[0x23]	1038	1			T4	5		T7	1		T9	3
valid_sources[0x24]	917	1			T4	8		T9	7		T10	4
valid_sources[0x25]	918	1			T4	2		T9	4		T23	2
valid_sources[0x26]	1011	1			T4	2		T9	6		T10	8
valid_sources[0x27]	772	1			T4	3		T6	1		T9	3
valid_sources[0x28]	958	1			T4	6		T9	8		T10	7
valid_sources[0x29]	2515	1			T4	5		T9	3		T23	5
valid_sources[0x2a]	907	1			T4	5		T7	1		T8	1
valid_sources[0x2b]	1673	1			T4	1		T14	2		T6	2
valid_sources[0x2c]	860	1			T4	4		T9	2		T24	1
valid_sources[0x2d]	782	1			T4	3		T9	6		T26	18
valid_sources[0x2e]	858	1			T4	1		T6	1		T9	2
valid_sources[0x2f]	783	1			T4	7		T9	2		T10	2
valid_sources[0x30]	1111	1			T4	2		T9	4		T10	6
valid_sources[0x31]	754	1			T4	9		T8	1		T23	2
valid_sources[0x32]	620	1			T4	4		T6	1		T10	7
valid_sources[0x33]	1131	1			T4	4		T9	2		T23	2
valid_sources[0x34]	847	1			T4	3		T7	1		T9	5
valid_sources[0x35]	979	1			T4	5		T14	6		T8	1
valid_sources[0x36]	1009	1			T4	1		T6	1		T10	1
valid_sources[0x37]	889	1			T4	5		T6	1		T16	1
valid_sources[0x38]	877	1			T4	1		T9	2		T23	1
valid_sources[0x39]	1490	1			T4	3		T9	4		T10	8
valid_sources[0x3a]	993	1			T4	5		T9	3		T10	1
valid_sources[0x3b]	737	1			T4	7		T9	1		T23	2
valid_sources[0x3c]	802	1			T4	1		T9	1		T23	4
valid_sources[0x3d]	920	1			T4	2		T8	1		T9	2
valid_sources[0x3e]	1034	1			T4	1		T9	4		T23	2
valid_sources[0x3f]	1087	1			T4	8		T6	1		T9	8
valid_sources[0x40]	897	1			T4	2		T9	3		T10	7
valid_sources[0x41]	1143	1			T4	6		T1	1		T7	1
valid_sources[0x42]	1368	1			T4	1		T14	1		T9	3
valid_sources[0x43]	1020	1			T4	5		T9	1		T10	2
valid_sources[0x44]	1084	1			T4	2		T13	1		T3	1
valid_sources[0x45]	904	1			T4	3		T9	3		T11	3
valid_sources[0x46]	790	1			T4	6		T22	44		T9	3
valid_sources[0x47]	855	1			T4	5		T9	5		T10	1
valid_sources[0x48]	906	1			T4	4		T9	3		T23	3
valid_sources[0x49]	1383	1			T4	5		T9	6		T10	6
valid_sources[0x4a]	907	1			T4	1		T9	5		T10	3
valid_sources[0x4b]	820	1			T4	2		T7	1		T9	2
valid_sources[0x4c]	755	1			T4	3		T9	2		T10	2
valid_sources[0x4d]	906	1			T4	1		T3	1		T9	2
valid_sources[0x4e]	908	1			T4	4		T9	4		T10	6
valid_sources[0x4f]	807	1			T4	4		T9	3		T26	40
valid_sources[0x50]	2344	1			T4	7		T9	1		T10	1
valid_sources[0x51]	1847	1			T4	3		T5	2		T9	2
valid_sources[0x52]	948	1			T4	6		T9	4		T11	6
valid_sources[0x53]	854	1			T4	4		T9	2		T10	6
valid_sources[0x54]	903	1			T4	9		T9	6		T11	3
valid_sources[0x55]	2015	1			T4	3		T16	1		T9	6
valid_sources[0x56]	903	1			T4	1		T9	4		T11	2
valid_sources[0x57]	1444	1			T4	1		T9	2		T10	1
valid_sources[0x58]	1270	1			T4	3		T3	2		T9	5
valid_sources[0x59]	930	1			T4	2		T9	4		T10	1
valid_sources[0x5a]	678	1			T4	1		T9	4		T10	5
valid_sources[0x5b]	787	1			T4	7		T9	8		T23	3
valid_sources[0x5c]	757	1			T4	8		T6	1		T23	6
valid_sources[0x5d]	965	1			T4	6		T9	2		T10	3
valid_sources[0x5e]	896	1			T4	6		T16	1		T9	5
valid_sources[0x5f]	1249	1			T4	9		T9	1		T10	1
valid_sources[0x60]	1024	1			T4	2		T9	1		T23	1
valid_sources[0x61]	1063	1			T4	3		T9	5		T10	2
valid_sources[0x62]	930	1			T4	5		T9	1		T11	1
valid_sources[0x63]	858	1			T4	4		T9	1		T23	3
valid_sources[0x64]	822	1			T4	1		T6	1		T9	5
valid_sources[0x65]	823	1			T4	2		T9	1		T11	2
valid_sources[0x66]	798	1			T4	2		T9	3		T10	2
valid_sources[0x67]	906	1			T4	9		T8	1		T9	4
valid_sources[0x68]	830	1			T4	7		T9	2		T10	3
valid_sources[0x69]	921	1			T4	4		T1	1		T9	6
valid_sources[0x6a]	1158	1			T4	1		T3	1		T9	5
valid_sources[0x6b]	848	1			T4	5		T3	2		T9	4
valid_sources[0x6c]	866	1			T4	4		T9	5		T10	3
valid_sources[0x6d]	756	1			T4	8		T9	4		T23	1
valid_sources[0x6e]	848	1			T4	3		T10	2		T11	3
valid_sources[0x6f]	894	1			T4	3		T9	2		T10	3
valid_sources[0x70]	804	1			T13	1		T9	5		T11	2
valid_sources[0x71]	1180	1			T4	4		T9	2		T31	1
valid_sources[0x72]	872	1			T4	2		T9	2		T10	1
valid_sources[0x73]	1920	1			T4	4		T9	6		T10	1
valid_sources[0x74]	836	1			T4	3		T8	1		T9	6
valid_sources[0x75]	1901	1			T4	4		T3	2		T9	4
valid_sources[0x76]	863	1			T4	4		T9	1		T10	7
valid_sources[0x77]	1010	1			T4	5		T9	3		T23	5
valid_sources[0x78]	924	1			T4	3		T9	3		T10	1
valid_sources[0x79]	1061	1			T4	6		T3	1		T9	3
valid_sources[0x7a]	989	1			T4	1		T9	7		T10	2
valid_sources[0x7b]	830	1			T4	4		T10	7		T26	12
valid_sources[0x7c]	1958	1			T4	6		T9	2		T11	1
valid_sources[0x7d]	1319	1			T4	3		T9	4		T10	1
valid_sources[0x7e]	807	1			T4	3		T13	2		T9	9
valid_sources[0x7f]	766	1			T4	8		T6	1		T9	4
valid_sources[0x80]	705	1			T4	1		T9	2		T10	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

60950

1

T4

169

T5

1

T1

3

values[0x0]

all_enables

biggest_size

30713

1

T4

136

T5

3

T1

2

values[0x1]

all_enables

biggest_size

21515

1

T4

93

T1

1

T2

50