Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T13,T2
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T13,T2
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T9,T25,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T9,T25,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T9,T25,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T25,T46
1	0	Covered	T4,T13,T2
1	1	Covered	T9,T25,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T25,T46
0	1	Covered	T77,T94
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T25,T46
0	1	Covered	T9,T25,T46
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T25,T46
1	-	Covered	T9,T25,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T25,T46
DetectSt	168	Covered	T9,T25,T46
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T9,T25,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T25,T46
DebounceSt->IdleSt	163	Covered	T25,T47,T50
DetectSt->IdleSt	186	Covered	T77,T94
DetectSt->StableSt	191	Covered	T9,T25,T46
IdleSt->DebounceSt	148	Covered	T9,T25,T46
StableSt->IdleSt	206	Covered	T9,T25,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T25,T46
0	1	Covered	T9,T25,T46
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T25,T46
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T25,T46
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T25,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T25,T50,T35
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T25,T46
DetectSt	-	-	-	-	1	-	-	Covered	T77,T94
DetectSt	-	-	-	-	0	1	-	Covered	T9,T25,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T25,T46
StableSt	-	-	-	-	-	-	0	Covered	T9,T25,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8695005	257	0	0
CntIncr_A	8695005	296912	0	0
CntNoWrap_A	8695005	8013066	0	0
DetectStDropOut_A	8695005	2	0	0
DetectedOut_A	8695005	700	0	0
DetectedPulseOut_A	8695005	113	0	0
DisabledIdleSt_A	8695005	7710550	0	0
DisabledNoDetection_A	8695005	7712935	0	0
EnterDebounceSt_A	8695005	147	0	0
EnterDetectSt_A	8695005	115	0	0
EnterStableSt_A	8695005	113	0	0
PulseIsPulse_A	8695005	113	0	0
StayInStableSt	8695005	587	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8695005	6869	0	0
gen_low_level_sva.LowLevelEvent_A	8695005	8015761	0	0
gen_not_sticky_sva.StableStDropOut_A	8695005	113	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	257	0	0
T9	160050	4	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	0	0	0
T23	2248	0	0	0
T24	522	0	0	0
T25	0	5	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T35	0	1	0	0
T46	0	4	0	0
T47	0	2	0	0
T49	0	4	0	0
T50	0	1	0	0
T51	0	4	0	0
T53	422	0	0	0
T64	523	0	0	0
T87	0	2	0	0
T88	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	296912	0	0
T9	160050	92	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	0	0	0
T23	2248	0	0	0
T24	522	0	0	0
T25	0	171	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T35	0	39	0	0
T46	0	112	0	0
T47	0	222	0	0
T49	0	112	0	0
T50	0	92	0	0
T51	0	81	0	0
T53	422	0	0	0
T64	523	0	0	0
T87	0	56	0	0
T88	0	42359	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8013066	0	0
T1	521	120	0	0
T2	30724	29434	0	0
T3	771	370	0	0
T4	19423	18989	0	0
T5	402	1	0	0
T6	1089	688	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	2	0	0
T43	12983	0	0	0
T75	14153	0	0	0
T77	162894	1	0	0
T78	615	0	0	0
T94	0	1	0	0
T105	446	0	0	0
T106	430	0	0	0
T107	22393	0	0	0
T108	492	0	0	0
T109	8437	0	0	0
T110	574	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	700	0	0
T9	160050	9	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	0	0	0
T23	2248	0	0	0
T24	522	0	0	0
T25	0	10	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T36	0	26	0	0
T42	0	2	0	0
T46	0	22	0	0
T47	0	3	0	0
T49	0	17	0	0
T51	0	3	0	0
T53	422	0	0	0
T64	523	0	0	0
T87	0	7	0	0
T88	0	22	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	113	0	0
T9	160050	2	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	0	0	0
T23	2248	0	0	0
T24	522	0	0	0
T25	0	2	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T36	0	4	0	0
T42	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T49	0	2	0	0
T51	0	2	0	0
T53	422	0	0	0
T64	523	0	0	0
T87	0	1	0	0
T88	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	7710550	0	0
T1	521	120	0	0
T2	30724	29434	0	0
T3	771	370	0	0
T4	19423	18989	0	0
T5	402	1	0	0
T6	1089	688	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	7712935	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	147	0	0
T9	160050	2	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	0	0	0
T23	2248	0	0	0
T24	522	0	0	0
T25	0	3	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T35	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	2	0	0
T53	422	0	0	0
T64	523	0	0	0
T87	0	1	0	0
T88	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	115	0	0
T9	160050	2	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	0	0	0
T23	2248	0	0	0
T24	522	0	0	0
T25	0	2	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T36	0	4	0	0
T42	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T49	0	2	0	0
T51	0	2	0	0
T53	422	0	0	0
T64	523	0	0	0
T87	0	1	0	0
T88	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	113	0	0
T9	160050	2	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	0	0	0
T23	2248	0	0	0
T24	522	0	0	0
T25	0	2	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T36	0	4	0	0
T42	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T49	0	2	0	0
T51	0	2	0	0
T53	422	0	0	0
T64	523	0	0	0
T87	0	1	0	0
T88	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	113	0	0
T9	160050	2	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	0	0	0
T23	2248	0	0	0
T24	522	0	0	0
T25	0	2	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T36	0	4	0	0
T42	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T49	0	2	0	0
T51	0	2	0	0
T53	422	0	0	0
T64	523	0	0	0
T87	0	1	0	0
T88	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	587	0	0
T9	160050	7	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	0	0	0
T23	2248	0	0	0
T24	522	0	0	0
T25	0	8	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T36	0	22	0	0
T42	0	1	0	0
T46	0	20	0	0
T47	0	2	0	0
T49	0	15	0	0
T51	0	1	0	0
T53	422	0	0	0
T64	523	0	0	0
T87	0	6	0	0
T88	0	20	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	6869	0	0
T1	521	0	0	0
T2	30724	18	0	0
T3	771	0	0	0
T4	19423	33	0	0
T5	402	0	0	0
T6	1089	1	0	0
T7	0	1	0	0
T8	0	4	0	0
T13	446	6	0	0
T14	643	3	0	0
T15	2573	11	0	0
T16	595	0	0	0
T17	0	25	0	0
T22	0	10	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8015761	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	113	0	0
T9	160050	2	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	0	0	0
T23	2248	0	0	0
T24	522	0	0	0
T25	0	2	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T36	0	4	0	0
T42	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T49	0	2	0	0
T51	0	2	0	0
T53	422	0	0	0
T64	523	0	0	0
T87	0	1	0	0
T88	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T13,T2
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T13,T2
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T8,T9,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T8,T9,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T8,T9,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T12
1	0	Covered	T4,T13,T2
1	1	Covered	T8,T9,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T12
0	1	Covered	T12,T54,T43
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T12
0	1	Unreachable
1	0	Covered	T8,T9,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T12
DetectSt	168	Covered	T8,T9,T12
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T8,T9,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T12
DebounceSt->IdleSt	163	Covered	T54,T58,T114
DetectSt->IdleSt	186	Covered	T12,T54,T43
DetectSt->StableSt	191	Covered	T8,T9,T12
IdleSt->DebounceSt	148	Covered	T8,T9,T12
StableSt->IdleSt	206	Covered	T8,T9,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T9,T12
0	1	Covered	T8,T9,T12
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T12
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T54,T58,T114
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T12
DetectSt	-	-	-	-	1	-	-	Covered	T12,T54,T43
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T9,T12
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8695005	224	0	0
CntIncr_A	8695005	76130	0	0
CntNoWrap_A	8695005	8013099	0	0
DetectStDropOut_A	8695005	23	0	0
DetectedOut_A	8695005	106178	0	0
DetectedPulseOut_A	8695005	59	0	0
DisabledIdleSt_A	8695005	6701249	0	0
DisabledNoDetection_A	8695005	6703682	0	0
EnterDebounceSt_A	8695005	143	0	0
EnterDetectSt_A	8695005	82	0	0
EnterStableSt_A	8695005	59	0	0
PulseIsPulse_A	8695005	59	0	0
StayInStableSt	8695005	106119	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8695005	6869	0	0
gen_low_level_sva.LowLevelEvent_A	8695005	8015761	0	0
gen_sticky_sva.StableStDropOut_A	8695005	780693	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	224	0	0
T8	987	2	0	0
T9	160050	2	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	4	0	0
T23	2248	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T39	0	2	0	0
T53	422	0	0	0
T54	0	5	0	0
T55	0	2	0	0
T56	0	2	0	0
T57	0	2	0	0
T58	0	5	0	0
T59	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	76130	0	0
T8	987	33	0	0
T9	160050	53	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	138	0	0
T23	2248	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T39	0	59	0	0
T53	422	0	0	0
T54	0	165	0	0
T55	0	59	0	0
T56	0	19	0	0
T57	0	48	0	0
T58	0	90	0	0
T59	0	35	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8013099	0	0
T1	521	120	0	0
T2	30724	29434	0	0
T3	771	370	0	0
T4	19423	18989	0	0
T5	402	1	0	0
T6	1089	688	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	23	0	0
T12	1470	1	0	0
T24	522	0	0	0
T30	7421	0	0	0
T31	19687	0	0	0
T43	0	3	0	0
T44	13576	0	0	0
T54	0	2	0	0
T60	1314	0	0	0
T64	523	0	0	0
T83	0	2	0	0
T102	462	0	0	0
T103	416	0	0	0
T104	426	0	0	0
T116	0	2	0	0
T117	0	2	0	0
T118	0	1	0	0
T119	0	2	0	0
T120	0	2	0	0
T121	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	106178	0	0
T8	987	223	0	0
T9	160050	270	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	2	0	0
T23	2248	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T39	0	504	0	0
T53	422	0	0	0
T55	0	464	0	0
T56	0	15	0	0
T57	0	238	0	0
T59	0	5	0	0
T113	0	458	0	0
T115	0	437	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	59	0	0
T8	987	1	0	0
T9	160050	1	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	1	0	0
T23	2248	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T39	0	1	0	0
T53	422	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	0	1	0	0
T113	0	1	0	0
T115	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	6701249	0	0
T1	521	120	0	0
T2	30724	29434	0	0
T3	771	370	0	0
T4	19423	18989	0	0
T5	402	1	0	0
T6	1089	688	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	6703682	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	143	0	0
T8	987	1	0	0
T9	160050	1	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	2	0	0
T23	2248	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T39	0	1	0	0
T53	422	0	0	0
T54	0	3	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	5	0	0
T59	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	82	0	0
T8	987	1	0	0
T9	160050	1	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	2	0	0
T23	2248	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T39	0	1	0	0
T53	422	0	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	0	1	0	0
T113	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	59	0	0
T8	987	1	0	0
T9	160050	1	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	1	0	0
T23	2248	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T39	0	1	0	0
T53	422	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	0	1	0	0
T113	0	1	0	0
T115	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	59	0	0
T8	987	1	0	0
T9	160050	1	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	1	0	0
T23	2248	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T39	0	1	0	0
T53	422	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	0	1	0	0
T113	0	1	0	0
T115	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	106119	0	0
T8	987	222	0	0
T9	160050	269	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	1	0	0
T23	2248	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T39	0	503	0	0
T53	422	0	0	0
T55	0	463	0	0
T56	0	14	0	0
T57	0	237	0	0
T59	0	4	0	0
T113	0	457	0	0
T115	0	435	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	6869	0	0
T1	521	0	0	0
T2	30724	18	0	0
T3	771	0	0	0
T4	19423	33	0	0
T5	402	0	0	0
T6	1089	1	0	0
T7	0	1	0	0
T8	0	4	0	0
T13	446	6	0	0
T14	643	3	0	0
T15	2573	11	0	0
T16	595	0	0	0
T17	0	25	0	0
T22	0	10	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8015761	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	780693	0	0
T8	987	289	0	0
T9	160050	146343	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	83	0	0
T23	2248	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T39	0	159	0	0
T53	422	0	0	0
T55	0	122	0	0
T56	0	126	0	0
T57	0	392	0	0
T59	0	152	0	0
T113	0	301	0	0
T115	0	111	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T13,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T13,T2
1	1	Covered	T1,T13,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T8,T9,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T8,T9,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T9,T54,T55

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T12
1	0	Covered	T1,T13,T2
1	1	Covered	T8,T9,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T54,T55
0	1	Covered	T84,T85,T86
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T54,T55
0	1	Unreachable
1	0	Covered	T9,T54,T55

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T12
DetectSt	168	Covered	T9,T54,T55
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T9,T54,T55

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T54,T55
DebounceSt->IdleSt	163	Covered	T8,T12,T39
DetectSt->IdleSt	186	Covered	T84,T85,T86
DetectSt->StableSt	191	Covered	T9,T54,T55
IdleSt->DebounceSt	148	Covered	T8,T9,T12
StableSt->IdleSt	206	Covered	T9,T54,T55

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T9,T12
0	1	Covered	T8,T9,T12
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T54,T55
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T12
IdleSt	0	-	-	-	-	-	-	Covered	T1,T13,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T54,T55
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T12,T39
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T12
DetectSt	-	-	-	-	1	-	-	Covered	T84,T85,T86
DetectSt	-	-	-	-	0	1	-	Covered	T9,T54,T55
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T54,T55
StableSt	-	-	-	-	-	-	0	Covered	T9,T54,T55
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8695005	201	0	0
CntIncr_A	8695005	425706	0	0
CntNoWrap_A	8695005	8013122	0	0
DetectStDropOut_A	8695005	10	0	0
DetectedOut_A	8695005	461289	0	0
DetectedPulseOut_A	8695005	56	0	0
DisabledIdleSt_A	8695005	6701249	0	0
DisabledNoDetection_A	8695005	6703682	0	0
EnterDebounceSt_A	8695005	136	0	0
EnterDetectSt_A	8695005	66	0	0
EnterStableSt_A	8695005	56	0	0
PulseIsPulse_A	8695005	56	0	0
StayInStableSt	8695005	461233	0	0
gen_high_level_sva.HighLevelEvent_A	8695005	8015761	0	0
gen_sticky_sva.StableStDropOut_A	8695005	373679	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	201	0	0
T8	987	4	0	0
T9	160050	2	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	1	0	0
T23	2248	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T39	0	5	0	0
T53	422	0	0	0
T54	0	4	0	0
T55	0	2	0	0
T56	0	2	0	0
T57	0	2	0	0
T58	0	2	0	0
T59	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	425706	0	0
T8	987	152	0	0
T9	160050	61	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	35	0	0
T23	2248	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T39	0	90	0	0
T53	422	0	0	0
T54	0	112	0	0
T55	0	62	0	0
T56	0	83	0	0
T57	0	61	0	0
T58	0	63	0	0
T59	0	71	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8013122	0	0
T1	521	120	0	0
T2	30724	29434	0	0
T3	771	370	0	0
T4	19423	18989	0	0
T5	402	1	0	0
T6	1089	688	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	10	0	0
T84	2896	2	0	0
T85	0	2	0	0
T86	0	1	0	0
T120	0	3	0	0
T122	0	1	0	0
T123	0	1	0	0
T124	424	0	0	0
T125	502	0	0	0
T126	26285	0	0	0
T127	502	0	0	0
T128	428	0	0	0
T129	41638	0	0	0
T130	409	0	0	0
T131	527	0	0	0
T132	1397	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	461289	0	0
T9	160050	327	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	0	0	0
T23	2248	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T53	422	0	0	0
T54	0	72	0	0
T55	0	278	0	0
T56	0	42	0	0
T57	0	397	0	0
T58	0	524	0	0
T59	0	61	0	0
T64	523	0	0	0
T113	0	293	0	0
T114	0	84	0	0
T115	0	272	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	56	0	0
T9	160050	1	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	0	0	0
T23	2248	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T53	422	0	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T64	523	0	0	0
T113	0	1	0	0
T114	0	1	0	0
T115	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	6701249	0	0
T1	521	120	0	0
T2	30724	29434	0	0
T3	771	370	0	0
T4	19423	18989	0	0
T5	402	1	0	0
T6	1089	688	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	6703682	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	136	0	0
T8	987	4	0	0
T9	160050	1	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	1	0	0
T23	2248	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T39	0	5	0	0
T53	422	0	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	66	0	0
T9	160050	1	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	0	0	0
T23	2248	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T53	422	0	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T64	523	0	0	0
T113	0	1	0	0
T114	0	1	0	0
T115	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	56	0	0
T9	160050	1	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	0	0	0
T23	2248	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T53	422	0	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T64	523	0	0	0
T113	0	1	0	0
T114	0	1	0	0
T115	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	56	0	0
T9	160050	1	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	0	0	0
T23	2248	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T53	422	0	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T64	523	0	0	0
T113	0	1	0	0
T114	0	1	0	0
T115	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	461233	0	0
T9	160050	326	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	0	0	0
T23	2248	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T53	422	0	0	0
T54	0	70	0	0
T55	0	277	0	0
T56	0	41	0	0
T57	0	396	0	0
T58	0	523	0	0
T59	0	60	0	0
T64	523	0	0	0
T113	0	292	0	0
T114	0	83	0	0
T115	0	270	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8015761	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	373679	0	0
T9	160050	146271	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	0	0	0
T23	2248	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T53	422	0	0	0
T54	0	72	0	0
T55	0	307	0	0
T56	0	28	0	0
T57	0	215	0	0
T58	0	152	0	0
T59	0	59	0	0
T64	523	0	0	0
T113	0	457	0	0
T114	0	230	0	0
T115	0	418	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T1,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T8,T9,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T8,T9,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T8,T9,T54

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T12
1	0	Covered	T4,T1,T13
1	1	Covered	T8,T9,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T54
0	1	Covered	T82,T77,T83
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T54
0	1	Unreachable
1	0	Covered	T8,T9,T54

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T12
DetectSt	168	Covered	T8,T9,T54
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T8,T9,T54

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T54
DebounceSt->IdleSt	163	Covered	T12,T58,T59
DetectSt->IdleSt	186	Covered	T82,T77,T83
DetectSt->StableSt	191	Covered	T8,T9,T54
IdleSt->DebounceSt	148	Covered	T8,T9,T12
StableSt->IdleSt	206	Covered	T8,T9,T54

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T9,T12
0	1	Covered	T8,T9,T12
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T54
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T54
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T58,T59
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T12
DetectSt	-	-	-	-	1	-	-	Covered	T82,T77,T83
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T54
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T9,T54
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T54
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8695005	217	0	0
CntIncr_A	8695005	107818	0	0
CntNoWrap_A	8695005	8013106	0	0
DetectStDropOut_A	8695005	15	0	0
DetectedOut_A	8695005	203903	0	0
DetectedPulseOut_A	8695005	57	0	0
DisabledIdleSt_A	8695005	6701249	0	0
DisabledNoDetection_A	8695005	6703682	0	0
EnterDebounceSt_A	8695005	146	0	0
EnterDetectSt_A	8695005	72	0	0
EnterStableSt_A	8695005	57	0	0
PulseIsPulse_A	8695005	57	0	0
StayInStableSt	8695005	203846	0	0
gen_high_event_sva.HighLevelEvent_A	8695005	8015761	0	0
gen_high_level_sva.HighLevelEvent_A	8695005	8015761	0	0
gen_sticky_sva.StableStDropOut_A	8695005	214957	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	217	0	0
T8	987	2	0	0
T9	160050	2	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	2	0	0
T23	2248	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T39	0	2	0	0
T53	422	0	0	0
T54	0	4	0	0
T55	0	2	0	0
T56	0	2	0	0
T57	0	2	0	0
T58	0	5	0	0
T59	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	107818	0	0
T8	987	76	0	0
T9	160050	34145	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	164	0	0
T23	2248	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T39	0	75	0	0
T53	422	0	0	0
T54	0	126	0	0
T55	0	13	0	0
T56	0	100	0	0
T57	0	69	0	0
T58	0	85	0	0
T59	0	88	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8013106	0	0
T1	521	120	0	0
T2	30724	29434	0	0
T3	771	370	0	0
T4	19423	18989	0	0
T5	402	1	0	0
T6	1089	688	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	15	0	0
T36	15068	0	0	0
T42	124553	0	0	0
T77	0	1	0	0
T82	159345	1	0	0
T83	0	4	0	0
T117	0	2	0	0
T133	0	1	0	0
T134	0	2	0	0
T135	0	4	0	0
T136	423	0	0	0
T137	12387	0	0	0
T138	22789	0	0	0
T139	522	0	0	0
T140	689	0	0	0
T141	490	0	0	0
T142	2155	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	203903	0	0
T8	987	324	0	0
T9	160050	112481	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	0	0	0
T23	2248	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T39	0	491	0	0
T42	0	93	0	0
T53	422	0	0	0
T54	0	70	0	0
T55	0	116	0	0
T56	0	21	0	0
T57	0	565	0	0
T114	0	156	0	0
T115	0	298	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	57	0	0
T8	987	1	0	0
T9	160050	1	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	0	0	0
T23	2248	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T39	0	1	0	0
T42	0	1	0	0
T53	422	0	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T114	0	1	0	0
T115	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	6701249	0	0
T1	521	120	0	0
T2	30724	29434	0	0
T3	771	370	0	0
T4	19423	18989	0	0
T5	402	1	0	0
T6	1089	688	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	6703682	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	146	0	0
T8	987	1	0	0
T9	160050	1	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	2	0	0
T23	2248	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T39	0	1	0	0
T53	422	0	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	5	0	0
T59	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	72	0	0
T8	987	1	0	0
T9	160050	1	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	0	0	0
T23	2248	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T39	0	1	0	0
T53	422	0	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T82	0	1	0	0
T114	0	1	0	0
T115	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	57	0	0
T8	987	1	0	0
T9	160050	1	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	0	0	0
T23	2248	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T39	0	1	0	0
T42	0	1	0	0
T53	422	0	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T114	0	1	0	0
T115	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	57	0	0
T8	987	1	0	0
T9	160050	1	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	0	0	0
T23	2248	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T39	0	1	0	0
T42	0	1	0	0
T53	422	0	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T114	0	1	0	0
T115	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	203846	0	0
T8	987	323	0	0
T9	160050	112480	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	0	0	0
T23	2248	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T39	0	490	0	0
T42	0	92	0	0
T53	422	0	0	0
T54	0	68	0	0
T55	0	115	0	0
T56	0	20	0	0
T57	0	564	0	0
T114	0	155	0	0
T115	0	296	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8015761	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8015761	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	214957	0	0
T8	987	149	0	0
T9	160050	47	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	0	0	0
T23	2248	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T39	0	167	0	0
T42	0	309	0	0
T53	422	0	0	0
T54	0	80	0	0
T55	0	535	0	0
T56	0	46	0	0
T57	0	52	0	0
T114	0	145	0	0
T115	0	391	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T1,T13
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T39,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T6,T39,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T39,T42,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T37
1	0	Covered	T4,T5,T1
1	1	Covered	T6,T39,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T39,T42,T43
0	1	Covered	T117,T143,T144
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T39,T42,T43
0	1	Covered	T39,T42,T43
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T39,T42,T43
1	-	Covered	T39,T42,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T39,T42
DetectSt	168	Covered	T39,T42,T43
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T39,T42,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T39,T42,T43
DebounceSt->IdleSt	163	Covered	T6,T73,T74
DetectSt->IdleSt	186	Covered	T117,T143,T144
DetectSt->StableSt	191	Covered	T39,T42,T43
IdleSt->DebounceSt	148	Covered	T6,T39,T42
StableSt->IdleSt	206	Covered	T39,T42,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T39,T42
0	1	Covered	T6,T39,T42
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T39,T42,T43
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T39,T42
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T39,T42,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T6,T145
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T39,T42
DetectSt	-	-	-	-	1	-	-	Covered	T117,T143,T144
DetectSt	-	-	-	-	0	1	-	Covered	T39,T42,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T39,T42,T43
StableSt	-	-	-	-	-	-	0	Covered	T39,T42,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8695005	68	0	0
CntIncr_A	8695005	112410	0	0
CntNoWrap_A	8695005	8013255	0	0
DetectStDropOut_A	8695005	3	0	0
DetectedOut_A	8695005	2791	0	0
DetectedPulseOut_A	8695005	29	0	0
DisabledIdleSt_A	8695005	7512424	0	0
DisabledNoDetection_A	8695005	7514806	0	0
EnterDebounceSt_A	8695005	36	0	0
EnterDetectSt_A	8695005	32	0	0
EnterStableSt_A	8695005	29	0	0
PulseIsPulse_A	8695005	29	0	0
StayInStableSt	8695005	2745	0	0
gen_high_level_sva.HighLevelEvent_A	8695005	8015761	0	0
gen_not_sticky_sva.StableStDropOut_A	8695005	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	68	0	0
T6	1089	1	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	0	0	0
T10	37403	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	496	0	0	0
T23	2248	0	0	0
T39	0	2	0	0
T42	0	4	0	0
T43	0	2	0	0
T83	0	2	0	0
T85	0	2	0	0
T94	0	4	0	0
T117	0	2	0	0
T146	0	2	0	0
T147	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	112410	0	0
T6	1089	80	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	0	0	0
T10	37403	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	496	0	0	0
T23	2248	0	0	0
T39	0	16	0	0
T42	0	94	0	0
T43	0	18	0	0
T83	0	64	0	0
T85	0	19	0	0
T94	0	110210	0	0
T117	0	67	0	0
T146	0	87	0	0
T147	0	99	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8013255	0	0
T1	521	120	0	0
T2	30724	29434	0	0
T3	771	370	0	0
T4	19423	18989	0	0
T5	402	1	0	0
T6	1089	687	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	3	0	0
T117	20697	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T148	498	0	0	0
T149	953	0	0	0
T150	12767	0	0	0
T151	674	0	0	0
T152	65864	0	0	0
T153	489	0	0	0
T154	24860	0	0	0
T155	403	0	0	0
T156	607	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	2791	0	0
T39	15545	43	0	0
T42	0	84	0	0
T43	0	84	0	0
T47	5675	0	0	0
T57	1846	0	0	0
T61	498	0	0	0
T69	502	0	0	0
T83	0	43	0	0
T85	0	41	0	0
T94	0	84	0	0
T118	0	244	0	0
T146	0	36	0	0
T147	0	44	0	0
T157	0	83	0	0
T158	425	0	0	0
T159	437	0	0	0
T160	957	0	0	0
T161	17951	0	0	0
T162	513	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	29	0	0
T39	15545	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T47	5675	0	0	0
T57	1846	0	0	0
T61	498	0	0	0
T69	502	0	0	0
T83	0	1	0	0
T85	0	1	0	0
T94	0	2	0	0
T118	0	2	0	0
T146	0	1	0	0
T147	0	1	0	0
T157	0	2	0	0
T158	425	0	0	0
T159	437	0	0	0
T160	957	0	0	0
T161	17951	0	0	0
T162	513	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	7512424	0	0
T1	521	120	0	0
T2	30724	29434	0	0
T3	771	370	0	0
T4	19423	18989	0	0
T5	402	1	0	0
T6	1089	4	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	7514806	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	4	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	36	0	0
T6	1089	1	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	0	0	0
T10	37403	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	496	0	0	0
T23	2248	0	0	0
T39	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T83	0	1	0	0
T85	0	1	0	0
T94	0	2	0	0
T117	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	32	0	0
T39	15545	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T47	5675	0	0	0
T57	1846	0	0	0
T61	498	0	0	0
T69	502	0	0	0
T83	0	1	0	0
T85	0	1	0	0
T94	0	2	0	0
T117	0	1	0	0
T118	0	2	0	0
T146	0	1	0	0
T147	0	1	0	0
T158	425	0	0	0
T159	437	0	0	0
T160	957	0	0	0
T161	17951	0	0	0
T162	513	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	29	0	0
T39	15545	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T47	5675	0	0	0
T57	1846	0	0	0
T61	498	0	0	0
T69	502	0	0	0
T83	0	1	0	0
T85	0	1	0	0
T94	0	2	0	0
T118	0	2	0	0
T146	0	1	0	0
T147	0	1	0	0
T157	0	2	0	0
T158	425	0	0	0
T159	437	0	0	0
T160	957	0	0	0
T161	17951	0	0	0
T162	513	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	29	0	0
T39	15545	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T47	5675	0	0	0
T57	1846	0	0	0
T61	498	0	0	0
T69	502	0	0	0
T83	0	1	0	0
T85	0	1	0	0
T94	0	2	0	0
T118	0	2	0	0
T146	0	1	0	0
T147	0	1	0	0
T157	0	2	0	0
T158	425	0	0	0
T159	437	0	0	0
T160	957	0	0	0
T161	17951	0	0	0
T162	513	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	2745	0	0
T39	15545	42	0	0
T42	0	81	0	0
T43	0	83	0	0
T47	5675	0	0	0
T57	1846	0	0	0
T61	498	0	0	0
T69	502	0	0	0
T83	0	41	0	0
T85	0	40	0	0
T94	0	81	0	0
T118	0	241	0	0
T146	0	35	0	0
T147	0	42	0	0
T157	0	80	0	0
T158	425	0	0	0
T159	437	0	0	0
T160	957	0	0	0
T161	17951	0	0	0
T162	513	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8015761	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	12	0	0
T39	15545	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T47	5675	0	0	0
T57	1846	0	0	0
T61	498	0	0	0
T69	502	0	0	0
T85	0	1	0	0
T94	0	1	0	0
T118	0	1	0	0
T120	0	1	0	0
T146	0	1	0	0
T157	0	1	0	0
T158	425	0	0	0
T159	437	0	0	0
T160	957	0	0	0
T161	17951	0	0	0
T162	513	0	0	0
T163	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T13
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T9,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T6,T9,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T9,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T9
1	0	Covered	T4,T1,T13
1	1	Covered	T6,T9,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T37
0	1	Covered	T78,T157
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T37
0	1	Covered	T6,T41,T164
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T9,T37
1	-	Covered	T6,T41,T164

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T9,T37
DetectSt	168	Covered	T6,T9,T37
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T6,T9,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T9,T37
DebounceSt->IdleSt	163	Covered	T42,T85,T157
DetectSt->IdleSt	186	Covered	T78,T157
DetectSt->StableSt	191	Covered	T6,T9,T37
IdleSt->DebounceSt	148	Covered	T6,T9,T37
StableSt->IdleSt	206	Covered	T6,T9,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T9,T37
0	1	Covered	T6,T9,T37
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T9,T37
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T9,T37
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T9,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T42,T85,T157
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T9,T37
DetectSt	-	-	-	-	1	-	-	Covered	T78,T157
DetectSt	-	-	-	-	0	1	-	Covered	T6,T9,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T41,T164
StableSt	-	-	-	-	-	-	0	Covered	T6,T9,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8695005	139	0	0
CntIncr_A	8695005	189571	0	0
CntNoWrap_A	8695005	8013184	0	0
DetectStDropOut_A	8695005	2	0	0
DetectedOut_A	8695005	120588	0	0
DetectedPulseOut_A	8695005	65	0	0
DisabledIdleSt_A	8695005	7513870	0	0
DisabledNoDetection_A	8695005	7516251	0	0
EnterDebounceSt_A	8695005	72	0	0
EnterDetectSt_A	8695005	67	0	0
EnterStableSt_A	8695005	65	0	0
PulseIsPulse_A	8695005	65	0	0
StayInStableSt	8695005	120493	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8695005	2603	0	0
gen_low_level_sva.LowLevelEvent_A	8695005	8015761	0	0
gen_not_sticky_sva.StableStDropOut_A	8695005	35	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	139	0	0
T6	1089	4	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	2	0	0
T10	37403	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	496	0	0	0
T23	2248	0	0	0
T37	0	2	0	0
T41	0	2	0	0
T70	0	2	0	0
T164	0	4	0	0
T165	0	2	0	0
T166	0	4	0	0
T167	0	2	0	0
T168	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	189571	0	0
T6	1089	160	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	79	0	0
T10	37403	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	496	0	0	0
T23	2248	0	0	0
T37	0	55	0	0
T41	0	67	0	0
T70	0	85	0	0
T164	0	180	0	0
T165	0	30	0	0
T166	0	180	0	0
T167	0	13	0	0
T168	0	57602	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8013184	0	0
T1	521	120	0	0
T2	30724	29434	0	0
T3	771	370	0	0
T4	19423	18989	0	0
T5	402	1	0	0
T6	1089	684	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	2	0	0
T43	12983	0	0	0
T75	14153	0	0	0
T78	615	1	0	0
T107	22393	0	0	0
T108	492	0	0	0
T109	8437	0	0	0
T110	574	0	0	0
T157	0	1	0	0
T169	960	0	0	0
T170	11774	0	0	0
T171	510	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	120588	0	0
T6	1089	197	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	42	0	0
T10	37403	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	496	0	0	0
T23	2248	0	0	0
T37	0	411	0	0
T41	0	216	0	0
T70	0	154	0	0
T164	0	227	0	0
T165	0	46	0	0
T166	0	296	0	0
T167	0	43	0	0
T168	0	102315	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	65	0	0
T6	1089	2	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	1	0	0
T10	37403	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	496	0	0	0
T23	2248	0	0	0
T37	0	1	0	0
T41	0	1	0	0
T70	0	1	0	0
T164	0	2	0	0
T165	0	1	0	0
T166	0	2	0	0
T167	0	1	0	0
T168	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	7513870	0	0
T1	521	120	0	0
T2	30724	29434	0	0
T3	771	370	0	0
T4	19423	18989	0	0
T5	402	1	0	0
T6	1089	4	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	7516251	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	4	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	72	0	0
T6	1089	2	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	1	0	0
T10	37403	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	496	0	0	0
T23	2248	0	0	0
T37	0	1	0	0
T41	0	1	0	0
T70	0	1	0	0
T164	0	2	0	0
T165	0	1	0	0
T166	0	2	0	0
T167	0	1	0	0
T168	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	67	0	0
T6	1089	2	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	1	0	0
T10	37403	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	496	0	0	0
T23	2248	0	0	0
T37	0	1	0	0
T41	0	1	0	0
T70	0	1	0	0
T164	0	2	0	0
T165	0	1	0	0
T166	0	2	0	0
T167	0	1	0	0
T168	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	65	0	0
T6	1089	2	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	1	0	0
T10	37403	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	496	0	0	0
T23	2248	0	0	0
T37	0	1	0	0
T41	0	1	0	0
T70	0	1	0	0
T164	0	2	0	0
T165	0	1	0	0
T166	0	2	0	0
T167	0	1	0	0
T168	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	65	0	0
T6	1089	2	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	1	0	0
T10	37403	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	496	0	0	0
T23	2248	0	0	0
T37	0	1	0	0
T41	0	1	0	0
T70	0	1	0	0
T164	0	2	0	0
T165	0	1	0	0
T166	0	2	0	0
T167	0	1	0	0
T168	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	120493	0	0
T6	1089	194	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	40	0	0
T10	37403	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	496	0	0	0
T23	2248	0	0	0
T37	0	409	0	0
T41	0	215	0	0
T70	0	152	0	0
T164	0	224	0	0
T165	0	44	0	0
T166	0	293	0	0
T167	0	41	0	0
T168	0	102313	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	2603	0	0
T1	521	1	0	0
T2	30724	8	0	0
T3	771	1	0	0
T6	1089	2	0	0
T7	498	0	0	0
T9	0	24	0	0
T13	446	4	0	0
T14	643	0	0	0
T15	2573	4	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	0	4	0	0
T23	0	13	0	0
T53	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8015761	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	35	0	0
T6	1089	1	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	0	0	0
T10	37403	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	496	0	0	0
T23	2248	0	0	0
T35	0	1	0	0
T36	0	3	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T164	0	1	0	0
T166	0	1	0	0
T169	0	1	0	0
T172	0	1	0	0