Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.17	93.48	85.71		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.17	93.48	85.71		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T1,T13
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T40,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T40,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T40,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T9
1	0	Covered	T4,T5,T1
1	1	Covered	T3,T40,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T40,T39
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T40,T39
0	1	Covered	T166,T172,T43
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T40,T39
1	-	Covered	T166,T172,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T40,T39
DetectSt	168	Covered	T3,T40,T39
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T40,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T40,T39
DebounceSt->IdleSt	163	Covered	T73,T74
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T40,T39
IdleSt->DebounceSt	148	Covered	T3,T40,T39
StableSt->IdleSt	206	Covered	T39,T166,T113

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T40,T39
0	1	Covered	T3,T40,T39
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T40,T39
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T40,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T40,T39
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T40,T39
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T40,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T166,T172,T43
StableSt	-	-	-	-	-	-	0	Covered	T3,T40,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8695005	58	0	0
CntIncr_A	8695005	1801	0	0
CntNoWrap_A	8695005	8013265	0	0
DetectStDropOut_A	8695005	0	0	0
DetectedOut_A	8695005	2419	0	0
DetectedPulseOut_A	8695005	28	0	0
DisabledIdleSt_A	8695005	7885862	0	0
DisabledNoDetection_A	8695005	7888250	0	0
EnterDebounceSt_A	8695005	30	0	0
EnterDetectSt_A	8695005	28	0	0
EnterStableSt_A	8695005	28	0	0
PulseIsPulse_A	8695005	28	0	0
StayInStableSt	8695005	2374	0	0
gen_high_level_sva.HighLevelEvent_A	8695005	8015761	0	0
gen_not_sticky_sva.StableStDropOut_A	8695005	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	58	0	0
T3	771	2	0	0
T6	1089	0	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	496	0	0	0
T23	2248	0	0	0
T35	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T43	0	6	0	0
T113	0	2	0	0
T146	0	2	0	0
T166	0	2	0	0
T172	0	2	0	0
T173	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	1801	0	0
T3	771	40	0	0
T6	1089	0	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	496	0	0	0
T23	2248	0	0	0
T35	0	29	0	0
T39	0	58	0	0
T40	0	98	0	0
T43	0	124	0	0
T113	0	19	0	0
T146	0	87	0	0
T166	0	90	0	0
T172	0	75	0	0
T173	0	68	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8013265	0	0
T1	521	120	0	0
T2	30724	29434	0	0
T3	771	368	0	0
T4	19423	18989	0	0
T5	402	1	0	0
T6	1089	688	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	2419	0	0
T3	771	90	0	0
T6	1089	0	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	496	0	0	0
T23	2248	0	0	0
T35	0	48	0	0
T39	0	43	0	0
T40	0	44	0	0
T43	0	220	0	0
T113	0	47	0	0
T146	0	130	0	0
T166	0	43	0	0
T172	0	174	0	0
T173	0	134	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	28	0	0
T3	771	1	0	0
T6	1089	0	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	496	0	0	0
T23	2248	0	0	0
T35	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	0	3	0	0
T113	0	1	0	0
T146	0	1	0	0
T166	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	7885862	0	0
T1	521	4	0	0
T2	30724	29434	0	0
T3	771	3	0	0
T4	19423	18989	0	0
T5	402	1	0	0
T6	1089	688	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	7888250	0	0
T1	521	4	0	0
T2	30724	29448	0	0
T3	771	3	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	30	0	0
T3	771	1	0	0
T6	1089	0	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	496	0	0	0
T23	2248	0	0	0
T35	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	0	3	0	0
T113	0	1	0	0
T146	0	1	0	0
T166	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	28	0	0
T3	771	1	0	0
T6	1089	0	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	496	0	0	0
T23	2248	0	0	0
T35	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	0	3	0	0
T113	0	1	0	0
T146	0	1	0	0
T166	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	28	0	0
T3	771	1	0	0
T6	1089	0	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	496	0	0	0
T23	2248	0	0	0
T35	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	0	3	0	0
T113	0	1	0	0
T146	0	1	0	0
T166	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	28	0	0
T3	771	1	0	0
T6	1089	0	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	496	0	0	0
T23	2248	0	0	0
T35	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	0	3	0	0
T113	0	1	0	0
T146	0	1	0	0
T166	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	2374	0	0
T3	771	88	0	0
T6	1089	0	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	496	0	0	0
T23	2248	0	0	0
T35	0	46	0	0
T39	0	41	0	0
T40	0	42	0	0
T43	0	216	0	0
T113	0	45	0	0
T146	0	129	0	0
T166	0	42	0	0
T172	0	173	0	0
T173	0	132	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8015761	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	11	0	0
T43	0	2	0	0
T59	9707	0	0	0
T92	7450	0	0	0
T146	0	1	0	0
T147	0	1	0	0
T166	1116	1	0	0
T172	0	1	0	0
T174	0	2	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	0	1	0	0
T178	503	0	0	0
T179	34787	0	0	0
T180	534	0	0	0
T181	494	0	0	0
T182	530	0	0	0
T183	423	0	0	0
T184	423	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T13
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T37,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T7,T37,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T37,T38,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T9,T37
1	0	Covered	T4,T1,T13
1	1	Covered	T7,T37,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T37,T38,T39
0	1	Covered	T117,T185,T186
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T37,T38,T39
0	1	Covered	T41,T166,T187
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T37,T38,T39
1	-	Covered	T41,T166,T187

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T37,T38
DetectSt	168	Covered	T37,T38,T39
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T37,T38,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T37,T38,T39
DebounceSt->IdleSt	163	Covered	T7,T38,T188
DetectSt->IdleSt	186	Covered	T117,T185,T186
DetectSt->StableSt	191	Covered	T37,T38,T39
IdleSt->DebounceSt	148	Covered	T7,T37,T38
StableSt->IdleSt	206	Covered	T39,T41,T166

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T37,T38
0	1	Covered	T7,T37,T38
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T37,T38,T39
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T37,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T37,T38,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T38,T188
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T37,T38
DetectSt	-	-	-	-	1	-	-	Covered	T117,T185,T186
DetectSt	-	-	-	-	0	1	-	Covered	T37,T38,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T41,T166,T187
StableSt	-	-	-	-	-	-	0	Covered	T37,T38,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8695005	133	0	0
CntIncr_A	8695005	64689	0	0
CntNoWrap_A	8695005	8013190	0	0
DetectStDropOut_A	8695005	3	0	0
DetectedOut_A	8695005	169872	0	0
DetectedPulseOut_A	8695005	59	0	0
DisabledIdleSt_A	8695005	7770010	0	0
DisabledNoDetection_A	8695005	7772394	0	0
EnterDebounceSt_A	8695005	72	0	0
EnterDetectSt_A	8695005	62	0	0
EnterStableSt_A	8695005	59	0	0
PulseIsPulse_A	8695005	59	0	0
StayInStableSt	8695005	169780	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8695005	3077	0	0
gen_low_level_sva.LowLevelEvent_A	8695005	8015761	0	0
gen_not_sticky_sva.StableStDropOut_A	8695005	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	133	0	0
T7	498	1	0	0
T8	987	0	0	0
T9	160050	0	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	0	0	0
T22	496	0	0	0
T23	2248	0	0	0
T26	5716	0	0	0
T37	0	2	0	0
T38	0	3	0	0
T39	0	2	0	0
T41	0	4	0	0
T53	422	0	0	0
T164	0	2	0	0
T165	0	2	0	0
T166	0	4	0	0
T168	0	2	0	0
T187	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	64689	0	0
T7	498	23	0	0
T8	987	0	0	0
T9	160050	0	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	0	0	0
T22	496	0	0	0
T23	2248	0	0	0
T26	5716	0	0	0
T37	0	55	0	0
T38	0	100	0	0
T39	0	16	0	0
T41	0	134	0	0
T53	422	0	0	0
T164	0	90	0	0
T165	0	30	0	0
T166	0	180	0	0
T168	0	57602	0	0
T187	0	67	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8013190	0	0
T1	521	120	0	0
T2	30724	29434	0	0
T3	771	370	0	0
T4	19423	18989	0	0
T5	402	1	0	0
T6	1089	688	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	3	0	0
T117	20697	1	0	0
T148	498	0	0	0
T149	953	0	0	0
T150	12767	0	0	0
T151	674	0	0	0
T152	65864	0	0	0
T153	489	0	0	0
T154	24860	0	0	0
T155	403	0	0	0
T156	607	0	0	0
T185	0	1	0	0
T186	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	169872	0	0
T25	699	0	0	0
T33	23864	0	0	0
T35	0	181	0	0
T37	876	411	0	0
T38	0	53	0	0
T39	0	64	0	0
T41	0	82	0	0
T45	17205	0	0	0
T65	526	0	0	0
T71	5620	0	0	0
T72	4816	0	0	0
T111	26677	0	0	0
T164	0	478	0	0
T165	0	47	0	0
T166	0	391	0	0
T168	0	163546	0	0
T187	0	51	0	0
T189	6799	0	0	0
T190	446	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	59	0	0
T25	699	0	0	0
T33	23864	0	0	0
T35	0	1	0	0
T37	876	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	2	0	0
T45	17205	0	0	0
T65	526	0	0	0
T71	5620	0	0	0
T72	4816	0	0	0
T111	26677	0	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	2	0	0
T168	0	1	0	0
T187	0	1	0	0
T189	6799	0	0	0
T190	446	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	7770010	0	0
T1	521	120	0	0
T2	30724	29434	0	0
T3	771	370	0	0
T4	19423	18989	0	0
T5	402	1	0	0
T6	1089	688	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	7772394	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	72	0	0
T7	498	1	0	0
T8	987	0	0	0
T9	160050	0	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	0	0	0
T22	496	0	0	0
T23	2248	0	0	0
T26	5716	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	2	0	0
T53	422	0	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	2	0	0
T168	0	1	0	0
T187	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	62	0	0
T25	699	0	0	0
T33	23864	0	0	0
T35	0	1	0	0
T37	876	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	2	0	0
T45	17205	0	0	0
T65	526	0	0	0
T71	5620	0	0	0
T72	4816	0	0	0
T111	26677	0	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	2	0	0
T168	0	1	0	0
T187	0	1	0	0
T189	6799	0	0	0
T190	446	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	59	0	0
T25	699	0	0	0
T33	23864	0	0	0
T35	0	1	0	0
T37	876	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	2	0	0
T45	17205	0	0	0
T65	526	0	0	0
T71	5620	0	0	0
T72	4816	0	0	0
T111	26677	0	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	2	0	0
T168	0	1	0	0
T187	0	1	0	0
T189	6799	0	0	0
T190	446	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	59	0	0
T25	699	0	0	0
T33	23864	0	0	0
T35	0	1	0	0
T37	876	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	2	0	0
T45	17205	0	0	0
T65	526	0	0	0
T71	5620	0	0	0
T72	4816	0	0	0
T111	26677	0	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	2	0	0
T168	0	1	0	0
T187	0	1	0	0
T189	6799	0	0	0
T190	446	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	169780	0	0
T25	699	0	0	0
T33	23864	0	0	0
T35	0	180	0	0
T37	876	409	0	0
T38	0	51	0	0
T39	0	62	0	0
T41	0	79	0	0
T45	17205	0	0	0
T65	526	0	0	0
T71	5620	0	0	0
T72	4816	0	0	0
T111	26677	0	0	0
T164	0	476	0	0
T165	0	45	0	0
T166	0	388	0	0
T168	0	163544	0	0
T187	0	50	0	0
T189	6799	0	0	0
T190	446	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	3077	0	0
T1	521	1	0	0
T2	30724	5	0	0
T3	771	1	0	0
T6	1089	2	0	0
T7	498	1	0	0
T9	0	38	0	0
T13	446	4	0	0
T14	643	0	0	0
T15	2573	8	0	0
T16	595	2	0	0
T17	5366	0	0	0
T22	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8015761	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	26	0	0
T35	0	1	0	0
T36	0	1	0	0
T41	997	1	0	0
T43	0	2	0	0
T58	1177	0	0	0
T59	9707	0	0	0
T146	0	1	0	0
T164	977	0	0	0
T166	1116	1	0	0
T169	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0
T178	503	0	0	0
T187	0	1	0	0
T191	503	0	0	0
T192	28882	0	0	0
T193	4415	0	0	0
T194	13050	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T1,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T1,T13
1	1	Covered	T4,T1,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T9,T38,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T9,T38,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T38,T40,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T38,T40
1	0	Covered	T4,T1,T13
1	1	Covered	T9,T38,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T40,T39,T41
0	1	Covered	T38,T146,T145
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T40,T39,T41
0	1	Covered	T40,T41,T164
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T40,T39,T41
1	-	Covered	T40,T41,T164

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T38,T40
DetectSt	168	Covered	T38,T40,T39
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T40,T39,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T38,T40,T39
DebounceSt->IdleSt	163	Covered	T9,T42,T83
DetectSt->IdleSt	186	Covered	T38,T146,T145
DetectSt->StableSt	191	Covered	T40,T39,T41
IdleSt->DebounceSt	148	Covered	T9,T38,T40
StableSt->IdleSt	206	Covered	T40,T39,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T38,T40
0	1	Covered	T9,T38,T40
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T38,T40,T39
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T38,T40
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T38,T40,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T42,T83
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T38,T40
DetectSt	-	-	-	-	1	-	-	Covered	T38,T146,T145
DetectSt	-	-	-	-	0	1	-	Covered	T40,T39,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T41,T164
StableSt	-	-	-	-	-	-	0	Covered	T40,T39,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8695005	121	0	0
CntIncr_A	8695005	139656	0	0
CntNoWrap_A	8695005	8013202	0	0
DetectStDropOut_A	8695005	3	0	0
DetectedOut_A	8695005	53170	0	0
DetectedPulseOut_A	8695005	53	0	0
DisabledIdleSt_A	8695005	7746214	0	0
DisabledNoDetection_A	8695005	7748604	0	0
EnterDebounceSt_A	8695005	66	0	0
EnterDetectSt_A	8695005	56	0	0
EnterStableSt_A	8695005	53	0	0
PulseIsPulse_A	8695005	53	0	0
StayInStableSt	8695005	53090	0	0
gen_high_level_sva.HighLevelEvent_A	8695005	8015761	0	0
gen_not_sticky_sva.StableStDropOut_A	8695005	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	121	0	0
T9	160050	1	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	0	0	0
T23	2248	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T35	0	2	0	0
T36	0	8	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	4	0	0
T53	422	0	0	0
T64	523	0	0	0
T164	0	4	0	0
T168	0	4	0	0
T187	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	139656	0	0
T9	160050	79	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	0	0	0
T23	2248	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T35	0	61	0	0
T36	0	270	0	0
T38	0	50	0	0
T39	0	17	0	0
T40	0	98	0	0
T41	0	134	0	0
T53	422	0	0	0
T64	523	0	0	0
T164	0	180	0	0
T168	0	115204	0	0
T187	0	67	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8013202	0	0
T1	521	120	0	0
T2	30724	29434	0	0
T3	771	370	0	0
T4	19423	18989	0	0
T5	402	1	0	0
T6	1089	688	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	3	0	0
T34	19163	0	0	0
T38	732	1	0	0
T54	753	0	0	0
T55	1244	0	0	0
T56	4345	0	0	0
T67	502	0	0	0
T89	20167	0	0	0
T145	0	1	0	0
T146	0	1	0	0
T195	415	0	0	0
T196	446	0	0	0
T197	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	53170	0	0
T35	0	50	0	0
T36	0	253	0	0
T39	15545	123	0	0
T40	1047	60	0	0
T41	0	100	0	0
T42	0	40	0	0
T46	723	0	0	0
T68	506	0	0	0
T90	5519	0	0	0
T91	5417	0	0	0
T158	425	0	0	0
T159	437	0	0	0
T164	0	226	0	0
T168	0	48297	0	0
T172	0	56	0	0
T187	0	165	0	0
T198	16271	0	0	0
T199	424	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	53	0	0
T35	0	1	0	0
T36	0	4	0	0
T39	15545	1	0	0
T40	1047	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T46	723	0	0	0
T68	506	0	0	0
T90	5519	0	0	0
T91	5417	0	0	0
T158	425	0	0	0
T159	437	0	0	0
T164	0	2	0	0
T168	0	2	0	0
T172	0	1	0	0
T187	0	1	0	0
T198	16271	0	0	0
T199	424	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	7746214	0	0
T1	521	120	0	0
T2	30724	29434	0	0
T3	771	370	0	0
T4	19423	18989	0	0
T5	402	1	0	0
T6	1089	688	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	7748604	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	66	0	0
T9	160050	1	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T12	1470	0	0	0
T23	2248	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T31	19687	0	0	0
T35	0	1	0	0
T36	0	4	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T53	422	0	0	0
T64	523	0	0	0
T164	0	2	0	0
T168	0	2	0	0
T187	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	56	0	0
T34	19163	0	0	0
T35	0	1	0	0
T36	0	4	0	0
T38	732	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T54	753	0	0	0
T55	1244	0	0	0
T56	4345	0	0	0
T67	502	0	0	0
T89	20167	0	0	0
T164	0	2	0	0
T168	0	2	0	0
T187	0	1	0	0
T195	415	0	0	0
T196	446	0	0	0
T197	422	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	53	0	0
T35	0	1	0	0
T36	0	4	0	0
T39	15545	1	0	0
T40	1047	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T46	723	0	0	0
T68	506	0	0	0
T90	5519	0	0	0
T91	5417	0	0	0
T158	425	0	0	0
T159	437	0	0	0
T164	0	2	0	0
T168	0	2	0	0
T172	0	1	0	0
T187	0	1	0	0
T198	16271	0	0	0
T199	424	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	53	0	0
T35	0	1	0	0
T36	0	4	0	0
T39	15545	1	0	0
T40	1047	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T46	723	0	0	0
T68	506	0	0	0
T90	5519	0	0	0
T91	5417	0	0	0
T158	425	0	0	0
T159	437	0	0	0
T164	0	2	0	0
T168	0	2	0	0
T172	0	1	0	0
T187	0	1	0	0
T198	16271	0	0	0
T199	424	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	53090	0	0
T35	0	48	0	0
T36	0	247	0	0
T39	15545	121	0	0
T40	1047	59	0	0
T41	0	97	0	0
T42	0	38	0	0
T46	723	0	0	0
T68	506	0	0	0
T90	5519	0	0	0
T91	5417	0	0	0
T158	425	0	0	0
T159	437	0	0	0
T164	0	223	0	0
T168	0	48294	0	0
T172	0	55	0	0
T187	0	163	0	0
T198	16271	0	0	0
T199	424	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8015761	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	26	0	0
T36	0	2	0	0
T39	15545	0	0	0
T40	1047	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T46	723	0	0	0
T68	506	0	0	0
T90	5519	0	0	0
T91	5417	0	0	0
T117	0	2	0	0
T146	0	1	0	0
T158	425	0	0	0
T159	437	0	0	0
T164	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0
T172	0	1	0	0
T198	16271	0	0	0
T199	424	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T13
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T13
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T9,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T9,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T9,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T38
1	0	Covered	T4,T1,T13
1	1	Covered	T3,T9,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T38
0	1	Covered	T157
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T38
0	1	Covered	T3,T39,T168
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T9,T38
1	-	Covered	T3,T39,T168

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T9,T38
DetectSt	168	Covered	T3,T9,T38
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T9,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T9,T38
DebounceSt->IdleSt	163	Covered	T77,T73,T74
DetectSt->IdleSt	186	Covered	T157
DetectSt->StableSt	191	Covered	T3,T9,T38
IdleSt->DebounceSt	148	Covered	T3,T9,T38
StableSt->IdleSt	206	Covered	T3,T9,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T9,T38
0	1	Covered	T3,T9,T38
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T38
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T9,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T9,T38
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T9,T38
DetectSt	-	-	-	-	1	-	-	Covered	T157
DetectSt	-	-	-	-	0	1	-	Covered	T3,T9,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T39,T168
StableSt	-	-	-	-	-	-	0	Covered	T3,T9,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8695005	66	0	0
CntIncr_A	8695005	97542	0	0
CntNoWrap_A	8695005	8013257	0	0
DetectStDropOut_A	8695005	1	0	0
DetectedOut_A	8695005	2796	0	0
DetectedPulseOut_A	8695005	31	0	0
DisabledIdleSt_A	8695005	7404673	0	0
DisabledNoDetection_A	8695005	7407061	0	0
EnterDebounceSt_A	8695005	35	0	0
EnterDetectSt_A	8695005	32	0	0
EnterStableSt_A	8695005	31	0	0
PulseIsPulse_A	8695005	31	0	0
StayInStableSt	8695005	2748	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8695005	6628	0	0
gen_low_level_sva.LowLevelEvent_A	8695005	8015761	0	0
gen_not_sticky_sva.StableStDropOut_A	8695005	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	66	0	0
T3	771	4	0	0
T6	1089	0	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	4	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	496	0	0	0
T23	2248	0	0	0
T35	0	2	0	0
T36	0	4	0	0
T38	0	2	0	0
T39	0	4	0	0
T40	0	2	0	0
T78	0	2	0	0
T165	0	2	0	0
T168	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	97542	0	0
T3	771	80	0	0
T6	1089	0	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	179	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	496	0	0	0
T23	2248	0	0	0
T35	0	29	0	0
T36	0	135	0	0
T38	0	50	0	0
T39	0	74	0	0
T40	0	98	0	0
T77	0	20383	0	0
T165	0	30	0	0
T168	0	57602	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8013257	0	0
T1	521	120	0	0
T2	30724	29434	0	0
T3	771	366	0	0
T4	19423	18989	0	0
T5	402	1	0	0
T6	1089	688	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	1	0	0
T80	16768	0	0	0
T157	786	1	0	0
T200	420	0	0	0
T201	2668	0	0	0
T202	441	0	0	0
T203	504	0	0	0
T204	885	0	0	0
T205	4770	0	0	0
T206	3608	0	0	0
T207	1417	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	2796	0	0
T3	771	91	0	0
T6	1089	0	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	114	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	496	0	0	0
T23	2248	0	0	0
T35	0	151	0	0
T36	0	339	0	0
T38	0	221	0	0
T39	0	85	0	0
T40	0	381	0	0
T78	0	41	0	0
T165	0	47	0	0
T168	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	31	0	0
T3	771	2	0	0
T6	1089	0	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	2	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	496	0	0	0
T23	2248	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T78	0	1	0	0
T165	0	1	0	0
T168	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	7404673	0	0
T1	521	120	0	0
T2	30724	29434	0	0
T3	771	3	0	0
T4	19423	18989	0	0
T5	402	1	0	0
T6	1089	688	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	7407061	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	3	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	35	0	0
T3	771	2	0	0
T6	1089	0	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	2	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	496	0	0	0
T23	2248	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T77	0	1	0	0
T165	0	1	0	0
T168	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	32	0	0
T3	771	2	0	0
T6	1089	0	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	2	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	496	0	0	0
T23	2248	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T78	0	1	0	0
T165	0	1	0	0
T168	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	31	0	0
T3	771	2	0	0
T6	1089	0	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	2	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	496	0	0	0
T23	2248	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T78	0	1	0	0
T165	0	1	0	0
T168	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	31	0	0
T3	771	2	0	0
T6	1089	0	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	2	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	496	0	0	0
T23	2248	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T78	0	1	0	0
T165	0	1	0	0
T168	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	2748	0	0
T3	771	88	0	0
T6	1089	0	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	110	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	496	0	0	0
T23	2248	0	0	0
T35	0	150	0	0
T36	0	337	0	0
T38	0	219	0	0
T39	0	82	0	0
T40	0	379	0	0
T78	0	39	0	0
T165	0	45	0	0
T168	0	42	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	6628	0	0
T1	521	1	0	0
T2	30724	20	0	0
T3	771	2	0	0
T4	19423	27	0	0
T5	402	0	0	0
T6	1089	1	0	0
T8	0	4	0	0
T13	446	6	0	0
T14	643	0	0	0
T15	2573	4	0	0
T16	595	0	0	0
T17	0	21	0	0
T22	0	10	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8015761	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	14	0	0
T3	771	1	0	0
T6	1089	0	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	496	0	0	0
T23	2248	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T39	0	1	0	0
T118	0	1	0	0
T163	0	1	0	0
T168	0	1	0	0
T174	0	1	0	0
T208	0	1	0	0
T209	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T1,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T1,T13
1	1	Covered	T4,T1,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T3,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T3,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T3,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T9
1	0	Covered	T4,T13,T2
1	1	Covered	T1,T3,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T9
0	1	Covered	T36,T43,T83
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T9
0	1	Covered	T3,T70,T164
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T9
1	-	Covered	T3,T70,T164

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T9
DetectSt	168	Covered	T1,T3,T9
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T3,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T9
DebounceSt->IdleSt	163	Covered	T37,T39,T165
DetectSt->IdleSt	186	Covered	T36,T43,T83
DetectSt->StableSt	191	Covered	T1,T3,T9
IdleSt->DebounceSt	148	Covered	T1,T3,T9
StableSt->IdleSt	206	Covered	T3,T9,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T9
0	1	Covered	T1,T3,T9
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T37,T39,T165
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T9
DetectSt	-	-	-	-	1	-	-	Covered	T36,T43,T83
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T70,T164
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8695005	120	0	0
CntIncr_A	8695005	79282	0	0
CntNoWrap_A	8695005	8013203	0	0
DetectStDropOut_A	8695005	4	0	0
DetectedOut_A	8695005	111169	0	0
DetectedPulseOut_A	8695005	50	0	0
DisabledIdleSt_A	8695005	7749508	0	0
DisabledNoDetection_A	8695005	7751895	0	0
EnterDebounceSt_A	8695005	66	0	0
EnterDetectSt_A	8695005	54	0	0
EnterStableSt_A	8695005	50	0	0
PulseIsPulse_A	8695005	50	0	0
StayInStableSt	8695005	111095	0	0
gen_high_level_sva.HighLevelEvent_A	8695005	8015761	0	0
gen_not_sticky_sva.StableStDropOut_A	8695005	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	120	0	0
T1	521	2	0	0
T2	30724	0	0	0
T3	771	4	0	0
T6	1089	0	0	0
T7	498	0	0	0
T9	0	2	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T37	0	3	0	0
T39	0	3	0	0
T70	0	2	0	0
T164	0	2	0	0
T165	0	1	0	0
T166	0	6	0	0
T168	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	79282	0	0
T1	521	29	0	0
T2	30724	0	0	0
T3	771	80	0	0
T6	1089	0	0	0
T7	498	0	0	0
T9	0	100	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T37	0	110	0	0
T39	0	32	0	0
T70	0	85	0	0
T164	0	90	0	0
T165	0	30	0	0
T166	0	270	0	0
T168	0	57602	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8013203	0	0
T1	521	118	0	0
T2	30724	29434	0	0
T3	771	366	0	0
T4	19423	18989	0	0
T5	402	1	0	0
T6	1089	688	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	4	0	0
T36	15068	1	0	0
T42	124553	0	0	0
T43	0	1	0	0
T83	0	1	0	0
T136	423	0	0	0
T137	12387	0	0	0
T138	22789	0	0	0
T139	522	0	0	0
T140	689	0	0	0
T141	490	0	0	0
T142	2155	0	0	0
T210	0	1	0	0
T211	535	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	111169	0	0
T1	521	82	0	0
T2	30724	0	0	0
T3	771	235	0	0
T6	1089	0	0	0
T7	498	0	0	0
T9	0	541	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T37	0	44	0	0
T39	0	42	0	0
T70	0	27	0	0
T164	0	40	0	0
T166	0	203	0	0
T168	0	105898	0	0
T187	0	164	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	50	0	0
T1	521	1	0	0
T2	30724	0	0	0
T3	771	2	0	0
T6	1089	0	0	0
T7	498	0	0	0
T9	0	1	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T70	0	1	0	0
T164	0	1	0	0
T166	0	3	0	0
T168	0	1	0	0
T187	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	7749508	0	0
T1	521	4	0	0
T2	30724	29434	0	0
T3	771	3	0	0
T4	19423	18989	0	0
T5	402	1	0	0
T6	1089	688	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	7751895	0	0
T1	521	4	0	0
T2	30724	29448	0	0
T3	771	3	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	66	0	0
T1	521	1	0	0
T2	30724	0	0	0
T3	771	2	0	0
T6	1089	0	0	0
T7	498	0	0	0
T9	0	1	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T37	0	2	0	0
T39	0	2	0	0
T70	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	3	0	0
T168	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	54	0	0
T1	521	1	0	0
T2	30724	0	0	0
T3	771	2	0	0
T6	1089	0	0	0
T7	498	0	0	0
T9	0	1	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T70	0	1	0	0
T164	0	1	0	0
T166	0	3	0	0
T168	0	1	0	0
T187	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	50	0	0
T1	521	1	0	0
T2	30724	0	0	0
T3	771	2	0	0
T6	1089	0	0	0
T7	498	0	0	0
T9	0	1	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T70	0	1	0	0
T164	0	1	0	0
T166	0	3	0	0
T168	0	1	0	0
T187	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	50	0	0
T1	521	1	0	0
T2	30724	0	0	0
T3	771	2	0	0
T6	1089	0	0	0
T7	498	0	0	0
T9	0	1	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T70	0	1	0	0
T164	0	1	0	0
T166	0	3	0	0
T168	0	1	0	0
T187	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	111095	0	0
T1	521	80	0	0
T2	30724	0	0	0
T3	771	232	0	0
T6	1089	0	0	0
T7	498	0	0	0
T9	0	539	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T37	0	42	0	0
T39	0	40	0	0
T70	0	26	0	0
T164	0	39	0	0
T166	0	199	0	0
T168	0	105897	0	0
T187	0	162	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8015761	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	26	0	0
T3	771	1	0	0
T6	1089	0	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	496	0	0	0
T23	2248	0	0	0
T70	0	1	0	0
T147	0	1	0	0
T164	0	1	0	0
T166	0	2	0	0
T168	0	1	0	0
T212	0	1	0	0
T213	0	1	0	0
T214	0	1	0	0
T215	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T13
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T13
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T37,T38,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T37,T38,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T37,T38,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T9
1	0	Covered	T4,T13,T2
1	1	Covered	T37,T38,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T37,T38,T39
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T37,T38,T39
0	1	Covered	T37,T39,T36
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T37,T38,T39
1	-	Covered	T37,T39,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T37,T38,T39
DetectSt	168	Covered	T37,T38,T39
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T37,T38,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T37,T38,T39
DebounceSt->IdleSt	163	Covered	T95,T157,T73
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T37,T38,T39
IdleSt->DebounceSt	148	Covered	T37,T38,T39
StableSt->IdleSt	206	Covered	T37,T39,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T37,T38,T39
0	1	Covered	T37,T38,T39
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T37,T38,T39
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T37,T38,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T37,T38,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T95,T157,T143
DebounceSt	-	0	0	-	-	-	-	Covered	T37,T38,T39
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T37,T38,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T37,T39,T36
StableSt	-	-	-	-	-	-	0	Covered	T37,T38,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8695005	73	0	0
CntIncr_A	8695005	60048	0	0
CntNoWrap_A	8695005	8013250	0	0
DetectStDropOut_A	8695005	0	0	0
DetectedOut_A	8695005	3387	0	0
DetectedPulseOut_A	8695005	34	0	0
DisabledIdleSt_A	8695005	7775058	0	0
DisabledNoDetection_A	8695005	7777448	0	0
EnterDebounceSt_A	8695005	39	0	0
EnterDetectSt_A	8695005	34	0	0
EnterStableSt_A	8695005	34	0	0
PulseIsPulse_A	8695005	34	0	0
StayInStableSt	8695005	3335	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8695005	6226	0	0
gen_low_level_sva.LowLevelEvent_A	8695005	8015761	0	0
gen_not_sticky_sva.StableStDropOut_A	8695005	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	73	0	0
T25	699	0	0	0
T33	23864	0	0	0
T36	0	4	0	0
T37	876	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T43	0	2	0	0
T45	17205	0	0	0
T65	526	0	0	0
T71	5620	0	0	0
T72	4816	0	0	0
T95	0	1	0	0
T111	26677	0	0	0
T146	0	2	0	0
T164	0	2	0	0
T168	0	2	0	0
T172	0	4	0	0
T189	6799	0	0	0
T190	446	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	60048	0	0
T25	699	0	0	0
T33	23864	0	0	0
T36	0	128	0	0
T37	876	55	0	0
T38	0	50	0	0
T39	0	16	0	0
T43	0	18	0	0
T45	17205	0	0	0
T65	526	0	0	0
T71	5620	0	0	0
T72	4816	0	0	0
T95	0	41	0	0
T111	26677	0	0	0
T146	0	87	0	0
T164	0	90	0	0
T168	0	57602	0	0
T172	0	150	0	0
T189	6799	0	0	0
T190	446	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8013250	0	0
T1	521	120	0	0
T2	30724	29434	0	0
T3	771	370	0	0
T4	19423	18989	0	0
T5	402	1	0	0
T6	1089	688	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	3387	0	0
T25	699	0	0	0
T33	23864	0	0	0
T36	0	162	0	0
T37	876	273	0	0
T38	0	131	0	0
T39	0	66	0	0
T43	0	39	0	0
T45	17205	0	0	0
T65	526	0	0	0
T71	5620	0	0	0
T72	4816	0	0	0
T83	0	43	0	0
T111	26677	0	0	0
T146	0	34	0	0
T164	0	199	0	0
T168	0	45	0	0
T172	0	85	0	0
T189	6799	0	0	0
T190	446	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	34	0	0
T25	699	0	0	0
T33	23864	0	0	0
T36	0	2	0	0
T37	876	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T43	0	1	0	0
T45	17205	0	0	0
T65	526	0	0	0
T71	5620	0	0	0
T72	4816	0	0	0
T83	0	1	0	0
T111	26677	0	0	0
T146	0	1	0	0
T164	0	1	0	0
T168	0	1	0	0
T172	0	2	0	0
T189	6799	0	0	0
T190	446	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	7775058	0	0
T1	521	4	0	0
T2	30724	29434	0	0
T3	771	370	0	0
T4	19423	18989	0	0
T5	402	1	0	0
T6	1089	688	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	7777448	0	0
T1	521	4	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	39	0	0
T25	699	0	0	0
T33	23864	0	0	0
T36	0	2	0	0
T37	876	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T43	0	1	0	0
T45	17205	0	0	0
T65	526	0	0	0
T71	5620	0	0	0
T72	4816	0	0	0
T95	0	1	0	0
T111	26677	0	0	0
T146	0	1	0	0
T164	0	1	0	0
T168	0	1	0	0
T172	0	2	0	0
T189	6799	0	0	0
T190	446	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	34	0	0
T25	699	0	0	0
T33	23864	0	0	0
T36	0	2	0	0
T37	876	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T43	0	1	0	0
T45	17205	0	0	0
T65	526	0	0	0
T71	5620	0	0	0
T72	4816	0	0	0
T83	0	1	0	0
T111	26677	0	0	0
T146	0	1	0	0
T164	0	1	0	0
T168	0	1	0	0
T172	0	2	0	0
T189	6799	0	0	0
T190	446	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	34	0	0
T25	699	0	0	0
T33	23864	0	0	0
T36	0	2	0	0
T37	876	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T43	0	1	0	0
T45	17205	0	0	0
T65	526	0	0	0
T71	5620	0	0	0
T72	4816	0	0	0
T83	0	1	0	0
T111	26677	0	0	0
T146	0	1	0	0
T164	0	1	0	0
T168	0	1	0	0
T172	0	2	0	0
T189	6799	0	0	0
T190	446	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	34	0	0
T25	699	0	0	0
T33	23864	0	0	0
T36	0	2	0	0
T37	876	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T43	0	1	0	0
T45	17205	0	0	0
T65	526	0	0	0
T71	5620	0	0	0
T72	4816	0	0	0
T83	0	1	0	0
T111	26677	0	0	0
T146	0	1	0	0
T164	0	1	0	0
T168	0	1	0	0
T172	0	2	0	0
T189	6799	0	0	0
T190	446	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	3335	0	0
T25	699	0	0	0
T33	23864	0	0	0
T36	0	160	0	0
T37	876	272	0	0
T38	0	129	0	0
T39	0	65	0	0
T43	0	38	0	0
T45	17205	0	0	0
T65	526	0	0	0
T71	5620	0	0	0
T72	4816	0	0	0
T83	0	41	0	0
T111	26677	0	0	0
T146	0	33	0	0
T164	0	197	0	0
T168	0	43	0	0
T172	0	82	0	0
T189	6799	0	0	0
T190	446	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	6226	0	0
T1	521	0	0	0
T2	30724	17	0	0
T3	771	1	0	0
T4	19423	24	0	0
T5	402	0	0	0
T6	1089	0	0	0
T9	0	21	0	0
T10	0	10	0	0
T13	446	5	0	0
T14	643	0	0	0
T15	2573	5	0	0
T16	595	0	0	0
T17	0	25	0	0
T22	0	7	0	0
T23	0	19	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8015761	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	16	0	0
T25	699	0	0	0
T33	23864	0	0	0
T36	0	2	0	0
T37	876	1	0	0
T39	0	1	0	0
T43	0	1	0	0
T45	17205	0	0	0
T65	526	0	0	0
T71	5620	0	0	0
T72	4816	0	0	0
T111	26677	0	0	0
T117	0	1	0	0
T118	0	1	0	0
T146	0	1	0	0
T172	0	1	0	0
T189	6799	0	0	0
T190	446	0	0	0
T216	0	1	0	0
T217	0	1	0	0