Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T17,T26
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T17,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T17,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T17,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T17,T26
1	0	Covered	T4,T44,T32
1	1	Covered	T4,T17,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T17,T26
0	1	Covered	T17,T26,T71
1	0	Covered	T45,T92,T243

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T44,T32
0	1	Covered	T4,T44,T32
1	0	Covered	T81

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T44,T32
1	-	Covered	T4,T44,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T17,T26
DetectSt	168	Covered	T4,T17,T26
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T4,T44,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T17,T26
DebounceSt->IdleSt	163	Covered	T244,T232,T150
DetectSt->IdleSt	186	Covered	T17,T26,T71
DetectSt->StableSt	191	Covered	T4,T44,T32
IdleSt->DebounceSt	148	Covered	T4,T17,T26
StableSt->IdleSt	206	Covered	T4,T44,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T17,T26
0	1	Covered	T4,T17,T26
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T17,T26
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T4,T17,T26
IdleSt	0	-	-	-	-	-	-	Covered	T4,T17,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T17,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T244,T232,T150
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T17,T26
DetectSt	-	-	-	-	1	-	-	Covered	T17,T26,T71
DetectSt	-	-	-	-	0	1	-	Covered	T4,T44,T32
DetectSt	-	-	-	-	0	0	-	Covered	T4,T17,T26
StableSt	-	-	-	-	-	-	1	Covered	T4,T44,T32
StableSt	-	-	-	-	-	-	0	Covered	T4,T44,T32
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8695005	3139	0	0
CntIncr_A	8695005	109868	0	0
CntNoWrap_A	8695005	8010184	0	0
DetectStDropOut_A	8695005	497	0	0
DetectedOut_A	8695005	71514	0	0
DetectedPulseOut_A	8695005	911	0	0
DisabledIdleSt_A	8695005	7561385	0	0
DisabledNoDetection_A	8695005	7563609	0	0
EnterDebounceSt_A	8695005	1603	0	0
EnterDetectSt_A	8695005	1536	0	0
EnterStableSt_A	8695005	911	0	0
PulseIsPulse_A	8695005	911	0	0
StayInStableSt	8695005	70484	0	0
gen_high_event_sva.HighLevelEvent_A	8695005	8015761	0	0
gen_high_level_sva.HighLevelEvent_A	8695005	8015761	0	0
gen_not_sticky_sva.StableStDropOut_A	8695005	783	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	3139	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	30	0	0
T5	402	0	0	0
T6	1089	0	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	0	30	0	0
T26	0	20	0	0
T32	0	50	0	0
T33	0	52	0	0
T34	0	32	0	0
T44	0	38	0	0
T45	0	48	0	0
T71	0	22	0	0
T72	0	50	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	109868	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	645	0	0
T5	402	0	0	0
T6	1089	0	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	0	816	0	0
T26	0	617	0	0
T32	0	2150	0	0
T33	0	754	0	0
T34	0	1120	0	0
T44	0	1197	0	0
T45	0	1562	0	0
T71	0	652	0	0
T72	0	1101	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8010184	0	0
T1	521	120	0	0
T2	30724	29434	0	0
T3	771	370	0	0
T4	19423	18959	0	0
T5	402	1	0	0
T6	1089	688	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	497	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	0	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T17	5366	15	0	0
T22	496	0	0	0
T23	2248	0	0	0
T26	5716	10	0	0
T45	0	21	0	0
T53	422	0	0	0
T71	0	11	0	0
T72	0	25	0	0
T90	0	10	0	0
T91	0	29	0	0
T92	0	4	0	0
T93	0	15	0	0
T243	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	71514	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	1448	0	0
T5	402	0	0	0
T6	1089	0	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T32	0	1691	0	0
T33	0	1449	0	0
T34	0	283	0	0
T44	0	1900	0	0
T79	0	1067	0	0
T192	0	598	0	0
T194	0	884	0	0
T245	0	3381	0	0
T246	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	911	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	15	0	0
T5	402	0	0	0
T6	1089	0	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T32	0	25	0	0
T33	0	26	0	0
T34	0	16	0	0
T44	0	19	0	0
T79	0	16	0	0
T192	0	5	0	0
T194	0	28	0	0
T245	0	28	0	0
T246	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	7561385	0	0
T1	521	120	0	0
T2	30724	29434	0	0
T3	771	370	0	0
T4	19423	14702	0	0
T5	402	1	0	0
T6	1089	688	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	7563609	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	14705	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	1603	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	15	0	0
T5	402	0	0	0
T6	1089	0	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	0	15	0	0
T26	0	10	0	0
T32	0	25	0	0
T33	0	26	0	0
T34	0	16	0	0
T44	0	19	0	0
T45	0	24	0	0
T71	0	11	0	0
T72	0	25	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	1536	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	15	0	0
T5	402	0	0	0
T6	1089	0	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	0	15	0	0
T26	0	10	0	0
T32	0	25	0	0
T33	0	26	0	0
T34	0	16	0	0
T44	0	19	0	0
T45	0	24	0	0
T71	0	11	0	0
T72	0	25	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	911	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	15	0	0
T5	402	0	0	0
T6	1089	0	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T32	0	25	0	0
T33	0	26	0	0
T34	0	16	0	0
T44	0	19	0	0
T79	0	16	0	0
T192	0	5	0	0
T194	0	28	0	0
T245	0	28	0	0
T246	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	911	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	15	0	0
T5	402	0	0	0
T6	1089	0	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T32	0	25	0	0
T33	0	26	0	0
T34	0	16	0	0
T44	0	19	0	0
T79	0	16	0	0
T192	0	5	0	0
T194	0	28	0	0
T245	0	28	0	0
T246	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	70484	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	1430	0	0
T5	402	0	0	0
T6	1089	0	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T32	0	1659	0	0
T33	0	1422	0	0
T34	0	267	0	0
T44	0	1879	0	0
T79	0	1051	0	0
T192	0	591	0	0
T194	0	854	0	0
T245	0	3346	0	0
T246	0	42	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8015761	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8015761	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	783	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	12	0	0
T5	402	0	0	0
T6	1089	0	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T32	0	18	0	0
T33	0	25	0	0
T34	0	16	0	0
T44	0	17	0	0
T79	0	16	0	0
T192	0	3	0	0
T194	0	26	0	0
T245	0	21	0	0
T247	0	13	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T2,T17
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T17
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T2,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T4,T2,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T2,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T9
1	0	Covered	T4,T2,T15
1	1	Covered	T4,T2,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T2,T9
0	1	Covered	T11,T89,T42
1	0	Covered	T73,T74

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T2,T9
0	1	Covered	T2,T9,T10
1	0	Covered	T74

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T2,T9
1	-	Covered	T2,T9,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T2,T9
DetectSt	168	Covered	T4,T2,T9
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T4,T2,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T2,T9
DebounceSt->IdleSt	163	Covered	T2,T9,T23
DetectSt->IdleSt	186	Covered	T11,T89,T42
DetectSt->StableSt	191	Covered	T4,T2,T9
IdleSt->DebounceSt	148	Covered	T4,T2,T9
StableSt->IdleSt	206	Covered	T4,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T2,T9
0	1	Covered	T4,T2,T9
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T2,T9
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T2,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T2,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T9,T23
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T2,T9
DetectSt	-	-	-	-	1	-	-	Covered	T11,T89,T42
DetectSt	-	-	-	-	0	1	-	Covered	T4,T2,T9
DetectSt	-	-	-	-	0	0	-	Covered	T4,T2,T9
StableSt	-	-	-	-	-	-	1	Covered	T2,T9,T10
StableSt	-	-	-	-	-	-	0	Covered	T4,T2,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8695005	928	0	0
CntIncr_A	8695005	47536	0	0
CntNoWrap_A	8695005	8012395	0	0
DetectStDropOut_A	8695005	44	0	0
DetectedOut_A	8695005	16411	0	0
DetectedPulseOut_A	8695005	375	0	0
DisabledIdleSt_A	8695005	7648155	0	0
DisabledNoDetection_A	8695005	7649861	0	0
EnterDebounceSt_A	8695005	506	0	0
EnterDetectSt_A	8695005	424	0	0
EnterStableSt_A	8695005	375	0	0
PulseIsPulse_A	8695005	375	0	0
StayInStableSt	8695005	15990	0	0
gen_high_level_sva.HighLevelEvent_A	8695005	8015761	0	0
gen_not_sticky_sva.StableStDropOut_A	8695005	324	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	928	0	0
T1	521	0	0	0
T2	30724	25	0	0
T3	771	0	0	0
T4	19423	4	0	0
T5	402	0	0	0
T6	1089	0	0	0
T9	0	3	0	0
T10	0	4	0	0
T11	0	6	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T23	0	1	0	0
T30	0	8	0	0
T31	0	6	0	0
T32	0	12	0	0
T44	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	47536	0	0
T1	521	0	0	0
T2	30724	638	0	0
T3	771	0	0	0
T4	19423	126	0	0
T5	402	0	0	0
T6	1089	0	0	0
T9	0	45	0	0
T10	0	314	0	0
T11	0	246	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T23	0	20	0	0
T30	0	344	0	0
T31	0	788	0	0
T32	0	426	0	0
T44	0	78	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8012395	0	0
T1	521	120	0	0
T2	30724	29409	0	0
T3	771	370	0	0
T4	19423	18985	0	0
T5	402	1	0	0
T6	1089	688	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	44	0	0
T11	12776	3	0	0
T12	1470	0	0	0
T24	522	0	0	0
T30	7421	0	0	0
T31	19687	0	0	0
T42	0	1	0	0
T60	1314	0	0	0
T64	523	0	0	0
T89	0	3	0	0
T95	0	1	0	0
T96	0	7	0	0
T97	0	10	0	0
T98	0	2	0	0
T99	0	2	0	0
T100	0	2	0	0
T101	0	3	0	0
T102	462	0	0	0
T103	416	0	0	0
T104	426	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	16411	0	0
T1	521	0	0	0
T2	30724	561	0	0
T3	771	0	0	0
T4	19423	88	0	0
T5	402	0	0	0
T6	1089	0	0	0
T9	0	5	0	0
T10	0	57	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T30	0	328	0	0
T31	0	23	0	0
T32	0	345	0	0
T44	0	54	0	0
T56	0	3	0	0
T111	0	411	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	375	0	0
T1	521	0	0	0
T2	30724	12	0	0
T3	771	0	0	0
T4	19423	2	0	0
T5	402	0	0	0
T6	1089	0	0	0
T9	0	1	0	0
T10	0	2	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T30	0	4	0	0
T31	0	2	0	0
T32	0	6	0	0
T44	0	1	0	0
T56	0	1	0	0
T111	0	7	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	7648155	0	0
T1	521	120	0	0
T2	30724	26309	0	0
T3	771	370	0	0
T4	19423	17544	0	0
T5	402	1	0	0
T6	1089	688	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	7649861	0	0
T1	521	121	0	0
T2	30724	26310	0	0
T3	771	371	0	0
T4	19423	17548	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	506	0	0
T1	521	0	0	0
T2	30724	13	0	0
T3	771	0	0	0
T4	19423	2	0	0
T5	402	0	0	0
T6	1089	0	0	0
T9	0	2	0	0
T10	0	2	0	0
T11	0	3	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T23	0	1	0	0
T30	0	4	0	0
T31	0	4	0	0
T32	0	6	0	0
T44	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	424	0	0
T1	521	0	0	0
T2	30724	12	0	0
T3	771	0	0	0
T4	19423	2	0	0
T5	402	0	0	0
T6	1089	0	0	0
T9	0	1	0	0
T10	0	2	0	0
T11	0	3	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T30	0	4	0	0
T31	0	2	0	0
T32	0	6	0	0
T44	0	1	0	0
T111	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	375	0	0
T1	521	0	0	0
T2	30724	12	0	0
T3	771	0	0	0
T4	19423	2	0	0
T5	402	0	0	0
T6	1089	0	0	0
T9	0	1	0	0
T10	0	2	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T30	0	4	0	0
T31	0	2	0	0
T32	0	6	0	0
T44	0	1	0	0
T56	0	1	0	0
T111	0	7	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	375	0	0
T1	521	0	0	0
T2	30724	12	0	0
T3	771	0	0	0
T4	19423	2	0	0
T5	402	0	0	0
T6	1089	0	0	0
T9	0	1	0	0
T10	0	2	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T30	0	4	0	0
T31	0	2	0	0
T32	0	6	0	0
T44	0	1	0	0
T56	0	1	0	0
T111	0	7	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	15990	0	0
T1	521	0	0	0
T2	30724	549	0	0
T3	771	0	0	0
T4	19423	84	0	0
T5	402	0	0	0
T6	1089	0	0	0
T9	0	4	0	0
T10	0	55	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T30	0	324	0	0
T31	0	21	0	0
T32	0	333	0	0
T44	0	53	0	0
T56	0	2	0	0
T111	0	404	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8015761	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	324	0	0
T2	30724	12	0	0
T3	771	0	0	0
T6	1089	0	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	0	1	0	0
T10	0	2	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	496	0	0	0
T30	0	4	0	0
T31	0	2	0	0
T44	0	1	0	0
T47	0	2	0	0
T56	0	1	0	0
T111	0	7	0	0
T112	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T17,T26
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T17,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T17,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T17,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T17,T26
1	0	Covered	T4,T44,T32
1	1	Covered	T4,T17,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T17,T26
0	1	Covered	T17,T26,T71
1	0	Covered	T45,T79,T92

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T44,T32
0	1	Covered	T4,T44,T32
1	0	Covered	T248

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T44,T32
1	-	Covered	T4,T44,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T17,T26
DetectSt	168	Covered	T4,T17,T26
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T4,T44,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T17,T26
DebounceSt->IdleSt	163	Covered	T244,T232,T150
DetectSt->IdleSt	186	Covered	T17,T26,T71
DetectSt->StableSt	191	Covered	T4,T44,T32
IdleSt->DebounceSt	148	Covered	T4,T17,T26
StableSt->IdleSt	206	Covered	T4,T44,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T17,T26
0	1	Covered	T4,T17,T26
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T17,T26
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T4,T17,T26
IdleSt	0	-	-	-	-	-	-	Covered	T4,T17,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T17,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T244,T232,T150
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T17,T26
DetectSt	-	-	-	-	1	-	-	Covered	T17,T26,T71
DetectSt	-	-	-	-	0	1	-	Covered	T4,T44,T32
DetectSt	-	-	-	-	0	0	-	Covered	T4,T17,T26
StableSt	-	-	-	-	-	-	1	Covered	T4,T44,T32
StableSt	-	-	-	-	-	-	0	Covered	T4,T44,T32
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8695005	2910	0	0
CntIncr_A	8695005	105241	0	0
CntNoWrap_A	8695005	8010413	0	0
DetectStDropOut_A	8695005	450	0	0
DetectedOut_A	8695005	60672	0	0
DetectedPulseOut_A	8695005	757	0	0
DisabledIdleSt_A	8695005	7569988	0	0
DisabledNoDetection_A	8695005	7572231	0	0
EnterDebounceSt_A	8695005	1485	0	0
EnterDetectSt_A	8695005	1426	0	0
EnterStableSt_A	8695005	757	0	0
PulseIsPulse_A	8695005	757	0	0
StayInStableSt	8695005	59813	0	0
gen_high_event_sva.HighLevelEvent_A	8695005	8015761	0	0
gen_high_level_sva.HighLevelEvent_A	8695005	8015761	0	0
gen_not_sticky_sva.StableStDropOut_A	8695005	636	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	2910	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	22	0	0
T5	402	0	0	0
T6	1089	0	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	0	24	0	0
T26	0	2	0	0
T32	0	24	0	0
T33	0	48	0	0
T34	0	22	0	0
T44	0	8	0	0
T45	0	6	0	0
T71	0	14	0	0
T72	0	50	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	105241	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	385	0	0
T5	402	0	0	0
T6	1089	0	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	0	652	0	0
T26	0	61	0	0
T32	0	828	0	0
T33	0	720	0	0
T34	0	572	0	0
T44	0	316	0	0
T45	0	195	0	0
T71	0	414	0	0
T72	0	1101	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8010413	0	0
T1	521	120	0	0
T2	30724	29434	0	0
T3	771	370	0	0
T4	19423	18967	0	0
T5	402	1	0	0
T6	1089	688	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	450	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	0	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T17	5366	12	0	0
T22	496	0	0	0
T23	2248	0	0	0
T26	5716	1	0	0
T53	422	0	0	0
T71	0	7	0	0
T72	0	25	0	0
T79	0	8	0	0
T90	0	10	0	0
T91	0	16	0	0
T92	0	5	0	0
T93	0	28	0	0
T243	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	60672	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	477	0	0
T5	402	0	0	0
T6	1089	0	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T32	0	780	0	0
T33	0	1511	0	0
T34	0	672	0	0
T44	0	106	0	0
T137	0	2474	0	0
T192	0	1455	0	0
T194	0	882	0	0
T245	0	3025	0	0
T247	0	1069	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	757	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	11	0	0
T5	402	0	0	0
T6	1089	0	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T32	0	12	0	0
T33	0	24	0	0
T34	0	11	0	0
T44	0	4	0	0
T137	0	27	0	0
T192	0	13	0	0
T194	0	8	0	0
T245	0	26	0	0
T247	0	12	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	7569988	0	0
T1	521	120	0	0
T2	30724	29434	0	0
T3	771	370	0	0
T4	19423	15711	0	0
T5	402	1	0	0
T6	1089	688	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	7572231	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	15715	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	1485	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	11	0	0
T5	402	0	0	0
T6	1089	0	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	0	12	0	0
T26	0	1	0	0
T32	0	12	0	0
T33	0	24	0	0
T34	0	11	0	0
T44	0	4	0	0
T45	0	3	0	0
T71	0	7	0	0
T72	0	25	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	1426	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	11	0	0
T5	402	0	0	0
T6	1089	0	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	0	12	0	0
T26	0	1	0	0
T32	0	12	0	0
T33	0	24	0	0
T34	0	11	0	0
T44	0	4	0	0
T45	0	3	0	0
T71	0	7	0	0
T72	0	25	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	757	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	11	0	0
T5	402	0	0	0
T6	1089	0	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T32	0	12	0	0
T33	0	24	0	0
T34	0	11	0	0
T44	0	4	0	0
T137	0	27	0	0
T192	0	13	0	0
T194	0	8	0	0
T245	0	26	0	0
T247	0	12	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	757	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	11	0	0
T5	402	0	0	0
T6	1089	0	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T32	0	12	0	0
T33	0	24	0	0
T34	0	11	0	0
T44	0	4	0	0
T137	0	27	0	0
T192	0	13	0	0
T194	0	8	0	0
T245	0	26	0	0
T247	0	12	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	59813	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	464	0	0
T5	402	0	0	0
T6	1089	0	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T32	0	767	0	0
T33	0	1483	0	0
T34	0	660	0	0
T44	0	102	0	0
T137	0	2445	0	0
T192	0	1435	0	0
T194	0	873	0	0
T245	0	2993	0	0
T247	0	1055	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8015761	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8015761	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	636	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	9	0	0
T5	402	0	0	0
T6	1089	0	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T32	0	11	0	0
T33	0	20	0	0
T34	0	10	0	0
T44	0	4	0	0
T137	0	25	0	0
T192	0	6	0	0
T194	0	7	0	0
T245	0	20	0	0
T247	0	10	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T2,T17
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T17
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T2,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T4,T2,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T2,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T10
1	0	Covered	T4,T2,T15
1	1	Covered	T4,T2,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T2,T10
0	1	Covered	T31,T30,T89
1	0	Covered	T73,T74

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T2,T10
0	1	Covered	T2,T10,T11
1	0	Covered	T75,T73,T249

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T2,T10
1	-	Covered	T2,T10,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T2,T10
DetectSt	168	Covered	T4,T2,T10
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T4,T2,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T2,T10
DebounceSt->IdleSt	163	Covered	T10,T31,T111
DetectSt->IdleSt	186	Covered	T31,T30,T89
DetectSt->StableSt	191	Covered	T4,T2,T10
IdleSt->DebounceSt	148	Covered	T4,T2,T10
StableSt->IdleSt	206	Covered	T4,T2,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T2,T10
0	1	Covered	T4,T2,T10
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T2,T10
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T2,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T2,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T31,T111
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T2,T10
DetectSt	-	-	-	-	1	-	-	Covered	T31,T30,T89
DetectSt	-	-	-	-	0	1	-	Covered	T4,T2,T10
DetectSt	-	-	-	-	0	0	-	Covered	T4,T2,T10
StableSt	-	-	-	-	-	-	1	Covered	T2,T10,T11
StableSt	-	-	-	-	-	-	0	Covered	T4,T2,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8695005	860	0	0
CntIncr_A	8695005	48112	0	0
CntNoWrap_A	8695005	8012463	0	0
DetectStDropOut_A	8695005	66	0	0
DetectedOut_A	8695005	14186	0	0
DetectedPulseOut_A	8695005	339	0	0
DisabledIdleSt_A	8695005	7662547	0	0
DisabledNoDetection_A	8695005	7664358	0	0
EnterDebounceSt_A	8695005	454	0	0
EnterDetectSt_A	8695005	408	0	0
EnterStableSt_A	8695005	339	0	0
PulseIsPulse_A	8695005	339	0	0
StayInStableSt	8695005	13803	0	0
gen_high_level_sva.HighLevelEvent_A	8695005	8015761	0	0
gen_not_sticky_sva.StableStDropOut_A	8695005	290	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	860	0	0
T1	521	0	0	0
T2	30724	26	0	0
T3	771	0	0	0
T4	19423	4	0	0
T5	402	0	0	0
T6	1089	0	0	0
T10	0	11	0	0
T11	0	4	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T30	0	2	0	0
T31	0	9	0	0
T32	0	2	0	0
T33	0	6	0	0
T111	0	21	0	0
T250	0	15	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	48112	0	0
T1	521	0	0	0
T2	30724	1131	0	0
T3	771	0	0	0
T4	19423	84	0	0
T5	402	0	0	0
T6	1089	0	0	0
T10	0	670	0	0
T11	0	156	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T30	0	167	0	0
T31	0	1083	0	0
T32	0	57	0	0
T33	0	138	0	0
T111	0	1307	0	0
T250	0	2931	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8012463	0	0
T1	521	120	0	0
T2	30724	29408	0	0
T3	771	370	0	0
T4	19423	18985	0	0
T5	402	1	0	0
T6	1089	688	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	66	0	0
T30	7421	1	0	0
T31	19687	4	0	0
T32	32184	0	0	0
T37	876	0	0	0
T43	0	1	0	0
T44	13576	0	0	0
T60	1314	0	0	0
T64	523	0	0	0
T77	0	1	0	0
T89	0	12	0	0
T102	462	0	0	0
T103	416	0	0	0
T104	426	0	0	0
T107	0	1	0	0
T138	0	5	0	0
T179	0	3	0	0
T229	0	2	0	0
T251	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	14186	0	0
T1	521	0	0	0
T2	30724	134	0	0
T3	771	0	0	0
T4	19423	131	0	0
T5	402	0	0	0
T6	1089	0	0	0
T10	0	344	0	0
T11	0	8	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T32	0	72	0	0
T33	0	222	0	0
T34	0	65	0	0
T39	0	31	0	0
T111	0	50	0	0
T250	0	51	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	339	0	0
T1	521	0	0	0
T2	30724	13	0	0
T3	771	0	0	0
T4	19423	2	0	0
T5	402	0	0	0
T6	1089	0	0	0
T10	0	5	0	0
T11	0	2	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T32	0	1	0	0
T33	0	3	0	0
T34	0	1	0	0
T39	0	1	0	0
T111	0	10	0	0
T250	0	7	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	7662547	0	0
T1	521	120	0	0
T2	30724	26309	0	0
T3	771	370	0	0
T4	19423	18514	0	0
T5	402	1	0	0
T6	1089	688	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	7664358	0	0
T1	521	121	0	0
T2	30724	26310	0	0
T3	771	371	0	0
T4	19423	18519	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	454	0	0
T1	521	0	0	0
T2	30724	13	0	0
T3	771	0	0	0
T4	19423	2	0	0
T5	402	0	0	0
T6	1089	0	0	0
T10	0	6	0	0
T11	0	2	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T30	0	1	0	0
T31	0	5	0	0
T32	0	1	0	0
T33	0	3	0	0
T111	0	11	0	0
T250	0	8	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	408	0	0
T1	521	0	0	0
T2	30724	13	0	0
T3	771	0	0	0
T4	19423	2	0	0
T5	402	0	0	0
T6	1089	0	0	0
T10	0	5	0	0
T11	0	2	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T30	0	1	0	0
T31	0	4	0	0
T32	0	1	0	0
T33	0	3	0	0
T111	0	10	0	0
T250	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	339	0	0
T1	521	0	0	0
T2	30724	13	0	0
T3	771	0	0	0
T4	19423	2	0	0
T5	402	0	0	0
T6	1089	0	0	0
T10	0	5	0	0
T11	0	2	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T32	0	1	0	0
T33	0	3	0	0
T34	0	1	0	0
T39	0	1	0	0
T111	0	10	0	0
T250	0	7	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	339	0	0
T1	521	0	0	0
T2	30724	13	0	0
T3	771	0	0	0
T4	19423	2	0	0
T5	402	0	0	0
T6	1089	0	0	0
T10	0	5	0	0
T11	0	2	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T32	0	1	0	0
T33	0	3	0	0
T34	0	1	0	0
T39	0	1	0	0
T111	0	10	0	0
T250	0	7	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	13803	0	0
T1	521	0	0	0
T2	30724	121	0	0
T3	771	0	0	0
T4	19423	127	0	0
T5	402	0	0	0
T6	1089	0	0	0
T10	0	339	0	0
T11	0	6	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T32	0	70	0	0
T33	0	218	0	0
T34	0	64	0	0
T39	0	30	0	0
T111	0	40	0	0
T250	0	44	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8015761	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	290	0	0
T2	30724	13	0	0
T3	771	0	0	0
T6	1089	0	0	0
T7	498	0	0	0
T8	987	0	0	0
T10	0	5	0	0
T11	0	2	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	496	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T39	0	1	0	0
T111	0	10	0	0
T112	0	2	0	0
T161	0	6	0	0
T250	0	7	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T17,T26
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T17,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T17,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T17,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T17,T26
1	0	Covered	T4,T44,T32
1	1	Covered	T4,T17,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T17,T26
0	1	Covered	T17,T26,T71
1	0	Covered	T4,T92,T252

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T44,T32,T45
0	1	Covered	T44,T32,T45
1	0	Covered	T81,T73,T74

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T44,T32,T45
1	-	Covered	T44,T32,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T17,T26
DetectSt	168	Covered	T4,T17,T26
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T44,T32,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T17,T26
DebounceSt->IdleSt	163	Covered	T244,T232,T150
DetectSt->IdleSt	186	Covered	T4,T17,T26
DetectSt->StableSt	191	Covered	T44,T32,T45
IdleSt->DebounceSt	148	Covered	T4,T17,T26
StableSt->IdleSt	206	Covered	T44,T32,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T17,T26
0	1	Covered	T4,T17,T26
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T17,T26
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T4,T17,T26
IdleSt	0	-	-	-	-	-	-	Covered	T4,T17,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T17,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T244,T232,T150
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T17,T26
DetectSt	-	-	-	-	1	-	-	Covered	T4,T17,T26
DetectSt	-	-	-	-	0	1	-	Covered	T44,T32,T45
DetectSt	-	-	-	-	0	0	-	Covered	T4,T17,T26
StableSt	-	-	-	-	-	-	1	Covered	T44,T32,T45
StableSt	-	-	-	-	-	-	0	Covered	T44,T32,T45
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8695005	3214	0	0
CntIncr_A	8695005	114087	0	0
CntNoWrap_A	8695005	8010109	0	0
DetectStDropOut_A	8695005	547	0	0
DetectedOut_A	8695005	68593	0	0
DetectedPulseOut_A	8695005	825	0	0
DisabledIdleSt_A	8695005	7563569	0	0
DisabledNoDetection_A	8695005	7565805	0	0
EnterDebounceSt_A	8695005	1643	0	0
EnterDetectSt_A	8695005	1573	0	0
EnterStableSt_A	8695005	825	0	0
PulseIsPulse_A	8695005	825	0	0
StayInStableSt	8695005	67661	0	0
gen_high_event_sva.HighLevelEvent_A	8695005	8015761	0	0
gen_high_level_sva.HighLevelEvent_A	8695005	8015761	0	0
gen_not_sticky_sva.StableStDropOut_A	8695005	703	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	3214	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	22	0	0
T5	402	0	0	0
T6	1089	0	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	0	14	0	0
T26	0	38	0	0
T32	0	50	0	0
T33	0	56	0	0
T34	0	22	0	0
T44	0	24	0	0
T45	0	14	0	0
T71	0	28	0	0
T72	0	28	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	114087	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	623	0	0
T5	402	0	0	0
T6	1089	0	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	0	379	0	0
T26	0	1175	0	0
T32	0	1525	0	0
T33	0	784	0	0
T34	0	902	0	0
T44	0	948	0	0
T45	0	413	0	0
T71	0	835	0	0
T72	0	610	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8010109	0	0
T1	521	120	0	0
T2	30724	29434	0	0
T3	771	370	0	0
T4	19423	18967	0	0
T5	402	1	0	0
T6	1089	688	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	547	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	0	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T17	5366	7	0	0
T22	496	0	0	0
T23	2248	0	0	0
T26	5716	19	0	0
T53	422	0	0	0
T71	0	14	0	0
T72	0	14	0	0
T90	0	13	0	0
T91	0	18	0	0
T92	0	5	0	0
T93	0	25	0	0
T253	0	16	0	0
T254	0	10	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	68593	0	0
T25	699	0	0	0
T32	32184	2086	0	0
T33	23864	2681	0	0
T34	0	347	0	0
T37	876	0	0	0
T44	13576	585	0	0
T45	17205	1250	0	0
T65	526	0	0	0
T71	5620	0	0	0
T72	4816	0	0	0
T79	0	716	0	0
T189	6799	0	0	0
T192	0	2563	0	0
T194	0	1102	0	0
T245	0	1358	0	0
T247	0	2736	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	825	0	0
T25	699	0	0	0
T32	32184	25	0	0
T33	23864	28	0	0
T34	0	11	0	0
T37	876	0	0	0
T44	13576	12	0	0
T45	17205	7	0	0
T65	526	0	0	0
T71	5620	0	0	0
T72	4816	0	0	0
T79	0	11	0	0
T189	6799	0	0	0
T192	0	24	0	0
T194	0	21	0	0
T245	0	18	0	0
T247	0	27	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	7563569	0	0
T1	521	120	0	0
T2	30724	29434	0	0
T3	771	370	0	0
T4	19423	15966	0	0
T5	402	1	0	0
T6	1089	688	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	7565805	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	15972	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	1643	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	11	0	0
T5	402	0	0	0
T6	1089	0	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	0	7	0	0
T26	0	19	0	0
T32	0	25	0	0
T33	0	28	0	0
T34	0	11	0	0
T44	0	12	0	0
T45	0	7	0	0
T71	0	14	0	0
T72	0	14	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	1573	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	11	0	0
T5	402	0	0	0
T6	1089	0	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	0	7	0	0
T26	0	19	0	0
T32	0	25	0	0
T33	0	28	0	0
T34	0	11	0	0
T44	0	12	0	0
T45	0	7	0	0
T71	0	14	0	0
T72	0	14	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	825	0	0
T25	699	0	0	0
T32	32184	25	0	0
T33	23864	28	0	0
T34	0	11	0	0
T37	876	0	0	0
T44	13576	12	0	0
T45	17205	7	0	0
T65	526	0	0	0
T71	5620	0	0	0
T72	4816	0	0	0
T79	0	11	0	0
T189	6799	0	0	0
T192	0	24	0	0
T194	0	21	0	0
T245	0	18	0	0
T247	0	27	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	825	0	0
T25	699	0	0	0
T32	32184	25	0	0
T33	23864	28	0	0
T34	0	11	0	0
T37	876	0	0	0
T44	13576	12	0	0
T45	17205	7	0	0
T65	526	0	0	0
T71	5620	0	0	0
T72	4816	0	0	0
T79	0	11	0	0
T189	6799	0	0	0
T192	0	24	0	0
T194	0	21	0	0
T245	0	18	0	0
T247	0	27	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	67661	0	0
T25	699	0	0	0
T32	32184	2056	0	0
T33	23864	2647	0	0
T34	0	334	0	0
T37	876	0	0	0
T44	13576	572	0	0
T45	17205	1238	0	0
T65	526	0	0	0
T71	5620	0	0	0
T72	4816	0	0	0
T79	0	703	0	0
T189	6799	0	0	0
T192	0	2529	0	0
T194	0	1080	0	0
T245	0	1337	0	0
T247	0	2704	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8015761	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8015761	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	703	0	0
T25	699	0	0	0
T32	32184	20	0	0
T33	23864	22	0	0
T34	0	9	0	0
T37	876	0	0	0
T44	13576	11	0	0
T45	17205	2	0	0
T65	526	0	0	0
T71	5620	0	0	0
T72	4816	0	0	0
T79	0	9	0	0
T189	6799	0	0	0
T192	0	14	0	0
T194	0	20	0	0
T245	0	15	0	0
T247	0	22	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T17,T10
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T17,T10
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T10,T11,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T10,T11,T31

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T10,T11,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T31
1	0	Covered	T4,T2,T15
1	1	Covered	T10,T11,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T31
0	1	Covered	T251,T255,T97
1	0	Covered	T73,T74

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T31
0	1	Covered	T10,T11,T31
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T11,T31
1	-	Covered	T10,T11,T31

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T11,T31
DetectSt	168	Covered	T10,T11,T31
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T10,T11,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T11,T31
DebounceSt->IdleSt	163	Covered	T10,T30,T111
DetectSt->IdleSt	186	Covered	T251,T255,T97
DetectSt->StableSt	191	Covered	T10,T11,T31
IdleSt->DebounceSt	148	Covered	T10,T11,T31
StableSt->IdleSt	206	Covered	T10,T11,T31

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T11,T31
0	1	Covered	T10,T11,T31
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T31
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T11,T31
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T11,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T30,T111
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T11,T31
DetectSt	-	-	-	-	1	-	-	Covered	T251,T255,T97
DetectSt	-	-	-	-	0	1	-	Covered	T10,T11,T31
DetectSt	-	-	-	-	0	0	-	Covered	T10,T11,T31
StableSt	-	-	-	-	-	-	1	Covered	T10,T11,T31
StableSt	-	-	-	-	-	-	0	Covered	T10,T11,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8695005	829	0	0
CntIncr_A	8695005	49397	0	0
CntNoWrap_A	8695005	8012494	0	0
DetectStDropOut_A	8695005	34	0	0
DetectedOut_A	8695005	14665	0	0
DetectedPulseOut_A	8695005	356	0	0
DisabledIdleSt_A	8695005	7657331	0	0
DisabledNoDetection_A	8695005	7659126	0	0
EnterDebounceSt_A	8695005	436	0	0
EnterDetectSt_A	8695005	394	0	0
EnterStableSt_A	8695005	355	0	0
PulseIsPulse_A	8695005	355	0	0
StayInStableSt	8695005	14275	0	0
gen_high_level_sva.HighLevelEvent_A	8695005	8015761	0	0
gen_not_sticky_sva.StableStDropOut_A	8695005	318	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	829	0	0
T10	37403	5	0	0
T11	12776	6	0	0
T12	1470	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T30	7421	1	0	0
T31	19687	12	0	0
T32	0	8	0	0
T33	0	10	0	0
T44	0	2	0	0
T45	0	10	0	0
T53	422	0	0	0
T60	1314	0	0	0
T64	523	0	0	0
T111	0	21	0	0
T250	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	49397	0	0
T10	37403	417	0	0
T11	12776	228	0	0
T12	1470	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T30	7421	69	0	0
T31	19687	1248	0	0
T32	0	320	0	0
T33	0	350	0	0
T44	0	67	0	0
T45	0	325	0	0
T53	422	0	0	0
T60	1314	0	0	0
T64	523	0	0	0
T111	0	1307	0	0
T250	0	628	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8012494	0	0
T1	521	120	0	0
T2	30724	29434	0	0
T3	771	370	0	0
T4	19423	18989	0	0
T5	402	1	0	0
T6	1089	688	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	34	0	0
T97	0	4	0	0
T172	45010	0	0	0
T173	800	0	0	0
T244	8022	0	0	0
T251	10233	8	0	0
T253	13616	0	0	0
T254	5517	0	0	0
T255	0	6	0	0
T256	0	3	0	0
T257	0	5	0	0
T258	0	5	0	0
T259	0	1	0	0
T260	0	2	0	0
T261	26026	0	0	0
T262	524	0	0	0
T263	457	0	0	0
T264	25857	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	14665	0	0
T10	37403	43	0	0
T11	12776	18	0	0
T12	1470	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T30	7421	0	0	0
T31	19687	111	0	0
T32	0	197	0	0
T33	0	253	0	0
T44	0	64	0	0
T45	0	380	0	0
T53	422	0	0	0
T60	1314	0	0	0
T64	523	0	0	0
T89	0	67	0	0
T111	0	50	0	0
T250	0	48	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	356	0	0
T10	37403	2	0	0
T11	12776	3	0	0
T12	1470	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T30	7421	0	0	0
T31	19687	6	0	0
T32	0	4	0	0
T33	0	5	0	0
T44	0	1	0	0
T45	0	5	0	0
T53	422	0	0	0
T60	1314	0	0	0
T64	523	0	0	0
T89	0	7	0	0
T111	0	10	0	0
T250	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	7657331	0	0
T1	521	120	0	0
T2	30724	29434	0	0
T3	771	370	0	0
T4	19423	18989	0	0
T5	402	1	0	0
T6	1089	688	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	7659126	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	436	0	0
T10	37403	3	0	0
T11	12776	3	0	0
T12	1470	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T30	7421	1	0	0
T31	19687	6	0	0
T32	0	4	0	0
T33	0	5	0	0
T44	0	1	0	0
T45	0	5	0	0
T53	422	0	0	0
T60	1314	0	0	0
T64	523	0	0	0
T111	0	11	0	0
T250	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	394	0	0
T10	37403	2	0	0
T11	12776	3	0	0
T12	1470	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T30	7421	0	0	0
T31	19687	6	0	0
T32	0	4	0	0
T33	0	5	0	0
T44	0	1	0	0
T45	0	5	0	0
T53	422	0	0	0
T60	1314	0	0	0
T64	523	0	0	0
T89	0	7	0	0
T111	0	10	0	0
T250	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	355	0	0
T10	37403	2	0	0
T11	12776	3	0	0
T12	1470	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T30	7421	0	0	0
T31	19687	6	0	0
T32	0	4	0	0
T33	0	5	0	0
T44	0	1	0	0
T45	0	5	0	0
T53	422	0	0	0
T60	1314	0	0	0
T64	523	0	0	0
T89	0	7	0	0
T111	0	10	0	0
T250	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	355	0	0
T10	37403	2	0	0
T11	12776	3	0	0
T12	1470	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T30	7421	0	0	0
T31	19687	6	0	0
T32	0	4	0	0
T33	0	5	0	0
T44	0	1	0	0
T45	0	5	0	0
T53	422	0	0	0
T60	1314	0	0	0
T64	523	0	0	0
T89	0	7	0	0
T111	0	10	0	0
T250	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	14275	0	0
T10	37403	41	0	0
T11	12776	15	0	0
T12	1470	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T30	7421	0	0	0
T31	19687	105	0	0
T32	0	193	0	0
T33	0	248	0	0
T44	0	62	0	0
T45	0	375	0	0
T53	422	0	0	0
T60	1314	0	0	0
T64	523	0	0	0
T89	0	60	0	0
T111	0	40	0	0
T250	0	47	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8015761	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	318	0	0
T10	37403	2	0	0
T11	12776	3	0	0
T12	1470	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T30	7421	0	0	0
T31	19687	6	0	0
T32	0	4	0	0
T33	0	5	0	0
T34	0	1	0	0
T45	0	5	0	0
T53	422	0	0	0
T60	1314	0	0	0
T64	523	0	0	0
T89	0	7	0	0
T111	0	10	0	0
T250	0	1	0	0