Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T17,T26
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T17,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T17,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T17,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T17,T26
1	0	Covered	T4,T44,T32
1	1	Covered	T4,T17,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T17,T26
0	1	Covered	T17,T26,T71
1	0	Covered	T45,T79,T194

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T44,T32
0	1	Covered	T4,T44,T32
1	0	Covered	T80

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T44,T32
1	-	Covered	T4,T44,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T17,T26
DetectSt	168	Covered	T4,T17,T26
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T4,T44,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T17,T26
DebounceSt->IdleSt	163	Covered	T244,T232,T150
DetectSt->IdleSt	186	Covered	T17,T26,T71
DetectSt->StableSt	191	Covered	T4,T44,T32
IdleSt->DebounceSt	148	Covered	T4,T17,T26
StableSt->IdleSt	206	Covered	T4,T44,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T17,T26
0	1	Covered	T4,T17,T26
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T17,T26
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T4,T17,T26
IdleSt	0	-	-	-	-	-	-	Covered	T4,T17,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T17,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T244,T232,T150
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T17,T26
DetectSt	-	-	-	-	1	-	-	Covered	T17,T26,T71
DetectSt	-	-	-	-	0	1	-	Covered	T4,T44,T32
DetectSt	-	-	-	-	0	0	-	Covered	T4,T17,T26
StableSt	-	-	-	-	-	-	1	Covered	T4,T44,T32
StableSt	-	-	-	-	-	-	0	Covered	T4,T44,T32
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8695005	3261	0	0
CntIncr_A	8695005	127711	0	0
CntNoWrap_A	8695005	8010062	0	0
DetectStDropOut_A	8695005	574	0	0
DetectedOut_A	8695005	66305	0	0
DetectedPulseOut_A	8695005	742	0	0
DisabledIdleSt_A	8695005	7566684	0	0
DisabledNoDetection_A	8695005	7568942	0	0
EnterDebounceSt_A	8695005	1666	0	0
EnterDetectSt_A	8695005	1596	0	0
EnterStableSt_A	8695005	742	0	0
PulseIsPulse_A	8695005	742	0	0
StayInStableSt	8695005	65478	0	0
gen_high_event_sva.HighLevelEvent_A	8695005	8015761	0	0
gen_high_level_sva.HighLevelEvent_A	8695005	8015761	0	0
gen_not_sticky_sva.StableStDropOut_A	8695005	654	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	3261	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	52	0	0
T5	402	0	0	0
T6	1089	0	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	0	20	0	0
T26	0	46	0	0
T32	0	28	0	0
T33	0	18	0	0
T34	0	52	0	0
T44	0	46	0	0
T45	0	40	0	0
T71	0	72	0	0
T72	0	14	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	127711	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	754	0	0
T5	402	0	0	0
T6	1089	0	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	0	543	0	0
T26	0	1430	0	0
T32	0	1106	0	0
T33	0	351	0	0
T34	0	1508	0	0
T44	0	1978	0	0
T45	0	1304	0	0
T71	0	2155	0	0
T72	0	304	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8010062	0	0
T1	521	120	0	0
T2	30724	29434	0	0
T3	771	370	0	0
T4	19423	18937	0	0
T5	402	1	0	0
T6	1089	688	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	574	0	0
T7	498	0	0	0
T8	987	0	0	0
T9	160050	0	0	0
T10	37403	0	0	0
T11	12776	0	0	0
T17	5366	10	0	0
T22	496	0	0	0
T23	2248	0	0	0
T26	5716	23	0	0
T45	0	13	0	0
T53	422	0	0	0
T71	0	36	0	0
T72	0	7	0	0
T79	0	3	0	0
T90	0	7	0	0
T91	0	11	0	0
T93	0	14	0	0
T243	0	10	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	66305	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	2433	0	0
T5	402	0	0	0
T6	1089	0	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T32	0	414	0	0
T33	0	780	0	0
T34	0	2574	0	0
T44	0	1002	0	0
T92	0	1732	0	0
T137	0	1497	0	0
T192	0	929	0	0
T245	0	2024	0	0
T247	0	658	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	742	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	26	0	0
T5	402	0	0	0
T6	1089	0	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T32	0	14	0	0
T33	0	9	0	0
T34	0	26	0	0
T44	0	23	0	0
T92	0	12	0	0
T137	0	16	0	0
T192	0	9	0	0
T245	0	12	0	0
T247	0	12	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	7566684	0	0
T1	521	120	0	0
T2	30724	29434	0	0
T3	771	370	0	0
T4	19423	14229	0	0
T5	402	1	0	0
T6	1089	688	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	7568942	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	14230	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	1666	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	26	0	0
T5	402	0	0	0
T6	1089	0	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	0	10	0	0
T26	0	23	0	0
T32	0	14	0	0
T33	0	9	0	0
T34	0	26	0	0
T44	0	23	0	0
T45	0	20	0	0
T71	0	36	0	0
T72	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	1596	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	26	0	0
T5	402	0	0	0
T6	1089	0	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	0	10	0	0
T26	0	23	0	0
T32	0	14	0	0
T33	0	9	0	0
T34	0	26	0	0
T44	0	23	0	0
T45	0	20	0	0
T71	0	36	0	0
T72	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	742	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	26	0	0
T5	402	0	0	0
T6	1089	0	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T32	0	14	0	0
T33	0	9	0	0
T34	0	26	0	0
T44	0	23	0	0
T92	0	12	0	0
T137	0	16	0	0
T192	0	9	0	0
T245	0	12	0	0
T247	0	12	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	742	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	26	0	0
T5	402	0	0	0
T6	1089	0	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T32	0	14	0	0
T33	0	9	0	0
T34	0	26	0	0
T44	0	23	0	0
T92	0	12	0	0
T137	0	16	0	0
T192	0	9	0	0
T245	0	12	0	0
T247	0	12	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	65478	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	2402	0	0
T5	402	0	0	0
T6	1089	0	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T32	0	399	0	0
T33	0	769	0	0
T34	0	2544	0	0
T44	0	979	0	0
T92	0	1720	0	0
T137	0	1479	0	0
T192	0	918	0	0
T245	0	2007	0	0
T247	0	646	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8015761	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8015761	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	654	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	21	0	0
T5	402	0	0	0
T6	1089	0	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T32	0	13	0	0
T33	0	7	0	0
T34	0	22	0	0
T44	0	23	0	0
T92	0	12	0	0
T137	0	14	0	0
T192	0	7	0	0
T245	0	7	0	0
T247	0	12	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T2,T17
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T17
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T2,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T4,T2,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T2,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T10
1	0	Covered	T4,T2,T15
1	1	Covered	T4,T2,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T2,T10
0	1	Covered	T2,T31,T189
1	0	Covered	T73,T74

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T10,T11
0	1	Covered	T10,T11,T30
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T10,T11
1	-	Covered	T10,T11,T30

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T2,T10
DetectSt	168	Covered	T4,T2,T10
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T4,T10,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T2,T10
DebounceSt->IdleSt	163	Covered	T31,T30,T44
DetectSt->IdleSt	186	Covered	T2,T31,T189
DetectSt->StableSt	191	Covered	T4,T10,T11
IdleSt->DebounceSt	148	Covered	T4,T2,T10
StableSt->IdleSt	206	Covered	T4,T10,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T2,T10
0	1	Covered	T4,T2,T10
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T2,T10
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T2,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T2,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T31,T30,T44
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T2,T10
DetectSt	-	-	-	-	1	-	-	Covered	T2,T31,T189
DetectSt	-	-	-	-	0	1	-	Covered	T4,T10,T11
DetectSt	-	-	-	-	0	0	-	Covered	T4,T2,T10
StableSt	-	-	-	-	-	-	1	Covered	T10,T11,T30
StableSt	-	-	-	-	-	-	0	Covered	T4,T10,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8695005	891	0	0
CntIncr_A	8695005	54475	0	0
CntNoWrap_A	8695005	8012432	0	0
DetectStDropOut_A	8695005	67	0	0
DetectedOut_A	8695005	14961	0	0
DetectedPulseOut_A	8695005	351	0	0
DisabledIdleSt_A	8695005	7658818	0	0
DisabledNoDetection_A	8695005	7660635	0	0
EnterDebounceSt_A	8695005	469	0	0
EnterDetectSt_A	8695005	423	0	0
EnterStableSt_A	8695005	351	0	0
PulseIsPulse_A	8695005	351	0	0
StayInStableSt	8695005	14580	0	0
gen_high_level_sva.HighLevelEvent_A	8695005	8015761	0	0
gen_not_sticky_sva.StableStDropOut_A	8695005	319	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	891	0	0
T1	521	0	0	0
T2	30724	26	0	0
T3	771	0	0	0
T4	19423	4	0	0
T5	402	0	0	0
T6	1089	0	0	0
T10	0	26	0	0
T11	0	8	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T30	0	7	0	0
T31	0	9	0	0
T32	0	2	0	0
T33	0	4	0	0
T44	0	1	0	0
T189	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	54475	0	0
T1	521	0	0	0
T2	30724	1265	0	0
T3	771	0	0	0
T4	19423	114	0	0
T5	402	0	0	0
T6	1089	0	0	0
T10	0	1417	0	0
T11	0	312	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T30	0	525	0	0
T31	0	1084	0	0
T32	0	67	0	0
T33	0	100	0	0
T44	0	37	0	0
T189	0	653	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8012432	0	0
T1	521	120	0	0
T2	30724	29408	0	0
T3	771	370	0	0
T4	19423	18985	0	0
T5	402	1	0	0
T6	1089	688	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	67	0	0
T2	30724	13	0	0
T3	771	0	0	0
T6	1089	0	0	0
T7	498	0	0	0
T8	987	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T17	5366	0	0	0
T22	496	0	0	0
T31	0	4	0	0
T43	0	1	0	0
T89	0	3	0	0
T152	0	10	0	0
T179	0	2	0	0
T189	0	4	0	0
T255	0	2	0	0
T265	0	4	0	0
T266	0	12	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	14961	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	101	0	0
T5	402	0	0	0
T6	1089	0	0	0
T10	0	998	0	0
T11	0	17	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T30	0	47	0	0
T32	0	62	0	0
T33	0	144	0	0
T34	0	364	0	0
T161	0	122	0	0
T198	0	352	0	0
T250	0	520	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	351	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	2	0	0
T5	402	0	0	0
T6	1089	0	0	0
T10	0	13	0	0
T11	0	4	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T30	0	3	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	4	0	0
T161	0	3	0	0
T198	0	4	0	0
T250	0	7	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	7658818	0	0
T1	521	120	0	0
T2	30724	26309	0	0
T3	771	370	0	0
T4	19423	16561	0	0
T5	402	1	0	0
T6	1089	688	0	0
T13	446	45	0	0
T14	643	242	0	0
T15	2573	569	0	0
T16	595	194	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	7660635	0	0
T1	521	121	0	0
T2	30724	26310	0	0
T3	771	371	0	0
T4	19423	16563	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	469	0	0
T1	521	0	0	0
T2	30724	13	0	0
T3	771	0	0	0
T4	19423	2	0	0
T5	402	0	0	0
T6	1089	0	0	0
T10	0	13	0	0
T11	0	4	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T30	0	4	0	0
T31	0	5	0	0
T32	0	1	0	0
T33	0	2	0	0
T44	0	1	0	0
T189	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	423	0	0
T1	521	0	0	0
T2	30724	13	0	0
T3	771	0	0	0
T4	19423	2	0	0
T5	402	0	0	0
T6	1089	0	0	0
T10	0	13	0	0
T11	0	4	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T30	0	3	0	0
T31	0	4	0	0
T32	0	1	0	0
T33	0	2	0	0
T189	0	4	0	0
T250	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	351	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	2	0	0
T5	402	0	0	0
T6	1089	0	0	0
T10	0	13	0	0
T11	0	4	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T30	0	3	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	4	0	0
T161	0	3	0	0
T198	0	4	0	0
T250	0	7	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	351	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	2	0	0
T5	402	0	0	0
T6	1089	0	0	0
T10	0	13	0	0
T11	0	4	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T30	0	3	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	4	0	0
T161	0	3	0	0
T198	0	4	0	0
T250	0	7	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	14580	0	0
T1	521	0	0	0
T2	30724	0	0	0
T3	771	0	0	0
T4	19423	97	0	0
T5	402	0	0	0
T6	1089	0	0	0
T10	0	984	0	0
T11	0	13	0	0
T13	446	0	0	0
T14	643	0	0	0
T15	2573	0	0	0
T16	595	0	0	0
T30	0	44	0	0
T32	0	60	0	0
T33	0	142	0	0
T34	0	360	0	0
T161	0	119	0	0
T198	0	348	0	0
T250	0	513	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	8015761	0	0
T1	521	121	0	0
T2	30724	29448	0	0
T3	771	371	0	0
T4	19423	18996	0	0
T5	402	2	0	0
T6	1089	689	0	0
T13	446	46	0	0
T14	643	243	0	0
T15	2573	573	0	0
T16	595	195	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8695005	319	0	0
T10	37403	12	0	0
T11	12776	4	0	0
T12	1470	0	0	0
T24	522	0	0	0
T26	5716	0	0	0
T30	7421	3	0	0
T31	19687	0	0	0
T33	0	2	0	0
T34	0	4	0	0
T53	422	0	0	0
T60	1314	0	0	0
T64	523	0	0	0
T92	0	6	0	0
T112	0	10	0	0
T161	0	3	0	0
T198	0	4	0	0
T250	0	7	0	0