Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1434769474	10185	0	0
auto_block_debounce_ctl_rd_A	1434769474	1684	0	0
auto_block_out_ctl_rd_A	1434769474	2386	0	0
com_det_ctl_0_rd_A	1434769474	3761	0	0
com_det_ctl_1_rd_A	1434769474	3934	0	0
com_det_ctl_2_rd_A	1434769474	3788	0	0
com_det_ctl_3_rd_A	1434769474	4011	0	0
com_out_ctl_0_rd_A	1434769474	4332	0	0
com_out_ctl_1_rd_A	1434769474	4282	0	0
com_out_ctl_2_rd_A	1434769474	4454	0	0
com_out_ctl_3_rd_A	1434769474	4425	0	0
com_pre_det_ctl_0_rd_A	1434769474	1316	0	0
com_pre_det_ctl_1_rd_A	1434769474	1382	0	0
com_pre_det_ctl_2_rd_A	1434769474	1326	0	0
com_pre_det_ctl_3_rd_A	1434769474	1399	0	0
com_pre_sel_ctl_0_rd_A	1434769474	4452	0	0
com_pre_sel_ctl_1_rd_A	1434769474	4762	0	0
com_pre_sel_ctl_2_rd_A	1434769474	4507	0	0
com_pre_sel_ctl_3_rd_A	1434769474	4981	0	0
com_sel_ctl_0_rd_A	1434769474	4443	0	0
com_sel_ctl_1_rd_A	1434769474	4625	0	0
com_sel_ctl_2_rd_A	1434769474	4648	0	0
com_sel_ctl_3_rd_A	1434769474	4351	0	0
ec_rst_ctl_rd_A	1434769474	2742	0	0
intr_enable_rd_A	1434769474	1999	0	0
key_intr_ctl_rd_A	1434769474	3949	0	0
key_intr_debounce_ctl_rd_A	1434769474	1295	0	0
key_invert_ctl_rd_A	1434769474	5253	0	0
pin_allowed_ctl_rd_A	1434769474	5973	0	0
pin_out_ctl_rd_A	1434769474	4389	0	0
pin_out_value_rd_A	1434769474	4405	0	0
regwen_rd_A	1434769474	1499	0	0
ulp_ac_debounce_ctl_rd_A	1434769474	1500	0	0
ulp_ctl_rd_A	1434769474	1370	0	0
ulp_lid_debounce_ctl_rd_A	1434769474	1531	0	0
ulp_pwrb_debounce_ctl_rd_A	1434769474	1308	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434769474	10185	0	0
T9	303860	14	0	0
T10	187021	0	0	0
T11	159708	0	0	0
T12	58668	0	0	0
T23	112393	0	0	0
T24	261224	0	0	0
T26	285850	0	0	0
T31	984384	0	0	0
T39	0	6	0	0
T47	0	7	0	0
T49	0	12	0	0
T53	202709	0	0	0
T56	0	2	0	0
T59	0	4	0	0
T64	130659	0	0	0
T113	0	6	0	0
T114	0	16	0	0
T287	0	7	0	0
T288	0	16	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434769474	1684	0	0
T3	66942	0	0	0
T6	126816	0	0	0
T7	196101	0	0	0
T8	224027	0	0	0
T9	303860	0	0	0
T14	315146	11	0	0
T15	128689	0	0	0
T16	71438	0	0	0
T17	257581	0	0	0
T22	123905	0	0	0
T39	0	29	0	0
T47	0	16	0	0
T48	0	12	0	0
T83	0	5	0	0
T95	0	13	0	0
T140	0	2	0	0
T289	0	16	0	0
T290	0	3	0	0
T291	0	31	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434769474	2386	0	0
T3	66942	0	0	0
T6	126816	0	0	0
T7	196101	0	0	0
T8	224027	0	0	0
T9	303860	0	0	0
T14	315146	12	0	0
T15	128689	0	0	0
T16	71438	0	0	0
T17	257581	0	0	0
T22	123905	0	0	0
T39	0	31	0	0
T47	0	20	0	0
T48	0	7	0	0
T83	0	32	0	0
T95	0	20	0	0
T140	0	3	0	0
T289	0	8	0	0
T290	0	2	0	0
T291	0	31	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434769474	3761	0	0
T1	247554	0	0	0
T2	152086	57	0	0
T3	66942	0	0	0
T4	951755	49	0	0
T5	201314	0	0	0
T6	126816	0	0	0
T13	35762	0	0	0
T14	315146	0	0	0
T15	128689	0	0	0
T16	71438	0	0	0
T32	0	47	0	0
T39	0	29	0	0
T45	0	52	0	0
T47	0	13	0	0
T192	0	86	0	0
T247	0	78	0	0
T250	0	41	0	0
T292	0	47	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434769474	3934	0	0
T1	247554	0	0	0
T2	152086	66	0	0
T3	66942	0	0	0
T4	951755	16	0	0
T5	201314	0	0	0
T6	126816	0	0	0
T13	35762	0	0	0
T14	315146	0	0	0
T15	128689	0	0	0
T16	71438	0	0	0
T32	0	71	0	0
T39	0	46	0	0
T45	0	26	0	0
T47	0	18	0	0
T192	0	74	0	0
T247	0	78	0	0
T250	0	68	0	0
T292	0	38	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434769474	3788	0	0
T1	247554	0	0	0
T2	152086	99	0	0
T3	66942	0	0	0
T4	951755	35	0	0
T5	201314	0	0	0
T6	126816	0	0	0
T13	35762	0	0	0
T14	315146	0	0	0
T15	128689	0	0	0
T16	71438	0	0	0
T32	0	60	0	0
T39	0	49	0	0
T45	0	32	0	0
T47	0	14	0	0
T192	0	74	0	0
T247	0	51	0	0
T250	0	42	0	0
T292	0	51	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434769474	4011	0	0
T1	247554	0	0	0
T2	152086	75	0	0
T3	66942	0	0	0
T4	951755	18	0	0
T5	201314	0	0	0
T6	126816	0	0	0
T13	35762	0	0	0
T14	315146	0	0	0
T15	128689	0	0	0
T16	71438	0	0	0
T32	0	65	0	0
T39	0	44	0	0
T45	0	35	0	0
T47	0	27	0	0
T192	0	103	0	0
T247	0	73	0	0
T250	0	43	0	0
T292	0	16	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434769474	4332	0	0
T1	247554	0	0	0
T2	152086	74	0	0
T3	66942	0	0	0
T4	951755	22	0	0
T5	201314	0	0	0
T6	126816	0	0	0
T13	35762	0	0	0
T14	315146	0	0	0
T15	128689	0	0	0
T16	71438	0	0	0
T32	0	62	0	0
T39	0	39	0	0
T45	0	34	0	0
T47	0	21	0	0
T192	0	88	0	0
T247	0	61	0	0
T250	0	42	0	0
T292	0	37	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434769474	4282	0	0
T1	247554	0	0	0
T2	152086	68	0	0
T3	66942	0	0	0
T4	951755	15	0	0
T5	201314	0	0	0
T6	126816	0	0	0
T13	35762	0	0	0
T14	315146	0	0	0
T15	128689	0	0	0
T16	71438	0	0	0
T32	0	58	0	0
T39	0	55	0	0
T45	0	35	0	0
T47	0	32	0	0
T192	0	97	0	0
T247	0	58	0	0
T250	0	30	0	0
T292	0	48	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434769474	4454	0	0
T1	247554	0	0	0
T2	152086	79	0	0
T3	66942	0	0	0
T4	951755	38	0	0
T5	201314	0	0	0
T6	126816	0	0	0
T13	35762	0	0	0
T14	315146	0	0	0
T15	128689	0	0	0
T16	71438	0	0	0
T32	0	45	0	0
T39	0	45	0	0
T45	0	37	0	0
T47	0	22	0	0
T192	0	94	0	0
T247	0	92	0	0
T250	0	51	0	0
T292	0	38	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434769474	4425	0	0
T1	247554	0	0	0
T2	152086	88	0	0
T3	66942	0	0	0
T4	951755	38	0	0
T5	201314	0	0	0
T6	126816	0	0	0
T13	35762	0	0	0
T14	315146	0	0	0
T15	128689	0	0	0
T16	71438	0	0	0
T32	0	47	0	0
T39	0	18	0	0
T45	0	36	0	0
T47	0	11	0	0
T192	0	92	0	0
T247	0	72	0	0
T250	0	40	0	0
T292	0	27	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434769474	1316	0	0
T39	360632	29	0	0
T47	266743	25	0	0
T57	12545	0	0	0
T61	246679	0	0	0
T69	246336	0	0	0
T83	0	22	0	0
T95	0	15	0	0
T117	0	16	0	0
T120	0	15	0	0
T122	0	18	0	0
T158	53160	0	0	0
T159	52446	0	0	0
T160	464226	0	0	0
T161	215417	0	0	0
T162	169412	0	0	0
T214	0	4	0	0
T237	0	1	0	0
T291	0	27	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434769474	1382	0	0
T39	360632	24	0	0
T47	266743	9	0	0
T57	12545	0	0	0
T61	246679	0	0	0
T69	246336	0	0	0
T83	0	6	0	0
T95	0	16	0	0
T101	0	3	0	0
T117	0	32	0	0
T122	0	8	0	0
T158	53160	0	0	0
T159	52446	0	0	0
T160	464226	0	0	0
T161	215417	0	0	0
T162	169412	0	0	0
T214	0	8	0	0
T237	0	5	0	0
T291	0	38	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434769474	1326	0	0
T39	360632	36	0	0
T47	266743	18	0	0
T57	12545	0	0	0
T61	246679	0	0	0
T69	246336	0	0	0
T83	0	14	0	0
T95	0	15	0	0
T101	0	10	0	0
T117	0	32	0	0
T120	0	5	0	0
T122	0	13	0	0
T158	53160	0	0	0
T159	52446	0	0	0
T160	464226	0	0	0
T161	215417	0	0	0
T162	169412	0	0	0
T237	0	1	0	0
T291	0	25	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434769474	1399	0	0
T39	360632	33	0	0
T47	266743	30	0	0
T57	12545	0	0	0
T61	246679	0	0	0
T69	246336	0	0	0
T83	0	2	0	0
T95	0	14	0	0
T101	0	15	0	0
T117	0	25	0	0
T120	0	18	0	0
T122	0	28	0	0
T158	53160	0	0	0
T159	52446	0	0	0
T160	464226	0	0	0
T161	215417	0	0	0
T162	169412	0	0	0
T237	0	7	0	0
T291	0	36	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434769474	4452	0	0
T1	247554	0	0	0
T2	152086	59	0	0
T3	66942	0	0	0
T4	951755	45	0	0
T5	201314	0	0	0
T6	126816	0	0	0
T13	35762	0	0	0
T14	315146	0	0	0
T15	128689	0	0	0
T16	71438	0	0	0
T32	0	57	0	0
T39	0	45	0	0
T45	0	18	0	0
T47	0	12	0	0
T192	0	81	0	0
T247	0	60	0	0
T250	0	50	0	0
T292	0	43	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434769474	4762	0	0
T1	247554	0	0	0
T2	152086	61	0	0
T3	66942	0	0	0
T4	951755	47	0	0
T5	201314	0	0	0
T6	126816	0	0	0
T13	35762	0	0	0
T14	315146	0	0	0
T15	128689	0	0	0
T16	71438	0	0	0
T32	0	70	0	0
T39	0	32	0	0
T45	0	33	0	0
T47	0	21	0	0
T192	0	90	0	0
T247	0	86	0	0
T250	0	62	0	0
T292	0	37	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434769474	4507	0	0
T1	247554	0	0	0
T2	152086	89	0	0
T3	66942	0	0	0
T4	951755	58	0	0
T5	201314	0	0	0
T6	126816	0	0	0
T13	35762	0	0	0
T14	315146	0	0	0
T15	128689	0	0	0
T16	71438	0	0	0
T32	0	56	0	0
T39	0	32	0	0
T45	0	29	0	0
T47	0	11	0	0
T192	0	60	0	0
T247	0	62	0	0
T250	0	32	0	0
T292	0	44	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434769474	4981	0	0
T1	247554	0	0	0
T2	152086	71	0	0
T3	66942	0	0	0
T4	951755	34	0	0
T5	201314	0	0	0
T6	126816	0	0	0
T13	35762	0	0	0
T14	315146	0	0	0
T15	128689	0	0	0
T16	71438	0	0	0
T32	0	56	0	0
T39	0	50	0	0
T45	0	44	0	0
T47	0	23	0	0
T192	0	73	0	0
T247	0	62	0	0
T250	0	24	0	0
T292	0	28	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434769474	4443	0	0
T1	247554	0	0	0
T2	152086	68	0	0
T3	66942	0	0	0
T4	951755	22	0	0
T5	201314	0	0	0
T6	126816	0	0	0
T13	35762	0	0	0
T14	315146	0	0	0
T15	128689	0	0	0
T16	71438	0	0	0
T32	0	60	0	0
T39	0	46	0	0
T45	0	49	0	0
T47	0	20	0	0
T192	0	81	0	0
T247	0	73	0	0
T250	0	32	0	0
T292	0	64	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434769474	4625	0	0
T1	247554	0	0	0
T2	152086	76	0	0
T3	66942	0	0	0
T4	951755	34	0	0
T5	201314	0	0	0
T6	126816	0	0	0
T13	35762	0	0	0
T14	315146	0	0	0
T15	128689	0	0	0
T16	71438	0	0	0
T32	0	47	0	0
T39	0	45	0	0
T45	0	34	0	0
T47	0	20	0	0
T192	0	80	0	0
T247	0	90	0	0
T250	0	30	0	0
T292	0	51	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434769474	4648	0	0
T1	247554	0	0	0
T2	152086	71	0	0
T3	66942	0	0	0
T4	951755	21	0	0
T5	201314	0	0	0
T6	126816	0	0	0
T13	35762	0	0	0
T14	315146	0	0	0
T15	128689	0	0	0
T16	71438	0	0	0
T32	0	74	0	0
T39	0	45	0	0
T45	0	32	0	0
T47	0	24	0	0
T192	0	76	0	0
T247	0	55	0	0
T250	0	54	0	0
T292	0	52	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434769474	4351	0	0
T1	247554	0	0	0
T2	152086	60	0	0
T3	66942	0	0	0
T4	951755	29	0	0
T5	201314	0	0	0
T6	126816	0	0	0
T13	35762	0	0	0
T14	315146	0	0	0
T15	128689	0	0	0
T16	71438	0	0	0
T32	0	57	0	0
T39	0	30	0	0
T45	0	31	0	0
T47	0	21	0	0
T192	0	74	0	0
T247	0	76	0	0
T250	0	43	0	0
T292	0	41	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434769474	2742	0	0
T1	247554	0	0	0
T2	152086	32	0	0
T3	66942	0	0	0
T4	951755	27	0	0
T5	201314	0	0	0
T6	126816	0	0	0
T13	35762	0	0	0
T14	315146	0	0	0
T15	128689	8	0	0
T16	71438	2	0	0
T17	0	4	0	0
T32	0	25	0	0
T39	0	38	0	0
T45	0	30	0	0
T47	0	20	0	0
T250	0	16	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434769474	1999	0	0
T7	196101	0	0	0
T8	224027	0	0	0
T9	303860	0	0	0
T10	187021	0	0	0
T15	128689	42	0	0
T16	71438	0	0	0
T17	257581	0	0	0
T22	123905	0	0	0
T23	112393	0	0	0
T39	0	87	0	0
T47	0	20	0	0
T53	202709	0	0	0
T83	0	71	0	0
T95	0	10	0	0
T117	0	53	0	0
T152	0	9	0	0
T237	0	17	0	0
T291	0	50	0	0
T293	0	16	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434769474	3949	0	0
T1	247554	1	0	0
T2	152086	0	0	0
T3	66942	0	0	0
T6	126816	5	0	0
T7	196101	0	0	0
T13	35762	0	0	0
T14	315146	0	0	0
T15	128689	0	0	0
T16	71438	0	0	0
T17	257581	0	0	0
T39	0	32	0	0
T47	0	21	0	0
T83	0	10	0	0
T95	0	21	0	0
T146	0	1	0	0
T147	0	1	0	0
T164	0	1	0	0
T291	0	37	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434769474	1295	0	0
T39	360632	17	0	0
T47	266743	21	0	0
T57	12545	0	0	0
T61	246679	0	0	0
T69	246336	0	0	0
T83	0	11	0	0
T95	0	4	0	0
T101	0	1	0	0
T117	0	37	0	0
T120	0	3	0	0
T122	0	10	0	0
T158	53160	0	0	0
T159	52446	0	0	0
T160	464226	0	0	0
T161	215417	0	0	0
T162	169412	0	0	0
T237	0	4	0	0
T291	0	53	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434769474	5253	0	0
T7	196101	0	0	0
T8	224027	0	0	0
T9	303860	0	0	0
T10	187021	0	0	0
T15	128689	48	0	0
T16	71438	0	0	0
T17	257581	0	0	0
T22	123905	59	0	0
T23	112393	0	0	0
T39	0	101	0	0
T47	0	90	0	0
T53	202709	0	0	0
T63	0	63	0	0
T95	0	74	0	0
T251	0	66	0	0
T294	0	40	0	0
T295	0	21	0	0
T296	0	20	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434769474	5973	0	0
T39	360632	100	0	0
T46	79632	0	0	0
T47	0	31	0	0
T57	12545	0	0	0
T68	70919	54	0	0
T69	246336	80	0	0
T90	607149	0	0	0
T91	130005	0	0	0
T125	0	72	0	0
T158	53160	0	0	0
T159	52446	0	0	0
T191	0	40	0	0
T199	53127	0	0	0
T297	0	61	0	0
T298	0	82	0	0
T299	0	73	0	0
T300	0	64	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434769474	4389	0	0
T39	360632	89	0	0
T46	79632	0	0	0
T47	0	22	0	0
T57	12545	0	0	0
T68	70919	89	0	0
T69	246336	57	0	0
T90	607149	0	0	0
T91	130005	0	0	0
T125	0	76	0	0
T158	53160	0	0	0
T159	52446	0	0	0
T191	0	34	0	0
T199	53127	0	0	0
T297	0	89	0	0
T298	0	57	0	0
T299	0	75	0	0
T300	0	58	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434769474	4405	0	0
T39	360632	108	0	0
T46	79632	0	0	0
T47	0	21	0	0
T57	12545	0	0	0
T68	70919	70	0	0
T69	246336	67	0	0
T90	607149	0	0	0
T91	130005	0	0	0
T125	0	88	0	0
T158	53160	0	0	0
T159	52446	0	0	0
T191	0	43	0	0
T199	53127	0	0	0
T297	0	61	0	0
T298	0	77	0	0
T299	0	68	0	0
T300	0	78	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434769474	1499	0	0
T39	360632	38	0	0
T47	266743	26	0	0
T57	12545	0	0	0
T61	246679	0	0	0
T69	246336	0	0	0
T83	0	12	0	0
T95	0	20	0	0
T117	0	25	0	0
T120	0	1	0	0
T122	0	17	0	0
T158	53160	0	0	0
T159	52446	0	0	0
T160	464226	0	0	0
T161	215417	0	0	0
T162	169412	0	0	0
T214	0	3	0	0
T237	0	8	0	0
T291	0	40	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434769474	1500	0	0
T39	0	43	0	0
T40	42870	0	0	0
T46	79632	0	0	0
T47	0	28	0	0
T55	117285	5	0	0
T56	100699	0	0	0
T57	0	3	0	0
T67	241187	0	0	0
T68	70919	0	0	0
T83	0	25	0	0
T95	0	20	0	0
T117	0	45	0	0
T152	0	6	0	0
T196	55708	0	0	0
T197	164898	0	0	0
T198	195259	0	0	0
T199	53127	0	0	0
T237	0	7	0	0
T291	0	53	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434769474	1370	0	0
T39	0	19	0	0
T40	42870	0	0	0
T46	79632	0	0	0
T47	0	16	0	0
T55	117285	1	0	0
T56	100699	0	0	0
T57	0	13	0	0
T67	241187	0	0	0
T68	70919	0	0	0
T83	0	14	0	0
T95	0	13	0	0
T117	0	32	0	0
T152	0	2	0	0
T196	55708	0	0	0
T197	164898	0	0	0
T198	195259	0	0	0
T199	53127	0	0	0
T237	0	22	0	0
T291	0	46	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434769474	1531	0	0
T39	0	46	0	0
T40	42870	0	0	0
T46	79632	0	0	0
T47	0	19	0	0
T55	117285	5	0	0
T56	100699	0	0	0
T57	0	8	0	0
T67	241187	0	0	0
T68	70919	0	0	0
T83	0	18	0	0
T95	0	16	0	0
T117	0	34	0	0
T152	0	4	0	0
T196	55708	0	0	0
T197	164898	0	0	0
T198	195259	0	0	0
T199	53127	0	0	0
T206	0	3	0	0
T291	0	46	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1434769474	1308	0	0
T39	0	22	0	0
T40	42870	0	0	0
T46	79632	0	0	0
T47	0	17	0	0
T55	117285	3	0	0
T56	100699	0	0	0
T57	0	3	0	0
T67	241187	0	0	0
T68	70919	0	0	0
T83	0	9	0	0
T95	0	6	0	0
T117	0	25	0	0
T152	0	10	0	0
T196	55708	0	0	0
T197	164898	0	0	0
T198	195259	0	0	0
T199	53127	0	0	0
T237	0	2	0	0
T291	0	25	0	0