Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.35 99.33 96.41 100.00 96.79 98.78 99.52 90.64


Total test records in report: 912
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T28 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.1104548473 May 23 01:38:43 PM PDT 24 May 23 01:38:47 PM PDT 24 2068239585 ps
T29 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.785720851 May 23 01:38:39 PM PDT 24 May 23 01:39:08 PM PDT 24 43025189851 ps
T267 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.2887287327 May 23 01:38:38 PM PDT 24 May 23 01:38:42 PM PDT 24 2153442985 ps
T272 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.960981878 May 23 01:38:28 PM PDT 24 May 23 01:40:00 PM PDT 24 38343375652 ps
T798 /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.3644463362 May 23 01:39:07 PM PDT 24 May 23 01:39:11 PM PDT 24 2021997587 ps
T268 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.2873677315 May 23 01:38:42 PM PDT 24 May 23 01:38:48 PM PDT 24 2081891936 ps
T19 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.2651509869 May 23 01:38:39 PM PDT 24 May 23 01:38:58 PM PDT 24 4435800749 ps
T799 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.2523413839 May 23 01:38:25 PM PDT 24 May 23 01:38:32 PM PDT 24 2010740739 ps
T800 /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.1394872826 May 23 01:39:05 PM PDT 24 May 23 01:39:10 PM PDT 24 2035129218 ps
T21 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.986788733 May 23 01:38:49 PM PDT 24 May 23 01:38:56 PM PDT 24 2050347401 ps
T277 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.1961633403 May 23 01:38:49 PM PDT 24 May 23 01:38:53 PM PDT 24 2106134946 ps
T273 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.1693094719 May 23 01:38:47 PM PDT 24 May 23 01:38:51 PM PDT 24 2233438793 ps
T326 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.860582632 May 23 01:38:29 PM PDT 24 May 23 01:40:21 PM PDT 24 38827507596 ps
T283 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3994935278 May 23 01:38:42 PM PDT 24 May 23 01:38:50 PM PDT 24 2132446224 ps
T270 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.1281358965 May 23 01:38:57 PM PDT 24 May 23 01:39:13 PM PDT 24 42928394944 ps
T274 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.3707051931 May 23 01:38:42 PM PDT 24 May 23 01:38:46 PM PDT 24 2412393516 ps
T307 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.884374223 May 23 01:39:05 PM PDT 24 May 23 01:39:10 PM PDT 24 2052111841 ps
T322 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.2673870176 May 23 01:38:25 PM PDT 24 May 23 01:38:28 PM PDT 24 2075718975 ps
T801 /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.1225476490 May 23 01:39:06 PM PDT 24 May 23 01:39:09 PM PDT 24 2085352549 ps
T20 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.2601850912 May 23 01:38:40 PM PDT 24 May 23 01:38:59 PM PDT 24 7427112548 ps
T802 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.3605289185 May 23 01:38:39 PM PDT 24 May 23 01:38:42 PM PDT 24 2027961632 ps
T803 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3677084775 May 23 01:38:52 PM PDT 24 May 23 01:38:55 PM PDT 24 2046303631 ps
T327 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.1858006720 May 23 01:38:26 PM PDT 24 May 23 01:38:30 PM PDT 24 4042869778 ps
T278 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.2945084270 May 23 01:38:58 PM PDT 24 May 23 01:39:04 PM PDT 24 2230973949 ps
T804 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2216187097 May 23 01:38:26 PM PDT 24 May 23 01:38:33 PM PDT 24 3401696893 ps
T805 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1516314892 May 23 01:38:59 PM PDT 24 May 23 01:39:02 PM PDT 24 2037525729 ps
T806 /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.153778017 May 23 01:39:05 PM PDT 24 May 23 01:39:09 PM PDT 24 2029342134 ps
T807 /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.1797491328 May 23 01:39:08 PM PDT 24 May 23 01:39:14 PM PDT 24 2018767299 ps
T808 /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.534068737 May 23 01:39:02 PM PDT 24 May 23 01:39:08 PM PDT 24 2011089914 ps
T809 /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.916243518 May 23 01:39:03 PM PDT 24 May 23 01:39:11 PM PDT 24 2007630579 ps
T810 /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.913202317 May 23 01:39:04 PM PDT 24 May 23 01:39:11 PM PDT 24 2011080159 ps
T284 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.1505821051 May 23 01:38:48 PM PDT 24 May 23 01:38:56 PM PDT 24 2093630736 ps
T271 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.2920355086 May 23 01:38:37 PM PDT 24 May 23 01:39:32 PM PDT 24 22259350853 ps
T275 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.1010936748 May 23 01:38:55 PM PDT 24 May 23 01:39:03 PM PDT 24 2025866419 ps
T811 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.1232885082 May 23 01:38:49 PM PDT 24 May 23 01:38:57 PM PDT 24 2013433363 ps
T282 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.2103945620 May 23 01:38:42 PM PDT 24 May 23 01:38:49 PM PDT 24 2040121030 ps
T323 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.1426048343 May 23 01:38:29 PM PDT 24 May 23 01:38:57 PM PDT 24 9665209142 ps
T812 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.1102880946 May 23 01:38:57 PM PDT 24 May 23 01:39:01 PM PDT 24 2229161729 ps
T276 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.1763129761 May 23 01:38:38 PM PDT 24 May 23 01:38:42 PM PDT 24 3493377205 ps
T813 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.3584033882 May 23 01:38:56 PM PDT 24 May 23 01:39:03 PM PDT 24 2012245425 ps
T814 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.626051653 May 23 01:38:27 PM PDT 24 May 23 01:38:34 PM PDT 24 2010516001 ps
T815 /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.1380401773 May 23 01:39:06 PM PDT 24 May 23 01:39:14 PM PDT 24 2016273308 ps
T362 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.2456401747 May 23 01:38:58 PM PDT 24 May 23 01:39:32 PM PDT 24 22201770748 ps
T324 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.1562083919 May 23 01:38:40 PM PDT 24 May 23 01:38:47 PM PDT 24 2042942427 ps
T325 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.3779903271 May 23 01:38:51 PM PDT 24 May 23 01:39:08 PM PDT 24 9684832552 ps
T336 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.1546579331 May 23 01:38:55 PM PDT 24 May 23 01:39:52 PM PDT 24 22192634404 ps
T816 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1179895032 May 23 01:38:39 PM PDT 24 May 23 01:38:47 PM PDT 24 2070367255 ps
T308 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3378446329 May 23 01:38:55 PM PDT 24 May 23 01:38:59 PM PDT 24 2089997493 ps
T817 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.1343302783 May 23 01:38:40 PM PDT 24 May 23 01:38:44 PM PDT 24 2113275166 ps
T309 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.4061323354 May 23 01:38:28 PM PDT 24 May 23 01:38:32 PM PDT 24 4053586996 ps
T818 /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.1994846133 May 23 01:39:07 PM PDT 24 May 23 01:39:15 PM PDT 24 2017216861 ps
T310 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.404699300 May 23 01:38:38 PM PDT 24 May 23 01:38:44 PM PDT 24 2064133197 ps
T819 /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.197171159 May 23 01:39:06 PM PDT 24 May 23 01:39:11 PM PDT 24 2021408003 ps
T820 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.246224159 May 23 01:38:42 PM PDT 24 May 23 01:39:44 PM PDT 24 22235710224 ps
T821 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.1409430034 May 23 01:39:01 PM PDT 24 May 23 01:39:05 PM PDT 24 2147056729 ps
T822 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.393190929 May 23 01:39:01 PM PDT 24 May 23 01:39:03 PM PDT 24 2385926511 ps
T311 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.3394189652 May 23 01:38:40 PM PDT 24 May 23 01:38:43 PM PDT 24 2046796247 ps
T823 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.1247838573 May 23 01:38:39 PM PDT 24 May 23 01:39:39 PM PDT 24 22182926955 ps
T824 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.3984029328 May 23 01:38:49 PM PDT 24 May 23 01:39:11 PM PDT 24 9623849177 ps
T825 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.2074769730 May 23 01:38:28 PM PDT 24 May 23 01:38:33 PM PDT 24 2022400022 ps
T826 /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.878228220 May 23 01:39:06 PM PDT 24 May 23 01:39:14 PM PDT 24 2014886487 ps
T312 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.4162357306 May 23 01:38:27 PM PDT 24 May 23 01:39:17 PM PDT 24 41663500521 ps
T827 /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.1542187712 May 23 01:39:04 PM PDT 24 May 23 01:39:08 PM PDT 24 2039247912 ps
T828 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.3199740750 May 23 01:38:29 PM PDT 24 May 23 01:38:32 PM PDT 24 2044872139 ps
T337 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.1886116341 May 23 01:38:57 PM PDT 24 May 23 01:39:15 PM PDT 24 22487982317 ps
T280 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.4139512164 May 23 01:38:50 PM PDT 24 May 23 01:38:59 PM PDT 24 2113686009 ps
T829 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.2752879653 May 23 01:38:32 PM PDT 24 May 23 01:38:36 PM PDT 24 4045468462 ps
T830 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.255584486 May 23 01:38:28 PM PDT 24 May 23 01:40:34 PM PDT 24 42367116845 ps
T831 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.2605722709 May 23 01:38:56 PM PDT 24 May 23 01:39:00 PM PDT 24 2027032509 ps
T338 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.227885124 May 23 01:38:33 PM PDT 24 May 23 01:38:51 PM PDT 24 22267054583 ps
T281 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.2899028010 May 23 01:38:38 PM PDT 24 May 23 01:38:45 PM PDT 24 2053253661 ps
T313 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.2113461371 May 23 01:38:41 PM PDT 24 May 23 01:38:49 PM PDT 24 22058002020 ps
T832 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.1642942772 May 23 01:39:06 PM PDT 24 May 23 01:39:22 PM PDT 24 10004548599 ps
T833 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.1441124560 May 23 01:38:39 PM PDT 24 May 23 01:38:43 PM PDT 24 2726341686 ps
T834 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.4197304480 May 23 01:38:40 PM PDT 24 May 23 01:38:48 PM PDT 24 4783185183 ps
T314 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.774955904 May 23 01:38:51 PM PDT 24 May 23 01:38:58 PM PDT 24 2039149641 ps
T315 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2520699277 May 23 01:38:56 PM PDT 24 May 23 01:38:59 PM PDT 24 2109134571 ps
T835 /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.2721910792 May 23 01:39:08 PM PDT 24 May 23 01:39:12 PM PDT 24 2023765608 ps
T836 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.3670615641 May 23 01:38:49 PM PDT 24 May 23 01:38:53 PM PDT 24 2026710689 ps
T837 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.1620723813 May 23 01:38:59 PM PDT 24 May 23 01:39:35 PM PDT 24 9708843188 ps
T316 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.3293637766 May 23 01:38:29 PM PDT 24 May 23 01:38:34 PM PDT 24 2583177730 ps
T838 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.895902128 May 23 01:38:40 PM PDT 24 May 23 01:38:42 PM PDT 24 2069964550 ps
T839 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3069265867 May 23 01:38:26 PM PDT 24 May 23 01:38:37 PM PDT 24 4028618015 ps
T840 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2704227036 May 23 01:38:39 PM PDT 24 May 23 01:38:46 PM PDT 24 2013697491 ps
T841 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.4142922745 May 23 01:38:28 PM PDT 24 May 23 01:38:59 PM PDT 24 22227007445 ps
T842 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.2942108597 May 23 01:38:47 PM PDT 24 May 23 01:38:54 PM PDT 24 2012733098 ps
T843 /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.2812171208 May 23 01:39:06 PM PDT 24 May 23 01:39:14 PM PDT 24 2009516423 ps
T844 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.113967692 May 23 01:38:26 PM PDT 24 May 23 01:38:32 PM PDT 24 2148923821 ps
T317 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.3881753663 May 23 01:38:29 PM PDT 24 May 23 01:38:35 PM PDT 24 3413414555 ps
T845 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.3136564338 May 23 01:38:32 PM PDT 24 May 23 01:38:36 PM PDT 24 2064114955 ps
T846 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.1896452681 May 23 01:38:57 PM PDT 24 May 23 01:39:02 PM PDT 24 2148591566 ps
T847 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.3130596527 May 23 01:38:56 PM PDT 24 May 23 01:39:03 PM PDT 24 2052983133 ps
T848 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.2312070746 May 23 01:38:40 PM PDT 24 May 23 01:38:43 PM PDT 24 2499225998 ps
T849 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.1731566226 May 23 01:38:48 PM PDT 24 May 23 01:39:19 PM PDT 24 22297703662 ps
T850 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.3807380862 May 23 01:38:51 PM PDT 24 May 23 01:38:58 PM PDT 24 2011304679 ps
T851 /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.1327039144 May 23 01:39:04 PM PDT 24 May 23 01:39:11 PM PDT 24 2011290847 ps
T852 /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.23532545 May 23 01:39:05 PM PDT 24 May 23 01:39:13 PM PDT 24 2014379669 ps
T853 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.567935409 May 23 01:38:37 PM PDT 24 May 23 01:40:29 PM PDT 24 39823820453 ps
T854 /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.1979704530 May 23 01:39:06 PM PDT 24 May 23 01:39:11 PM PDT 24 2013101975 ps
T855 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2337699447 May 23 01:38:59 PM PDT 24 May 23 01:39:04 PM PDT 24 5424115809 ps
T856 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.131027264 May 23 01:38:26 PM PDT 24 May 23 01:38:30 PM PDT 24 2201348638 ps
T339 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.2499364680 May 23 01:38:42 PM PDT 24 May 23 01:39:29 PM PDT 24 22236094304 ps
T857 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.3281503856 May 23 01:39:01 PM PDT 24 May 23 01:39:06 PM PDT 24 2128421974 ps
T858 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.1557148202 May 23 01:38:26 PM PDT 24 May 23 01:38:35 PM PDT 24 2028395936 ps
T859 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.1776569620 May 23 01:38:50 PM PDT 24 May 23 01:39:01 PM PDT 24 4667827493 ps
T860 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.1763705581 May 23 01:38:32 PM PDT 24 May 23 01:38:35 PM PDT 24 2083831387 ps
T861 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1577678977 May 23 01:38:55 PM PDT 24 May 23 01:39:00 PM PDT 24 2153936068 ps
T862 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.317227671 May 23 01:38:47 PM PDT 24 May 23 01:38:51 PM PDT 24 2103277659 ps
T863 /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.926370961 May 23 01:39:06 PM PDT 24 May 23 01:39:14 PM PDT 24 2013654349 ps
T864 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1111543386 May 23 01:38:25 PM PDT 24 May 23 01:38:30 PM PDT 24 2103924249 ps
T865 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.3205476340 May 23 01:38:40 PM PDT 24 May 23 01:38:43 PM PDT 24 2267913301 ps
T866 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.2285924072 May 23 01:38:58 PM PDT 24 May 23 01:39:05 PM PDT 24 2043101943 ps
T318 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.3694094578 May 23 01:38:38 PM PDT 24 May 23 01:38:41 PM PDT 24 2399315561 ps
T867 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3885432903 May 23 01:38:57 PM PDT 24 May 23 01:39:36 PM PDT 24 42682025613 ps
T868 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2163977584 May 23 01:38:27 PM PDT 24 May 23 01:38:32 PM PDT 24 2342211685 ps
T869 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.2343540539 May 23 01:38:39 PM PDT 24 May 23 01:38:44 PM PDT 24 5509968210 ps
T870 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.404596573 May 23 01:38:38 PM PDT 24 May 23 01:38:59 PM PDT 24 5657213514 ps
T871 /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.2353874035 May 23 01:39:05 PM PDT 24 May 23 01:39:12 PM PDT 24 2011722734 ps
T872 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.3289401364 May 23 01:38:59 PM PDT 24 May 23 01:39:02 PM PDT 24 2037558174 ps
T873 /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.3951370463 May 23 01:39:02 PM PDT 24 May 23 01:39:04 PM PDT 24 2130871829 ps
T874 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.4098806736 May 23 01:38:50 PM PDT 24 May 23 01:39:02 PM PDT 24 22678727290 ps
T319 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.3276277156 May 23 01:38:39 PM PDT 24 May 23 01:38:42 PM PDT 24 2085152497 ps
T875 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2829131636 May 23 01:38:52 PM PDT 24 May 23 01:38:57 PM PDT 24 2048604874 ps
T876 /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.1336881558 May 23 01:39:06 PM PDT 24 May 23 01:39:10 PM PDT 24 2062477875 ps
T877 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.907050254 May 23 01:38:58 PM PDT 24 May 23 01:39:04 PM PDT 24 2033228237 ps
T878 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.1234652270 May 23 01:39:05 PM PDT 24 May 23 01:39:10 PM PDT 24 2026125401 ps
T879 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.371191361 May 23 01:38:48 PM PDT 24 May 23 01:38:55 PM PDT 24 2077743129 ps
T880 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.4029997453 May 23 01:38:54 PM PDT 24 May 23 01:40:45 PM PDT 24 42385762841 ps
T881 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2089042580 May 23 01:39:05 PM PDT 24 May 23 01:40:06 PM PDT 24 22187205276 ps
T882 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.3308535910 May 23 01:38:38 PM PDT 24 May 23 01:38:46 PM PDT 24 2183445852 ps
T883 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.222793707 May 23 01:38:56 PM PDT 24 May 23 01:39:19 PM PDT 24 5212272846 ps
T884 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.1435433086 May 23 01:38:59 PM PDT 24 May 23 01:39:03 PM PDT 24 2371136881 ps
T885 /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.3713027977 May 23 01:39:05 PM PDT 24 May 23 01:39:09 PM PDT 24 2038849275 ps
T886 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.3887410105 May 23 01:38:37 PM PDT 24 May 23 01:38:43 PM PDT 24 2211086753 ps
T887 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.1307038361 May 23 01:38:26 PM PDT 24 May 23 01:38:49 PM PDT 24 4865635714 ps
T888 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.1195572972 May 23 01:38:58 PM PDT 24 May 23 01:39:17 PM PDT 24 4499687082 ps
T889 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.2503519537 May 23 01:38:38 PM PDT 24 May 23 01:38:52 PM PDT 24 7457783523 ps
T890 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.4131873401 May 23 01:38:38 PM PDT 24 May 23 01:38:40 PM PDT 24 2118906045 ps
T891 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.642206787 May 23 01:38:40 PM PDT 24 May 23 01:39:11 PM PDT 24 6645545264 ps
T320 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.693297478 May 23 01:38:42 PM PDT 24 May 23 01:38:49 PM PDT 24 2045786908 ps
T892 /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.3237090682 May 23 01:39:02 PM PDT 24 May 23 01:39:04 PM PDT 24 2051611812 ps
T893 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.984252142 May 23 01:38:38 PM PDT 24 May 23 01:38:45 PM PDT 24 2050415209 ps
T894 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2927219914 May 23 01:38:28 PM PDT 24 May 23 01:38:31 PM PDT 24 2070647524 ps
T895 /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.2457515198 May 23 01:39:05 PM PDT 24 May 23 01:39:13 PM PDT 24 2014322442 ps
T896 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.413468809 May 23 01:38:43 PM PDT 24 May 23 01:39:04 PM PDT 24 43158076440 ps
T897 /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.2323113105 May 23 01:39:03 PM PDT 24 May 23 01:39:09 PM PDT 24 2013589079 ps
T321 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.707874681 May 23 01:38:29 PM PDT 24 May 23 01:38:37 PM PDT 24 2046249409 ps
T898 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1458408879 May 23 01:38:55 PM PDT 24 May 23 01:39:00 PM PDT 24 2136098298 ps
T899 /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.1201848343 May 23 01:39:08 PM PDT 24 May 23 01:39:17 PM PDT 24 2009410945 ps
T900 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.4059888154 May 23 01:38:40 PM PDT 24 May 23 01:38:47 PM PDT 24 2013189547 ps
T901 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.3536066687 May 23 01:39:03 PM PDT 24 May 23 01:39:10 PM PDT 24 2035421027 ps
T902 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.965950067 May 23 01:38:52 PM PDT 24 May 23 01:39:06 PM PDT 24 9548553060 ps
T903 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3295804498 May 23 01:39:03 PM PDT 24 May 23 01:39:06 PM PDT 24 2265718965 ps
T904 /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.2016824472 May 23 01:39:05 PM PDT 24 May 23 01:39:13 PM PDT 24 2012110612 ps
T905 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.445704826 May 23 01:38:44 PM PDT 24 May 23 01:38:50 PM PDT 24 2012149318 ps
T906 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.4073313873 May 23 01:38:53 PM PDT 24 May 23 01:38:57 PM PDT 24 2098022734 ps
T907 /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.2921614367 May 23 01:39:05 PM PDT 24 May 23 01:39:11 PM PDT 24 2019373274 ps
T908 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.2923094383 May 23 01:38:24 PM PDT 24 May 23 01:38:56 PM PDT 24 42953102239 ps
T909 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2080749175 May 23 01:38:59 PM PDT 24 May 23 01:39:06 PM PDT 24 4825240790 ps
T910 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.3389107930 May 23 01:38:49 PM PDT 24 May 23 01:39:05 PM PDT 24 42799845543 ps
T911 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3367059106 May 23 01:38:58 PM PDT 24 May 23 01:39:00 PM PDT 24 2252419720 ps
T912 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.2200944765 May 23 01:38:26 PM PDT 24 May 23 01:38:31 PM PDT 24 2215221517 ps

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.1854945468
Short name T4
Test name
Test status
Simulation time 97117142013 ps
CPU time 265.52 seconds
Started May 23 12:55:38 PM PDT 24
Finished May 23 01:00:05 PM PDT 24
Peak memory 202248 kb
Host smart-f79759eb-30ce-4624-a4ce-11e95d6a6d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854945468 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect_w
ith_pre_cond.1854945468
Directory /workspace/23.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.2506804792
Short name T9
Test name
Test status
Simulation time 800251448498 ps
CPU time 119.23 seconds
Started May 23 12:55:04 PM PDT 24
Finished May 23 12:57:05 PM PDT 24
Peak memory 210668 kb
Host smart-64e347c2-e0cc-4677-ad7e-fa747c6d1db3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506804792 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all_with_rand_reset.2506804792
Directory /workspace/15.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.355539263
Short name T39
Test name
Test status
Simulation time 77725653309 ps
CPU time 101 seconds
Started May 23 12:55:34 PM PDT 24
Finished May 23 12:57:16 PM PDT 24
Peak memory 218756 kb
Host smart-55973152-1fdf-412c-8cbd-242c7dda9ff5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355539263 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all_with_rand_reset.355539263
Directory /workspace/21.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.16588850
Short name T120
Test name
Test status
Simulation time 111211662280 ps
CPU time 85.52 seconds
Started May 23 12:57:18 PM PDT 24
Finished May 23 12:58:45 PM PDT 24
Peak memory 210696 kb
Host smart-3c97cc27-6c0f-4f75-b4b4-4231db180d4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16588850 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all_with_rand_reset.16588850
Directory /workspace/48.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_feature_disable.3319613352
Short name T73
Test name
Test status
Simulation time 27780756197 ps
CPU time 73.2 seconds
Started May 23 12:53:59 PM PDT 24
Finished May 23 12:55:14 PM PDT 24
Peak memory 201888 kb
Host smart-f7813d2a-7bfc-42c1-a57e-4c10284062fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319613352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.3319613352
Directory /workspace/1.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.2565823428
Short name T45
Test name
Test status
Simulation time 86026572213 ps
CPU time 55.8 seconds
Started May 23 12:57:20 PM PDT 24
Finished May 23 12:58:17 PM PDT 24
Peak memory 202284 kb
Host smart-14beb6d7-b5f4-4aae-8d0f-82d963eaf66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565823428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.sysrst_ctrl_combo_detect_w
ith_pre_cond.2565823428
Directory /workspace/98.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.2754132168
Short name T43
Test name
Test status
Simulation time 64915785629 ps
CPU time 78.97 seconds
Started May 23 12:57:10 PM PDT 24
Finished May 23 12:58:32 PM PDT 24
Peak memory 210696 kb
Host smart-63d02183-9f04-4d25-9c27-b87aacd314b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754132168 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all_with_rand_reset.2754132168
Directory /workspace/47.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.785720851
Short name T29
Test name
Test status
Simulation time 43025189851 ps
CPU time 28.69 seconds
Started May 23 01:38:39 PM PDT 24
Finished May 23 01:39:08 PM PDT 24
Peak memory 201964 kb
Host smart-de73ca55-b527-4c0a-bd19-4a42b832bcc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785720851 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ct
rl_tl_intg_err.785720851
Directory /workspace/5.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.4263203194
Short name T77
Test name
Test status
Simulation time 814468969711 ps
CPU time 151.71 seconds
Started May 23 12:55:51 PM PDT 24
Finished May 23 12:58:24 PM PDT 24
Peak memory 210700 kb
Host smart-b6d8249b-1c9a-487f-98fe-a3c8d8c1afad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263203194 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all_with_rand_reset.4263203194
Directory /workspace/25.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect.3730239097
Short name T10
Test name
Test status
Simulation time 187021351891 ps
CPU time 529.24 seconds
Started May 23 12:55:04 PM PDT 24
Finished May 23 01:03:56 PM PDT 24
Peak memory 202236 kb
Host smart-4d6b4e38-0a93-4b9e-863d-5018801754dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730239097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_c
trl_combo_detect.3730239097
Directory /workspace/14.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.2671092712
Short name T47
Test name
Test status
Simulation time 28376234627 ps
CPU time 72.81 seconds
Started May 23 12:56:44 PM PDT 24
Finished May 23 12:58:00 PM PDT 24
Peak memory 212868 kb
Host smart-19092c3c-d42d-407e-ae59-5c7059f6ef89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671092712 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all_with_rand_reset.2671092712
Directory /workspace/39.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.2584760893
Short name T117
Test name
Test status
Simulation time 103487180263 ps
CPU time 107.29 seconds
Started May 23 12:55:18 PM PDT 24
Finished May 23 12:57:07 PM PDT 24
Peak memory 210612 kb
Host smart-66f282c7-95c1-4285-830f-0a0a5d90e097
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584760893 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all_with_rand_reset.2584760893
Directory /workspace/19.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect.564321905
Short name T328
Test name
Test status
Simulation time 157722408240 ps
CPU time 111.99 seconds
Started May 23 12:55:36 PM PDT 24
Finished May 23 12:57:30 PM PDT 24
Peak memory 202272 kb
Host smart-8079e52f-5c42-4301-a333-6ef90a25e3b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564321905 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ct
rl_combo_detect.564321905
Directory /workspace/22.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_sec_cm.2882307510
Short name T109
Test name
Test status
Simulation time 42189738518 ps
CPU time 23.34 seconds
Started May 23 12:53:51 PM PDT 24
Finished May 23 12:54:16 PM PDT 24
Peak memory 222784 kb
Host smart-262ffc10-86bf-497d-b476-00a126622883
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882307510 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.2882307510
Directory /workspace/1.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_edge_detect.1341653202
Short name T157
Test name
Test status
Simulation time 3932455462 ps
CPU time 4.67 seconds
Started May 23 12:55:19 PM PDT 24
Finished May 23 12:55:26 PM PDT 24
Peak memory 202016 kb
Host smart-c3db546b-4951-4362-b348-babb18ca596b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341653202 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ct
rl_edge_detect.1341653202
Directory /workspace/18.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.3964438007
Short name T32
Test name
Test status
Simulation time 160924121581 ps
CPU time 101.2 seconds
Started May 23 12:56:43 PM PDT 24
Finished May 23 12:58:27 PM PDT 24
Peak memory 202356 kb
Host smart-3cad3c10-586a-4c96-aa04-2e5e01d9fd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964438007 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect_w
ith_pre_cond.3964438007
Directory /workspace/40.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.1869835100
Short name T42
Test name
Test status
Simulation time 622772270453 ps
CPU time 151.41 seconds
Started May 23 12:53:48 PM PDT 24
Finished May 23 12:56:21 PM PDT 24
Peak memory 210764 kb
Host smart-282ef674-2b2c-41ec-9a21-7a8d3315e99f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869835100 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_stress_all_with_rand_reset.1869835100
Directory /workspace/1.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.2461056295
Short name T83
Test name
Test status
Simulation time 253511969733 ps
CPU time 78.42 seconds
Started May 23 12:55:51 PM PDT 24
Finished May 23 12:57:11 PM PDT 24
Peak memory 210660 kb
Host smart-28521ede-3155-46de-94d3-9efcb0407e02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461056295 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all_with_rand_reset.2461056295
Directory /workspace/26.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.3707051931
Short name T274
Test name
Test status
Simulation time 2412393516 ps
CPU time 3.83 seconds
Started May 23 01:38:42 PM PDT 24
Finished May 23 01:38:46 PM PDT 24
Peak memory 201948 kb
Host smart-ff2dd303-0e00-4f51-8fc3-848304ad6392
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707051931 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_error
s.3707051931
Directory /workspace/8.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_edge_detect.355936601
Short name T145
Test name
Test status
Simulation time 4062377521 ps
CPU time 3.86 seconds
Started May 23 12:56:34 PM PDT 24
Finished May 23 12:56:40 PM PDT 24
Peak memory 202024 kb
Host smart-0f99053b-a0e7-4798-a101-6d707e200623
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355936601 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctr
l_edge_detect.355936601
Directory /workspace/38.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.986788733
Short name T21
Test name
Test status
Simulation time 2050347401 ps
CPU time 5.91 seconds
Started May 23 01:38:49 PM PDT 24
Finished May 23 01:38:56 PM PDT 24
Peak memory 201776 kb
Host smart-439c2e01-eeee-41a2-b147-6de4f43a2d45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986788733 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_r
w.986788733
Directory /workspace/12.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.2667656266
Short name T245
Test name
Test status
Simulation time 166738037571 ps
CPU time 217.51 seconds
Started May 23 12:54:26 PM PDT 24
Finished May 23 12:58:06 PM PDT 24
Peak memory 202196 kb
Host smart-429316a2-f3e3-435d-a707-7d9304823d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667656266 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect_wi
th_pre_cond.2667656266
Directory /workspace/7.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all.3531434746
Short name T172
Test name
Test status
Simulation time 225053006370 ps
CPU time 125.17 seconds
Started May 23 12:56:21 PM PDT 24
Finished May 23 12:58:27 PM PDT 24
Peak memory 202340 kb
Host smart-3e1cfb81-e0a8-4728-a490-b2faf60686e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531434746 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_s
tress_all.3531434746
Directory /workspace/33.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.235698064
Short name T192
Test name
Test status
Simulation time 144413006487 ps
CPU time 361.4 seconds
Started May 23 12:54:53 PM PDT 24
Finished May 23 01:00:56 PM PDT 24
Peak memory 202296 kb
Host smart-94d95f7f-b672-4ad5-968f-e32563367de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235698064 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect_wi
th_pre_cond.235698064
Directory /workspace/12.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect.212250028
Short name T198
Test name
Test status
Simulation time 81358987669 ps
CPU time 52.76 seconds
Started May 23 12:53:58 PM PDT 24
Finished May 23 12:54:53 PM PDT 24
Peak memory 202204 kb
Host smart-81f31519-4dfb-4a98-8521-75c2ac02a248
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212250028 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctr
l_combo_detect.212250028
Directory /workspace/3.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.1943697994
Short name T261
Test name
Test status
Simulation time 130132487660 ps
CPU time 34.03 seconds
Started May 23 12:53:48 PM PDT 24
Finished May 23 12:54:24 PM PDT 24
Peak memory 202284 kb
Host smart-3dd0717e-eca1-4900-8daf-113d2b691646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943697994 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_wi
th_pre_cond.1943697994
Directory /workspace/0.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.1113231068
Short name T13
Test name
Test status
Simulation time 2235206915 ps
CPU time 1.61 seconds
Started May 23 12:55:07 PM PDT 24
Finished May 23 12:55:12 PM PDT 24
Peak memory 202000 kb
Host smart-a8d135f8-744c-4aa0-b7c5-b81e794ac128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113231068 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.1113231068
Directory /workspace/15.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect.2539188314
Short name T96
Test name
Test status
Simulation time 106052557610 ps
CPU time 65.12 seconds
Started May 23 12:55:49 PM PDT 24
Finished May 23 12:56:55 PM PDT 24
Peak memory 202248 kb
Host smart-ecac45cf-eebd-4652-acfa-d5f6d34c5bd8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539188314 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_c
trl_combo_detect.2539188314
Directory /workspace/25.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_alert_test.3323807867
Short name T443
Test name
Test status
Simulation time 2022269373 ps
CPU time 3.07 seconds
Started May 23 12:55:08 PM PDT 24
Finished May 23 12:55:13 PM PDT 24
Peak memory 201936 kb
Host smart-b564911a-ad82-4665-bbbe-5589031f0134
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323807867 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_te
st.3323807867
Directory /workspace/15.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.2490102253
Short name T12
Test name
Test status
Simulation time 7353192472 ps
CPU time 2.13 seconds
Started May 23 12:55:09 PM PDT 24
Finished May 23 12:55:13 PM PDT 24
Peak memory 202004 kb
Host smart-e8fc3751-cf62-4593-a2bd-4fea0da69cf2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490102253 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ultra_low_pwr.2490102253
Directory /workspace/14.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.500911087
Short name T90
Test name
Test status
Simulation time 27598042878 ps
CPU time 17.97 seconds
Started May 23 12:53:58 PM PDT 24
Finished May 23 12:54:18 PM PDT 24
Peak memory 202236 kb
Host smart-decfd9db-7a96-4771-aeb9-97231b3d9d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500911087 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_wit
h_pre_cond.500911087
Directory /workspace/2.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect.1755658385
Short name T256
Test name
Test status
Simulation time 92160474730 ps
CPU time 128.39 seconds
Started May 23 12:55:18 PM PDT 24
Finished May 23 12:57:29 PM PDT 24
Peak memory 202340 kb
Host smart-604358ff-644d-4d67-93b8-219c93482ee1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755658385 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_combo_detect.1755658385
Directory /workspace/19.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.1625629889
Short name T178
Test name
Test status
Simulation time 2517659378 ps
CPU time 3.64 seconds
Started May 23 12:55:10 PM PDT 24
Finished May 23 12:55:15 PM PDT 24
Peak memory 202124 kb
Host smart-8ad09753-88c9-4675-9625-b2ce02274b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625629889 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.1625629889
Directory /workspace/15.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.3073092250
Short name T144
Test name
Test status
Simulation time 138440738858 ps
CPU time 60.58 seconds
Started May 23 12:56:42 PM PDT 24
Finished May 23 12:57:44 PM PDT 24
Peak memory 210752 kb
Host smart-4ce5ad2c-5b73-4ff1-be8d-ad1703fd26bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073092250 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all_with_rand_reset.3073092250
Directory /workspace/41.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_edge_detect.1975152392
Short name T168
Test name
Test status
Simulation time 1107793740601 ps
CPU time 45.21 seconds
Started May 23 12:54:53 PM PDT 24
Finished May 23 12:55:40 PM PDT 24
Peak memory 202120 kb
Host smart-477bd1cb-24a4-44ce-ac38-5a072f445335
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975152392 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ct
rl_edge_detect.1975152392
Directory /workspace/11.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.2527442765
Short name T344
Test name
Test status
Simulation time 146936556546 ps
CPU time 90.67 seconds
Started May 23 12:55:18 PM PDT 24
Finished May 23 12:56:50 PM PDT 24
Peak memory 202300 kb
Host smart-1f9aba32-51fe-4c58-8f6e-44ad438da96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527442765 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect_w
ith_pre_cond.2527442765
Directory /workspace/18.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.1763129761
Short name T276
Test name
Test status
Simulation time 3493377205 ps
CPU time 2.72 seconds
Started May 23 01:38:38 PM PDT 24
Finished May 23 01:38:42 PM PDT 24
Peak memory 210952 kb
Host smart-c1aad7a3-c20e-44dc-89ff-cbe7720cf22e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763129761 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_erro
rs.1763129761
Directory /workspace/11.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3378446329
Short name T308
Test name
Test status
Simulation time 2089997493 ps
CPU time 3.74 seconds
Started May 23 01:38:55 PM PDT 24
Finished May 23 01:38:59 PM PDT 24
Peak memory 201660 kb
Host smart-11afc9b4-d0e2-4a23-908f-82c10d4e92a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378446329 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_
rw.3378446329
Directory /workspace/17.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.2030516133
Short name T333
Test name
Test status
Simulation time 115519381472 ps
CPU time 157.66 seconds
Started May 23 12:53:52 PM PDT 24
Finished May 23 12:56:31 PM PDT 24
Peak memory 202308 kb
Host smart-fccf5a8c-1d85-414c-b050-075cfe1422f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030516133 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_wi
th_pre_cond.2030516133
Directory /workspace/1.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect.621660573
Short name T154
Test name
Test status
Simulation time 124298960406 ps
CPU time 327.96 seconds
Started May 23 12:55:18 PM PDT 24
Finished May 23 01:00:47 PM PDT 24
Peak memory 202168 kb
Host smart-00c1c159-d6a1-4e03-84d3-89534b7aeb21
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621660573 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ct
rl_combo_detect.621660573
Directory /workspace/17.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.4136379599
Short name T335
Test name
Test status
Simulation time 98267197327 ps
CPU time 122.16 seconds
Started May 23 12:56:30 PM PDT 24
Finished May 23 12:58:33 PM PDT 24
Peak memory 202240 kb
Host smart-6cea5030-62e0-4425-9518-e09b0ed20de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136379599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect_w
ith_pre_cond.4136379599
Directory /workspace/36.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect.1949260563
Short name T359
Test name
Test status
Simulation time 79229294040 ps
CPU time 57.76 seconds
Started May 23 12:54:52 PM PDT 24
Finished May 23 12:55:51 PM PDT 24
Peak memory 202272 kb
Host smart-63b9dcce-0c8d-4bed-adaa-dbf84a7d61ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949260563 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_c
trl_combo_detect.1949260563
Directory /workspace/12.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect.4213725824
Short name T126
Test name
Test status
Simulation time 131429380890 ps
CPU time 199.5 seconds
Started May 23 12:56:07 PM PDT 24
Finished May 23 12:59:27 PM PDT 24
Peak memory 202276 kb
Host smart-f0a0f10d-04d0-4664-b55f-ae227824b475
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213725824 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_c
trl_combo_detect.4213725824
Directory /workspace/29.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect.764030565
Short name T89
Test name
Test status
Simulation time 100838528192 ps
CPU time 273.33 seconds
Started May 23 12:56:33 PM PDT 24
Finished May 23 01:01:09 PM PDT 24
Peak memory 202332 kb
Host smart-b149a172-361f-4441-88b3-003d8565c96d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764030565 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ct
rl_combo_detect.764030565
Directory /workspace/36.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.3221948804
Short name T49
Test name
Test status
Simulation time 59395871872 ps
CPU time 162.57 seconds
Started May 23 12:54:28 PM PDT 24
Finished May 23 12:57:15 PM PDT 24
Peak memory 210612 kb
Host smart-462a0b74-51b2-4b45-8a03-e6e3f3cb97df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221948804 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all_with_rand_reset.3221948804
Directory /workspace/7.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.2744568861
Short name T334
Test name
Test status
Simulation time 83524922730 ps
CPU time 109.59 seconds
Started May 23 12:57:20 PM PDT 24
Finished May 23 12:59:10 PM PDT 24
Peak memory 202436 kb
Host smart-906725f8-44bf-4859-8d87-c569cfce1da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744568861 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.sysrst_ctrl_combo_detect_w
ith_pre_cond.2744568861
Directory /workspace/86.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.1920548621
Short name T76
Test name
Test status
Simulation time 99052564324 ps
CPU time 251.45 seconds
Started May 23 12:55:33 PM PDT 24
Finished May 23 12:59:45 PM PDT 24
Peak memory 202272 kb
Host smart-0c925492-d4ee-472a-b204-268b66153112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920548621 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect_w
ith_pre_cond.1920548621
Directory /workspace/21.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.3202299517
Short name T80
Test name
Test status
Simulation time 83841990977 ps
CPU time 42.77 seconds
Started May 23 12:57:22 PM PDT 24
Finished May 23 12:58:06 PM PDT 24
Peak memory 202340 kb
Host smart-5c53a0b6-2e15-401e-8fe6-e02e8280680d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202299517 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.sysrst_ctrl_combo_detect_w
ith_pre_cond.3202299517
Directory /workspace/94.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.4030005759
Short name T248
Test name
Test status
Simulation time 233499391849 ps
CPU time 295.83 seconds
Started May 23 12:57:22 PM PDT 24
Finished May 23 01:02:19 PM PDT 24
Peak memory 202316 kb
Host smart-eba43cb4-8046-4778-a5c3-78e95c56b3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030005759 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.sysrst_ctrl_combo_detect_w
ith_pre_cond.4030005759
Directory /workspace/96.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_edge_detect.749391702
Short name T78
Test name
Test status
Simulation time 3079959528 ps
CPU time 3.72 seconds
Started May 23 12:56:18 PM PDT 24
Finished May 23 12:56:23 PM PDT 24
Peak memory 202020 kb
Host smart-acd870f7-6218-4f3b-930a-11d468c13d24
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749391702 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctr
l_edge_detect.749391702
Directory /workspace/35.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.1426048343
Short name T323
Test name
Test status
Simulation time 9665209142 ps
CPU time 26.48 seconds
Started May 23 01:38:29 PM PDT 24
Finished May 23 01:38:57 PM PDT 24
Peak memory 201908 kb
Host smart-1bf47669-30b3-43b0-bd02-f19deb00e1d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426048343 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.sysrst_ctrl_same_csr_outstanding.1426048343
Directory /workspace/1.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.1886116341
Short name T337
Test name
Test status
Simulation time 22487982317 ps
CPU time 16.85 seconds
Started May 23 01:38:57 PM PDT 24
Finished May 23 01:39:15 PM PDT 24
Peak memory 201928 kb
Host smart-b5cca194-2e65-4554-97d4-fed4d4c0251c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886116341 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_tl_intg_err.1886116341
Directory /workspace/15.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.893905021
Short name T85
Test name
Test status
Simulation time 805610436347 ps
CPU time 88.7 seconds
Started May 23 12:54:54 PM PDT 24
Finished May 23 12:56:24 PM PDT 24
Peak memory 210620 kb
Host smart-03685881-1bb5-4a5f-898d-0011aad53c18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893905021 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all_with_rand_reset.893905021
Directory /workspace/11.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.2575476272
Short name T68
Test name
Test status
Simulation time 2532847582 ps
CPU time 2.74 seconds
Started May 23 12:54:51 PM PDT 24
Finished May 23 12:54:55 PM PDT 24
Peak memory 202036 kb
Host smart-8e03f468-3ccd-4d5c-a3b3-4155f2d5c2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575476272 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.2575476272
Directory /workspace/14.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.3362277588
Short name T133
Test name
Test status
Simulation time 48345281987 ps
CPU time 123.46 seconds
Started May 23 12:55:38 PM PDT 24
Finished May 23 12:57:43 PM PDT 24
Peak memory 210620 kb
Host smart-36a76308-e2d6-48dd-804d-05a571b35bdf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362277588 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all_with_rand_reset.3362277588
Directory /workspace/22.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect.3536789405
Short name T332
Test name
Test status
Simulation time 51442428402 ps
CPU time 139.64 seconds
Started May 23 12:55:50 PM PDT 24
Finished May 23 12:58:10 PM PDT 24
Peak memory 202208 kb
Host smart-32acd943-a67f-4fa2-b31b-271f482266e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536789405 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_c
trl_combo_detect.3536789405
Directory /workspace/27.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.3005138441
Short name T353
Test name
Test status
Simulation time 123198017090 ps
CPU time 316.73 seconds
Started May 23 12:56:17 PM PDT 24
Finished May 23 01:01:36 PM PDT 24
Peak memory 202296 kb
Host smart-6461a7ce-29fb-4710-aabb-faaa38349656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005138441 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect_w
ith_pre_cond.3005138441
Directory /workspace/34.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.4062504797
Short name T365
Test name
Test status
Simulation time 89095802135 ps
CPU time 58.72 seconds
Started May 23 12:56:33 PM PDT 24
Finished May 23 12:57:34 PM PDT 24
Peak memory 202376 kb
Host smart-5da998a3-a4d4-47f6-a602-b9bbe18dcc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062504797 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect_w
ith_pre_cond.4062504797
Directory /workspace/38.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.2732642190
Short name T351
Test name
Test status
Simulation time 120682595933 ps
CPU time 83.09 seconds
Started May 23 12:56:58 PM PDT 24
Finished May 23 12:58:23 PM PDT 24
Peak memory 202280 kb
Host smart-e9c6b1e9-582f-4e45-822f-cd493c2d683b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732642190 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect_w
ith_pre_cond.2732642190
Directory /workspace/43.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.2042585650
Short name T342
Test name
Test status
Simulation time 90927837683 ps
CPU time 233.08 seconds
Started May 23 12:56:58 PM PDT 24
Finished May 23 01:00:53 PM PDT 24
Peak memory 202312 kb
Host smart-0cc3eebf-7832-4fae-93ea-5df205069533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042585650 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect_w
ith_pre_cond.2042585650
Directory /workspace/45.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.3785945979
Short name T364
Test name
Test status
Simulation time 69254504232 ps
CPU time 25.87 seconds
Started May 23 12:57:08 PM PDT 24
Finished May 23 12:57:36 PM PDT 24
Peak memory 202204 kb
Host smart-172d90c0-686a-4775-8849-65c7ed8128f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785945979 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.sysrst_ctrl_combo_detect_w
ith_pre_cond.3785945979
Directory /workspace/55.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.3978713255
Short name T79
Test name
Test status
Simulation time 53263143533 ps
CPU time 69.33 seconds
Started May 23 12:57:09 PM PDT 24
Finished May 23 12:58:23 PM PDT 24
Peak memory 202312 kb
Host smart-df296cee-cdea-4de2-afa5-18c6ee60fb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978713255 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.sysrst_ctrl_combo_detect_w
ith_pre_cond.3978713255
Directory /workspace/64.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.89557050
Short name T350
Test name
Test status
Simulation time 56090843225 ps
CPU time 36.88 seconds
Started May 23 12:57:11 PM PDT 24
Finished May 23 12:57:51 PM PDT 24
Peak memory 202132 kb
Host smart-8b95f410-ac72-422f-b12c-303564755453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89557050 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.sysrst_ctrl_combo_detect_wit
h_pre_cond.89557050
Directory /workspace/74.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.1896452681
Short name T846
Test name
Test status
Simulation time 2148591566 ps
CPU time 4.42 seconds
Started May 23 01:38:57 PM PDT 24
Finished May 23 01:39:02 PM PDT 24
Peak memory 210196 kb
Host smart-b63b0079-2ada-4102-9e9d-add8ec695ffa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896452681 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_erro
rs.1896452681
Directory /workspace/12.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_feature_disable.2060771177
Short name T74
Test name
Test status
Simulation time 32353074922 ps
CPU time 43.24 seconds
Started May 23 12:53:47 PM PDT 24
Finished May 23 12:54:32 PM PDT 24
Peak memory 202084 kb
Host smart-ee1ad3bc-ab91-4431-b092-10b0e178855f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060771177 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.2060771177
Directory /workspace/0.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.2705305639
Short name T81
Test name
Test status
Simulation time 52418834007 ps
CPU time 134.9 seconds
Started May 23 12:57:16 PM PDT 24
Finished May 23 12:59:32 PM PDT 24
Peak memory 202240 kb
Host smart-bd90e5ea-dff8-4fc9-8e97-ce00330f7f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705305639 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.sysrst_ctrl_combo_detect_w
ith_pre_cond.2705305639
Directory /workspace/65.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2216187097
Short name T804
Test name
Test status
Simulation time 3401696893 ps
CPU time 5.05 seconds
Started May 23 01:38:26 PM PDT 24
Finished May 23 01:38:33 PM PDT 24
Peak memory 201852 kb
Host smart-6c510466-52cb-47ac-90e4-fb46e32f1ffe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216187097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_aliasing.2216187097
Directory /workspace/0.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.960981878
Short name T272
Test name
Test status
Simulation time 38343375652 ps
CPU time 91.29 seconds
Started May 23 01:38:28 PM PDT 24
Finished May 23 01:40:00 PM PDT 24
Peak memory 201956 kb
Host smart-d593e3e7-fef1-4639-a48f-a1ac1f9cd33b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960981878 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_
csr_bit_bash.960981878
Directory /workspace/0.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3069265867
Short name T839
Test name
Test status
Simulation time 4028618015 ps
CPU time 10.28 seconds
Started May 23 01:38:26 PM PDT 24
Finished May 23 01:38:37 PM PDT 24
Peak memory 201724 kb
Host smart-926155fc-d475-47a0-ab2c-025157303f8b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069265867 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_hw_reset.3069265867
Directory /workspace/0.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.113967692
Short name T844
Test name
Test status
Simulation time 2148923821 ps
CPU time 3.86 seconds
Started May 23 01:38:26 PM PDT 24
Finished May 23 01:38:32 PM PDT 24
Peak memory 201824 kb
Host smart-0082a34f-9aba-4759-9502-68292e1462c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113967692 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_mem_rw_with_rand_reset.113967692
Directory /workspace/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.2673870176
Short name T322
Test name
Test status
Simulation time 2075718975 ps
CPU time 1.81 seconds
Started May 23 01:38:25 PM PDT 24
Finished May 23 01:38:28 PM PDT 24
Peak memory 201760 kb
Host smart-c3d4d06b-e094-43bb-8980-b6022a82c867
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673870176 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_r
w.2673870176
Directory /workspace/0.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.626051653
Short name T814
Test name
Test status
Simulation time 2010516001 ps
CPU time 5.69 seconds
Started May 23 01:38:27 PM PDT 24
Finished May 23 01:38:34 PM PDT 24
Peak memory 201496 kb
Host smart-d735ec50-2440-49c7-9df1-ec3b6ab60d94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626051653 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_test
.626051653
Directory /workspace/0.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.1307038361
Short name T887
Test name
Test status
Simulation time 4865635714 ps
CPU time 20.7 seconds
Started May 23 01:38:26 PM PDT 24
Finished May 23 01:38:49 PM PDT 24
Peak memory 201860 kb
Host smart-b591f1c9-ed94-4130-9650-f87b8b376311
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307038361 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.sysrst_ctrl_same_csr_outstanding.1307038361
Directory /workspace/0.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.131027264
Short name T856
Test name
Test status
Simulation time 2201348638 ps
CPU time 3.18 seconds
Started May 23 01:38:26 PM PDT 24
Finished May 23 01:38:30 PM PDT 24
Peak memory 201996 kb
Host smart-41881b5f-24f8-44dd-a14f-b8426bae9474
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131027264 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_errors
.131027264
Directory /workspace/0.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.2923094383
Short name T908
Test name
Test status
Simulation time 42953102239 ps
CPU time 31.22 seconds
Started May 23 01:38:24 PM PDT 24
Finished May 23 01:38:56 PM PDT 24
Peak memory 202020 kb
Host smart-f174cccb-8a8d-4414-846f-929f6ae90516
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923094383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_tl_intg_err.2923094383
Directory /workspace/0.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.3881753663
Short name T317
Test name
Test status
Simulation time 3413414555 ps
CPU time 5.33 seconds
Started May 23 01:38:29 PM PDT 24
Finished May 23 01:38:35 PM PDT 24
Peak memory 201900 kb
Host smart-ab3e9a63-3afd-4c53-8a4b-bddbe790bfa8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881753663 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_aliasing.3881753663
Directory /workspace/1.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.4162357306
Short name T312
Test name
Test status
Simulation time 41663500521 ps
CPU time 48.68 seconds
Started May 23 01:38:27 PM PDT 24
Finished May 23 01:39:17 PM PDT 24
Peak memory 201944 kb
Host smart-fca68a40-7de7-4d86-b954-64a053c446b0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162357306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_bit_bash.4162357306
Directory /workspace/1.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.1858006720
Short name T327
Test name
Test status
Simulation time 4042869778 ps
CPU time 3.47 seconds
Started May 23 01:38:26 PM PDT 24
Finished May 23 01:38:30 PM PDT 24
Peak memory 201740 kb
Host smart-1670fe25-b1f6-4249-9ca5-387af840c4c1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858006720 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_hw_reset.1858006720
Directory /workspace/1.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1111543386
Short name T864
Test name
Test status
Simulation time 2103924249 ps
CPU time 3.69 seconds
Started May 23 01:38:25 PM PDT 24
Finished May 23 01:38:30 PM PDT 24
Peak memory 201740 kb
Host smart-c4c8dd53-ad4e-4a64-8729-28cd719bc1ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111543386 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1111543386
Directory /workspace/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2927219914
Short name T894
Test name
Test status
Simulation time 2070647524 ps
CPU time 1.99 seconds
Started May 23 01:38:28 PM PDT 24
Finished May 23 01:38:31 PM PDT 24
Peak memory 201676 kb
Host smart-d5433138-be79-447f-9b61-36d0bfb68058
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927219914 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_r
w.2927219914
Directory /workspace/1.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.2523413839
Short name T799
Test name
Test status
Simulation time 2010740739 ps
CPU time 5.72 seconds
Started May 23 01:38:25 PM PDT 24
Finished May 23 01:38:32 PM PDT 24
Peak memory 201276 kb
Host smart-9d720cd2-9e4c-4eb4-8e02-d36f4aa5be99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523413839 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_tes
t.2523413839
Directory /workspace/1.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.1557148202
Short name T858
Test name
Test status
Simulation time 2028395936 ps
CPU time 6.77 seconds
Started May 23 01:38:26 PM PDT 24
Finished May 23 01:38:35 PM PDT 24
Peak memory 201872 kb
Host smart-c1def997-7cfa-44c5-a1b8-733704feb875
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557148202 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_error
s.1557148202
Directory /workspace/1.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.4142922745
Short name T841
Test name
Test status
Simulation time 22227007445 ps
CPU time 29.57 seconds
Started May 23 01:38:28 PM PDT 24
Finished May 23 01:38:59 PM PDT 24
Peak memory 202028 kb
Host smart-6a2655ea-025f-4e97-be24-b9d583ea2046
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142922745 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_tl_intg_err.4142922745
Directory /workspace/1.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.1693094719
Short name T273
Test name
Test status
Simulation time 2233438793 ps
CPU time 2.46 seconds
Started May 23 01:38:47 PM PDT 24
Finished May 23 01:38:51 PM PDT 24
Peak memory 201892 kb
Host smart-7e2f39c6-dbad-444a-b9a4-a046352d7a1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693094719 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_mem_rw_with_rand_reset.1693094719
Directory /workspace/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.404699300
Short name T310
Test name
Test status
Simulation time 2064133197 ps
CPU time 5.04 seconds
Started May 23 01:38:38 PM PDT 24
Finished May 23 01:38:44 PM PDT 24
Peak memory 201716 kb
Host smart-9e4ab40a-091e-466b-8ed2-f032c07f12d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404699300 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_r
w.404699300
Directory /workspace/10.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2704227036
Short name T840
Test name
Test status
Simulation time 2013697491 ps
CPU time 6.18 seconds
Started May 23 01:38:39 PM PDT 24
Finished May 23 01:38:46 PM PDT 24
Peak memory 201516 kb
Host smart-19559d5d-0b8b-420d-b2c5-3871b5d1f06a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704227036 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_te
st.2704227036
Directory /workspace/10.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.642206787
Short name T891
Test name
Test status
Simulation time 6645545264 ps
CPU time 30.3 seconds
Started May 23 01:38:40 PM PDT 24
Finished May 23 01:39:11 PM PDT 24
Peak memory 201892 kb
Host smart-40f35e85-02d8-4527-ae38-6494cf1a038c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642206787 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.sysrst_ctrl_same_csr_outstanding.642206787
Directory /workspace/10.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.2312070746
Short name T848
Test name
Test status
Simulation time 2499225998 ps
CPU time 1.86 seconds
Started May 23 01:38:40 PM PDT 24
Finished May 23 01:38:43 PM PDT 24
Peak memory 202012 kb
Host smart-17ccc5af-aeee-4fd6-a57b-f1aeef42cf15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312070746 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_erro
rs.2312070746
Directory /workspace/10.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.2920355086
Short name T271
Test name
Test status
Simulation time 22259350853 ps
CPU time 54.48 seconds
Started May 23 01:38:37 PM PDT 24
Finished May 23 01:39:32 PM PDT 24
Peak memory 201996 kb
Host smart-5aa1c6b4-23ff-41e5-be93-66e97d6ee37c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920355086 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_tl_intg_err.2920355086
Directory /workspace/10.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3367059106
Short name T911
Test name
Test status
Simulation time 2252419720 ps
CPU time 1.56 seconds
Started May 23 01:38:58 PM PDT 24
Finished May 23 01:39:00 PM PDT 24
Peak memory 201812 kb
Host smart-4708d6a2-a895-42a0-91e0-08183f638059
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367059106 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3367059106
Directory /workspace/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.907050254
Short name T877
Test name
Test status
Simulation time 2033228237 ps
CPU time 5.7 seconds
Started May 23 01:38:58 PM PDT 24
Finished May 23 01:39:04 PM PDT 24
Peak memory 201788 kb
Host smart-8a90de26-badc-4ad7-8ae0-4d3a8e5f7f93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907050254 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_r
w.907050254
Directory /workspace/11.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.3670615641
Short name T836
Test name
Test status
Simulation time 2026710689 ps
CPU time 1.92 seconds
Started May 23 01:38:49 PM PDT 24
Finished May 23 01:38:53 PM PDT 24
Peak memory 201304 kb
Host smart-51b8a9c5-fb36-40d4-83eb-49ea33bc72e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670615641 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_te
st.3670615641
Directory /workspace/11.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.1620723813
Short name T837
Test name
Test status
Simulation time 9708843188 ps
CPU time 34.65 seconds
Started May 23 01:38:59 PM PDT 24
Finished May 23 01:39:35 PM PDT 24
Peak memory 201904 kb
Host smart-885a69e8-693f-4c2e-9e74-5bc9235b92d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620723813 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
1.sysrst_ctrl_same_csr_outstanding.1620723813
Directory /workspace/11.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3885432903
Short name T867
Test name
Test status
Simulation time 42682025613 ps
CPU time 38.74 seconds
Started May 23 01:38:57 PM PDT 24
Finished May 23 01:39:36 PM PDT 24
Peak memory 201948 kb
Host smart-8f15d99a-a54c-4cd3-9179-97f4ba258e71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885432903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_tl_intg_err.3885432903
Directory /workspace/11.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.1505821051
Short name T284
Test name
Test status
Simulation time 2093630736 ps
CPU time 6.56 seconds
Started May 23 01:38:48 PM PDT 24
Finished May 23 01:38:56 PM PDT 24
Peak memory 202000 kb
Host smart-3f971e43-83f4-4493-abec-6e99a41247bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505821051 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_mem_rw_with_rand_reset.1505821051
Directory /workspace/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.3807380862
Short name T850
Test name
Test status
Simulation time 2011304679 ps
CPU time 5.85 seconds
Started May 23 01:38:51 PM PDT 24
Finished May 23 01:38:58 PM PDT 24
Peak memory 201228 kb
Host smart-f166d905-b829-421e-aa4f-432ba34fac79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807380862 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_te
st.3807380862
Directory /workspace/12.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.3984029328
Short name T824
Test name
Test status
Simulation time 9623849177 ps
CPU time 20.75 seconds
Started May 23 01:38:49 PM PDT 24
Finished May 23 01:39:11 PM PDT 24
Peak memory 201996 kb
Host smart-d1d78e6e-fddb-42ed-b0c0-c5d17701af2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984029328 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
2.sysrst_ctrl_same_csr_outstanding.3984029328
Directory /workspace/12.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.3389107930
Short name T910
Test name
Test status
Simulation time 42799845543 ps
CPU time 13.89 seconds
Started May 23 01:38:49 PM PDT 24
Finished May 23 01:39:05 PM PDT 24
Peak memory 201964 kb
Host smart-3b9e33f1-0a72-4c55-8c2a-e80c84beeb2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389107930 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_tl_intg_err.3389107930
Directory /workspace/12.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1458408879
Short name T898
Test name
Test status
Simulation time 2136098298 ps
CPU time 3.8 seconds
Started May 23 01:38:55 PM PDT 24
Finished May 23 01:39:00 PM PDT 24
Peak memory 201756 kb
Host smart-cd225da2-5f6d-4544-9a51-9a9a2ded4f38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458408879 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1458408879
Directory /workspace/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2520699277
Short name T315
Test name
Test status
Simulation time 2109134571 ps
CPU time 1.88 seconds
Started May 23 01:38:56 PM PDT 24
Finished May 23 01:38:59 PM PDT 24
Peak memory 201760 kb
Host smart-2f9765cb-f933-4b5b-bcc7-e6c03b69c32c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520699277 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_
rw.2520699277
Directory /workspace/13.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3677084775
Short name T803
Test name
Test status
Simulation time 2046303631 ps
CPU time 1.68 seconds
Started May 23 01:38:52 PM PDT 24
Finished May 23 01:38:55 PM PDT 24
Peak memory 201568 kb
Host smart-6b428d1a-c19a-49c8-90a1-533dc7cc1c90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677084775 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_te
st.3677084775
Directory /workspace/13.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2337699447
Short name T855
Test name
Test status
Simulation time 5424115809 ps
CPU time 3.9 seconds
Started May 23 01:38:59 PM PDT 24
Finished May 23 01:39:04 PM PDT 24
Peak memory 202024 kb
Host smart-3fa41216-ed41-483f-a8e8-2c0e456cbe4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337699447 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
3.sysrst_ctrl_same_csr_outstanding.2337699447
Directory /workspace/13.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.3281503856
Short name T857
Test name
Test status
Simulation time 2128421974 ps
CPU time 3.87 seconds
Started May 23 01:39:01 PM PDT 24
Finished May 23 01:39:06 PM PDT 24
Peak memory 201928 kb
Host smart-42c8ab05-101c-4e82-873c-f32049414200
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281503856 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_erro
rs.3281503856
Directory /workspace/13.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.2456401747
Short name T362
Test name
Test status
Simulation time 22201770748 ps
CPU time 32.91 seconds
Started May 23 01:38:58 PM PDT 24
Finished May 23 01:39:32 PM PDT 24
Peak memory 201812 kb
Host smart-d402cdc2-aa2e-40a6-aa35-85c74085a37f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456401747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_tl_intg_err.2456401747
Directory /workspace/13.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1577678977
Short name T861
Test name
Test status
Simulation time 2153936068 ps
CPU time 3.72 seconds
Started May 23 01:38:55 PM PDT 24
Finished May 23 01:39:00 PM PDT 24
Peak memory 201916 kb
Host smart-b2ba45de-ba53-4b8d-8a5f-356428ffdd0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577678977 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1577678977
Directory /workspace/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.3130596527
Short name T847
Test name
Test status
Simulation time 2052983133 ps
CPU time 6.17 seconds
Started May 23 01:38:56 PM PDT 24
Finished May 23 01:39:03 PM PDT 24
Peak memory 201760 kb
Host smart-e7d65dab-00bc-43f7-924b-97f57ee5b2a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130596527 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_
rw.3130596527
Directory /workspace/14.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1516314892
Short name T805
Test name
Test status
Simulation time 2037525729 ps
CPU time 1.48 seconds
Started May 23 01:38:59 PM PDT 24
Finished May 23 01:39:02 PM PDT 24
Peak memory 201540 kb
Host smart-f67c9dab-efa7-4b8b-ac94-2a6b1a298d3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516314892 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_te
st.1516314892
Directory /workspace/14.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.222793707
Short name T883
Test name
Test status
Simulation time 5212272846 ps
CPU time 21.41 seconds
Started May 23 01:38:56 PM PDT 24
Finished May 23 01:39:19 PM PDT 24
Peak memory 201896 kb
Host smart-ce06bd53-5133-485f-933b-c6d867c7c888
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222793707 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.sysrst_ctrl_same_csr_outstanding.222793707
Directory /workspace/14.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.4139512164
Short name T280
Test name
Test status
Simulation time 2113686009 ps
CPU time 7.65 seconds
Started May 23 01:38:50 PM PDT 24
Finished May 23 01:38:59 PM PDT 24
Peak memory 201896 kb
Host smart-9aa78ed0-9cee-45a6-88b9-54520e465dfb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139512164 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_erro
rs.4139512164
Directory /workspace/14.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.4029997453
Short name T880
Test name
Test status
Simulation time 42385762841 ps
CPU time 110.29 seconds
Started May 23 01:38:54 PM PDT 24
Finished May 23 01:40:45 PM PDT 24
Peak memory 201960 kb
Host smart-7d873461-01cb-4cae-abd3-cde35a6f0e30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029997453 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_tl_intg_err.4029997453
Directory /workspace/14.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.393190929
Short name T822
Test name
Test status
Simulation time 2385926511 ps
CPU time 1.26 seconds
Started May 23 01:39:01 PM PDT 24
Finished May 23 01:39:03 PM PDT 24
Peak memory 201316 kb
Host smart-805ed059-8e25-427d-ac1f-672157fdfcd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393190929 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_mem_rw_with_rand_reset.393190929
Directory /workspace/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.4073313873
Short name T906
Test name
Test status
Simulation time 2098022734 ps
CPU time 2.97 seconds
Started May 23 01:38:53 PM PDT 24
Finished May 23 01:38:57 PM PDT 24
Peak memory 201732 kb
Host smart-49959aab-b26e-40ab-9360-d2771d3e8307
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073313873 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_
rw.4073313873
Directory /workspace/15.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.3289401364
Short name T872
Test name
Test status
Simulation time 2037558174 ps
CPU time 1.99 seconds
Started May 23 01:38:59 PM PDT 24
Finished May 23 01:39:02 PM PDT 24
Peak memory 201564 kb
Host smart-dd263081-4ec2-4782-9051-0cdfca18f919
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289401364 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_te
st.3289401364
Directory /workspace/15.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.3779903271
Short name T325
Test name
Test status
Simulation time 9684832552 ps
CPU time 15.76 seconds
Started May 23 01:38:51 PM PDT 24
Finished May 23 01:39:08 PM PDT 24
Peak memory 201896 kb
Host smart-e355d0d6-0078-4c70-a71c-dbbd6b858665
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779903271 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
5.sysrst_ctrl_same_csr_outstanding.3779903271
Directory /workspace/15.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.1435433086
Short name T884
Test name
Test status
Simulation time 2371136881 ps
CPU time 2.46 seconds
Started May 23 01:38:59 PM PDT 24
Finished May 23 01:39:03 PM PDT 24
Peak memory 201908 kb
Host smart-2eb16346-cd99-40b8-b886-3464c9cbe9de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435433086 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_erro
rs.1435433086
Directory /workspace/15.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.1102880946
Short name T812
Test name
Test status
Simulation time 2229161729 ps
CPU time 2.52 seconds
Started May 23 01:38:57 PM PDT 24
Finished May 23 01:39:01 PM PDT 24
Peak memory 217496 kb
Host smart-e3275f07-7cbe-49c5-bd7d-fec0b76919ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102880946 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_mem_rw_with_rand_reset.1102880946
Directory /workspace/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.774955904
Short name T314
Test name
Test status
Simulation time 2039149641 ps
CPU time 6.21 seconds
Started May 23 01:38:51 PM PDT 24
Finished May 23 01:38:58 PM PDT 24
Peak memory 201672 kb
Host smart-761878b6-18a9-427e-a75e-1413fbfed949
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774955904 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_r
w.774955904
Directory /workspace/16.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.1232885082
Short name T811
Test name
Test status
Simulation time 2013433363 ps
CPU time 6.09 seconds
Started May 23 01:38:49 PM PDT 24
Finished May 23 01:38:57 PM PDT 24
Peak memory 201556 kb
Host smart-b61ba767-920f-4646-b19d-a94b266380d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232885082 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_te
st.1232885082
Directory /workspace/16.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.965950067
Short name T902
Test name
Test status
Simulation time 9548553060 ps
CPU time 12.6 seconds
Started May 23 01:38:52 PM PDT 24
Finished May 23 01:39:06 PM PDT 24
Peak memory 201948 kb
Host smart-70f139dd-f721-4099-9085-3b8a6afddfd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965950067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.sysrst_ctrl_same_csr_outstanding.965950067
Directory /workspace/16.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.2945084270
Short name T278
Test name
Test status
Simulation time 2230973949 ps
CPU time 5.38 seconds
Started May 23 01:38:58 PM PDT 24
Finished May 23 01:39:04 PM PDT 24
Peak memory 210212 kb
Host smart-c90637ed-cb76-4477-8fa0-c50527bfe343
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945084270 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_erro
rs.2945084270
Directory /workspace/16.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.1546579331
Short name T336
Test name
Test status
Simulation time 22192634404 ps
CPU time 56.52 seconds
Started May 23 01:38:55 PM PDT 24
Finished May 23 01:39:52 PM PDT 24
Peak memory 202012 kb
Host smart-717b760b-5b6c-4767-93f8-a9a9f2fa2797
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546579331 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_tl_intg_err.1546579331
Directory /workspace/16.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.371191361
Short name T879
Test name
Test status
Simulation time 2077743129 ps
CPU time 6.07 seconds
Started May 23 01:38:48 PM PDT 24
Finished May 23 01:38:55 PM PDT 24
Peak memory 201824 kb
Host smart-f9cf5b02-5bb6-4e56-8d47-5a333b4d0732
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371191361 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_mem_rw_with_rand_reset.371191361
Directory /workspace/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.2605722709
Short name T831
Test name
Test status
Simulation time 2027032509 ps
CPU time 3.4 seconds
Started May 23 01:38:56 PM PDT 24
Finished May 23 01:39:00 PM PDT 24
Peak memory 201264 kb
Host smart-4544bc34-03e9-426e-b495-d9e22ffbd3a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605722709 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_te
st.2605722709
Directory /workspace/17.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.1195572972
Short name T888
Test name
Test status
Simulation time 4499687082 ps
CPU time 18.03 seconds
Started May 23 01:38:58 PM PDT 24
Finished May 23 01:39:17 PM PDT 24
Peak memory 201816 kb
Host smart-2b1df828-3b04-4a46-8252-9156fa3ab3df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195572972 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
7.sysrst_ctrl_same_csr_outstanding.1195572972
Directory /workspace/17.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.1010936748
Short name T275
Test name
Test status
Simulation time 2025866419 ps
CPU time 6.68 seconds
Started May 23 01:38:55 PM PDT 24
Finished May 23 01:39:03 PM PDT 24
Peak memory 201820 kb
Host smart-b2eab479-636d-4b2f-8f9a-92a1709b1ed9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010936748 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_erro
rs.1010936748
Directory /workspace/17.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.4098806736
Short name T874
Test name
Test status
Simulation time 22678727290 ps
CPU time 10.35 seconds
Started May 23 01:38:50 PM PDT 24
Finished May 23 01:39:02 PM PDT 24
Peak memory 202032 kb
Host smart-42ad822e-8255-424c-8db9-2ec093bac849
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098806736 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_tl_intg_err.4098806736
Directory /workspace/17.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.1409430034
Short name T821
Test name
Test status
Simulation time 2147056729 ps
CPU time 3.66 seconds
Started May 23 01:39:01 PM PDT 24
Finished May 23 01:39:05 PM PDT 24
Peak memory 201456 kb
Host smart-b438e535-58b2-49ef-97a0-45f7c160f60d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409430034 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_mem_rw_with_rand_reset.1409430034
Directory /workspace/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.2285924072
Short name T866
Test name
Test status
Simulation time 2043101943 ps
CPU time 6.01 seconds
Started May 23 01:38:58 PM PDT 24
Finished May 23 01:39:05 PM PDT 24
Peak memory 201612 kb
Host smart-416d71c0-5886-4d23-a26a-7af12d868aa4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285924072 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_
rw.2285924072
Directory /workspace/18.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.3584033882
Short name T813
Test name
Test status
Simulation time 2012245425 ps
CPU time 5.94 seconds
Started May 23 01:38:56 PM PDT 24
Finished May 23 01:39:03 PM PDT 24
Peak memory 201464 kb
Host smart-dc1b21ba-7ae6-4771-8db3-907e15b07552
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584033882 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_te
st.3584033882
Directory /workspace/18.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2080749175
Short name T909
Test name
Test status
Simulation time 4825240790 ps
CPU time 5.55 seconds
Started May 23 01:38:59 PM PDT 24
Finished May 23 01:39:06 PM PDT 24
Peak memory 201972 kb
Host smart-5ae39a55-1640-46d2-9d56-55af0af47f64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080749175 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
8.sysrst_ctrl_same_csr_outstanding.2080749175
Directory /workspace/18.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2829131636
Short name T875
Test name
Test status
Simulation time 2048604874 ps
CPU time 3.98 seconds
Started May 23 01:38:52 PM PDT 24
Finished May 23 01:38:57 PM PDT 24
Peak memory 201956 kb
Host smart-8b4016f9-46f0-4a74-becc-b45702ebcbba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829131636 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_erro
rs.2829131636
Directory /workspace/18.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.1281358965
Short name T270
Test name
Test status
Simulation time 42928394944 ps
CPU time 15.14 seconds
Started May 23 01:38:57 PM PDT 24
Finished May 23 01:39:13 PM PDT 24
Peak memory 201976 kb
Host smart-3c932696-f8e0-4be0-ba06-3f33e895f526
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281358965 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_tl_intg_err.1281358965
Directory /workspace/18.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3295804498
Short name T903
Test name
Test status
Simulation time 2265718965 ps
CPU time 2.48 seconds
Started May 23 01:39:03 PM PDT 24
Finished May 23 01:39:06 PM PDT 24
Peak memory 202052 kb
Host smart-d7ba51c5-8979-4340-9579-ab679ff3bf34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295804498 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3295804498
Directory /workspace/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.884374223
Short name T307
Test name
Test status
Simulation time 2052111841 ps
CPU time 2.1 seconds
Started May 23 01:39:05 PM PDT 24
Finished May 23 01:39:10 PM PDT 24
Peak memory 201760 kb
Host smart-3b961f6c-a1bb-441e-976e-aa66f8d21eae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884374223 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_r
w.884374223
Directory /workspace/19.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.1234652270
Short name T878
Test name
Test status
Simulation time 2026125401 ps
CPU time 3.14 seconds
Started May 23 01:39:05 PM PDT 24
Finished May 23 01:39:10 PM PDT 24
Peak memory 201328 kb
Host smart-4601363f-703a-4613-b18e-c80121a72bbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234652270 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_te
st.1234652270
Directory /workspace/19.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.1642942772
Short name T832
Test name
Test status
Simulation time 10004548599 ps
CPU time 13.47 seconds
Started May 23 01:39:06 PM PDT 24
Finished May 23 01:39:22 PM PDT 24
Peak memory 201920 kb
Host smart-08472cd7-f2c1-4500-9347-bf2253725bd6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642942772 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
9.sysrst_ctrl_same_csr_outstanding.1642942772
Directory /workspace/19.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.3536066687
Short name T901
Test name
Test status
Simulation time 2035421027 ps
CPU time 6.91 seconds
Started May 23 01:39:03 PM PDT 24
Finished May 23 01:39:10 PM PDT 24
Peak memory 201896 kb
Host smart-01f8c8dd-f6ad-4dfd-beb6-d307d0746447
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536066687 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_erro
rs.3536066687
Directory /workspace/19.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2089042580
Short name T881
Test name
Test status
Simulation time 22187205276 ps
CPU time 57.91 seconds
Started May 23 01:39:05 PM PDT 24
Finished May 23 01:40:06 PM PDT 24
Peak memory 201988 kb
Host smart-75c4df17-a860-47d6-8d9f-702d7e4612b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089042580 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_tl_intg_err.2089042580
Directory /workspace/19.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.3293637766
Short name T316
Test name
Test status
Simulation time 2583177730 ps
CPU time 3.8 seconds
Started May 23 01:38:29 PM PDT 24
Finished May 23 01:38:34 PM PDT 24
Peak memory 202052 kb
Host smart-52e934c5-bc66-421f-b753-8c429e5dd825
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293637766 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_aliasing.3293637766
Directory /workspace/2.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.860582632
Short name T326
Test name
Test status
Simulation time 38827507596 ps
CPU time 110.53 seconds
Started May 23 01:38:29 PM PDT 24
Finished May 23 01:40:21 PM PDT 24
Peak memory 201872 kb
Host smart-c6ac9d57-415c-4096-b43f-da5449521776
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860582632 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_
csr_bit_bash.860582632
Directory /workspace/2.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.4061323354
Short name T309
Test name
Test status
Simulation time 4053586996 ps
CPU time 3.26 seconds
Started May 23 01:38:28 PM PDT 24
Finished May 23 01:38:32 PM PDT 24
Peak memory 201640 kb
Host smart-583036e5-2f37-475b-810f-fcd153dff6d5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061323354 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_hw_reset.4061323354
Directory /workspace/2.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.2200944765
Short name T912
Test name
Test status
Simulation time 2215221517 ps
CPU time 2.45 seconds
Started May 23 01:38:26 PM PDT 24
Finished May 23 01:38:31 PM PDT 24
Peak memory 201900 kb
Host smart-6431a8b7-1cdd-4288-863c-b9fc3230cac3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200944765 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_mem_rw_with_rand_reset.2200944765
Directory /workspace/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.707874681
Short name T321
Test name
Test status
Simulation time 2046249409 ps
CPU time 6.36 seconds
Started May 23 01:38:29 PM PDT 24
Finished May 23 01:38:37 PM PDT 24
Peak memory 201700 kb
Host smart-bf034a9f-e002-4687-8e3c-ff10222fe2b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707874681 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_rw
.707874681
Directory /workspace/2.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.2074769730
Short name T825
Test name
Test status
Simulation time 2022400022 ps
CPU time 3.99 seconds
Started May 23 01:38:28 PM PDT 24
Finished May 23 01:38:33 PM PDT 24
Peak memory 201256 kb
Host smart-921ab851-e979-4155-84c7-1123b734d8f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074769730 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_tes
t.2074769730
Directory /workspace/2.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.2521969794
Short name T18
Test name
Test status
Simulation time 4407029416 ps
CPU time 16.26 seconds
Started May 23 01:38:32 PM PDT 24
Finished May 23 01:38:50 PM PDT 24
Peak memory 201772 kb
Host smart-decba1f5-534b-4446-b893-a3e2a6f60286
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521969794 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.sysrst_ctrl_same_csr_outstanding.2521969794
Directory /workspace/2.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2163977584
Short name T868
Test name
Test status
Simulation time 2342211685 ps
CPU time 3.16 seconds
Started May 23 01:38:27 PM PDT 24
Finished May 23 01:38:32 PM PDT 24
Peak memory 202024 kb
Host smart-76b73a7a-c33d-466e-bd95-ddcca90e759a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163977584 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_error
s.2163977584
Directory /workspace/2.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.255584486
Short name T830
Test name
Test status
Simulation time 42367116845 ps
CPU time 124.68 seconds
Started May 23 01:38:28 PM PDT 24
Finished May 23 01:40:34 PM PDT 24
Peak memory 201976 kb
Host smart-7b8fb4fa-3362-4638-86fc-4bbee17a2b08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255584486 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ct
rl_tl_intg_err.255584486
Directory /workspace/2.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.926370961
Short name T863
Test name
Test status
Simulation time 2013654349 ps
CPU time 5.8 seconds
Started May 23 01:39:06 PM PDT 24
Finished May 23 01:39:14 PM PDT 24
Peak memory 201312 kb
Host smart-61150153-c0b5-4ed4-b72c-2ebc813a41d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926370961 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_tes
t.926370961
Directory /workspace/20.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.2921614367
Short name T907
Test name
Test status
Simulation time 2019373274 ps
CPU time 3.29 seconds
Started May 23 01:39:05 PM PDT 24
Finished May 23 01:39:11 PM PDT 24
Peak memory 201588 kb
Host smart-8265b3a5-c048-4e48-83e6-1da2dd416b24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921614367 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_te
st.2921614367
Directory /workspace/21.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.3644463362
Short name T798
Test name
Test status
Simulation time 2021997587 ps
CPU time 1.99 seconds
Started May 23 01:39:07 PM PDT 24
Finished May 23 01:39:11 PM PDT 24
Peak memory 201556 kb
Host smart-e1c8b0d8-647c-4e25-ab6a-d68d7ec127f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644463362 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_te
st.3644463362
Directory /workspace/22.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.3951370463
Short name T873
Test name
Test status
Simulation time 2130871829 ps
CPU time 1.14 seconds
Started May 23 01:39:02 PM PDT 24
Finished May 23 01:39:04 PM PDT 24
Peak memory 201544 kb
Host smart-29a0fb5b-e6c7-4153-9ee2-963d77821e90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951370463 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_te
st.3951370463
Directory /workspace/23.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.23532545
Short name T852
Test name
Test status
Simulation time 2014379669 ps
CPU time 5.71 seconds
Started May 23 01:39:05 PM PDT 24
Finished May 23 01:39:13 PM PDT 24
Peak memory 201308 kb
Host smart-6f5cf883-0d5b-4372-8f48-4df2dd131cc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23532545 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_test
.23532545
Directory /workspace/24.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.1994846133
Short name T818
Test name
Test status
Simulation time 2017216861 ps
CPU time 5.89 seconds
Started May 23 01:39:07 PM PDT 24
Finished May 23 01:39:15 PM PDT 24
Peak memory 201300 kb
Host smart-d82fb315-d8d9-474e-a822-eaccbc7a3f78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994846133 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_te
st.1994846133
Directory /workspace/25.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.1225476490
Short name T801
Test name
Test status
Simulation time 2085352549 ps
CPU time 1.06 seconds
Started May 23 01:39:06 PM PDT 24
Finished May 23 01:39:09 PM PDT 24
Peak memory 201324 kb
Host smart-5a419b6a-646e-4be3-bbc0-f16286758ec0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225476490 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_te
st.1225476490
Directory /workspace/26.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.534068737
Short name T808
Test name
Test status
Simulation time 2011089914 ps
CPU time 5.83 seconds
Started May 23 01:39:02 PM PDT 24
Finished May 23 01:39:08 PM PDT 24
Peak memory 201372 kb
Host smart-f0f37957-f710-48ca-9b92-536b998012d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534068737 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_tes
t.534068737
Directory /workspace/27.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.3237090682
Short name T892
Test name
Test status
Simulation time 2051611812 ps
CPU time 1.68 seconds
Started May 23 01:39:02 PM PDT 24
Finished May 23 01:39:04 PM PDT 24
Peak memory 201328 kb
Host smart-2456d56e-6893-4811-9ea8-26dfcc2eb277
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237090682 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_te
st.3237090682
Directory /workspace/28.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.1542187712
Short name T827
Test name
Test status
Simulation time 2039247912 ps
CPU time 1.89 seconds
Started May 23 01:39:04 PM PDT 24
Finished May 23 01:39:08 PM PDT 24
Peak memory 201320 kb
Host smart-2cdd7b6b-c73d-4997-b1f1-004440d0aa95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542187712 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_te
st.1542187712
Directory /workspace/29.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.1441124560
Short name T833
Test name
Test status
Simulation time 2726341686 ps
CPU time 3.47 seconds
Started May 23 01:38:39 PM PDT 24
Finished May 23 01:38:43 PM PDT 24
Peak memory 201936 kb
Host smart-c07afedd-f947-4d09-8233-aee23e54a858
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441124560 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_aliasing.1441124560
Directory /workspace/3.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.567935409
Short name T853
Test name
Test status
Simulation time 39823820453 ps
CPU time 110.39 seconds
Started May 23 01:38:37 PM PDT 24
Finished May 23 01:40:29 PM PDT 24
Peak memory 201992 kb
Host smart-41b456c8-34c5-4c04-a2e0-1c1596dcd282
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567935409 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_
csr_bit_bash.567935409
Directory /workspace/3.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.2752879653
Short name T829
Test name
Test status
Simulation time 4045468462 ps
CPU time 3.37 seconds
Started May 23 01:38:32 PM PDT 24
Finished May 23 01:38:36 PM PDT 24
Peak memory 201716 kb
Host smart-3509b46a-3965-4dcd-ba79-39cffa0272c0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752879653 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_hw_reset.2752879653
Directory /workspace/3.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.1104548473
Short name T28
Test name
Test status
Simulation time 2068239585 ps
CPU time 3.76 seconds
Started May 23 01:38:43 PM PDT 24
Finished May 23 01:38:47 PM PDT 24
Peak memory 201776 kb
Host smart-3eec04d1-9d99-4cca-af77-802821b40cd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104548473 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_mem_rw_with_rand_reset.1104548473
Directory /workspace/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.1763705581
Short name T860
Test name
Test status
Simulation time 2083831387 ps
CPU time 2.16 seconds
Started May 23 01:38:32 PM PDT 24
Finished May 23 01:38:35 PM PDT 24
Peak memory 201772 kb
Host smart-b8c85479-2151-42e5-8ac9-bdd1be25649d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763705581 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_r
w.1763705581
Directory /workspace/3.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.3199740750
Short name T828
Test name
Test status
Simulation time 2044872139 ps
CPU time 1.94 seconds
Started May 23 01:38:29 PM PDT 24
Finished May 23 01:38:32 PM PDT 24
Peak memory 201268 kb
Host smart-99e4a4fb-ce92-4771-a448-07656d4a3483
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199740750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_tes
t.3199740750
Directory /workspace/3.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.2601850912
Short name T20
Test name
Test status
Simulation time 7427112548 ps
CPU time 17.75 seconds
Started May 23 01:38:40 PM PDT 24
Finished May 23 01:38:59 PM PDT 24
Peak memory 202016 kb
Host smart-9f3e0c7f-4ae5-4357-b081-682a4c7a2f61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601850912 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.sysrst_ctrl_same_csr_outstanding.2601850912
Directory /workspace/3.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.3136564338
Short name T845
Test name
Test status
Simulation time 2064114955 ps
CPU time 2.29 seconds
Started May 23 01:38:32 PM PDT 24
Finished May 23 01:38:36 PM PDT 24
Peak memory 201724 kb
Host smart-fa4f9aba-ccc4-4f96-aec3-a4c79aab3ac2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136564338 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_error
s.3136564338
Directory /workspace/3.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.227885124
Short name T338
Test name
Test status
Simulation time 22267054583 ps
CPU time 17.05 seconds
Started May 23 01:38:33 PM PDT 24
Finished May 23 01:38:51 PM PDT 24
Peak memory 202028 kb
Host smart-bd293cde-bb46-4653-9695-708e4d6b3ef7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227885124 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ct
rl_tl_intg_err.227885124
Directory /workspace/3.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.1979704530
Short name T854
Test name
Test status
Simulation time 2013101975 ps
CPU time 3.2 seconds
Started May 23 01:39:06 PM PDT 24
Finished May 23 01:39:11 PM PDT 24
Peak memory 201288 kb
Host smart-600737a8-07b5-4ec7-8e2f-3888bc41e9bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979704530 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_te
st.1979704530
Directory /workspace/30.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.2016824472
Short name T904
Test name
Test status
Simulation time 2012110612 ps
CPU time 5.99 seconds
Started May 23 01:39:05 PM PDT 24
Finished May 23 01:39:13 PM PDT 24
Peak memory 201264 kb
Host smart-00d7bd50-faf6-47ef-89f0-501f10c0bd1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016824472 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_te
st.2016824472
Directory /workspace/31.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.916243518
Short name T809
Test name
Test status
Simulation time 2007630579 ps
CPU time 6.23 seconds
Started May 23 01:39:03 PM PDT 24
Finished May 23 01:39:11 PM PDT 24
Peak memory 201324 kb
Host smart-828ca22d-f22a-4c77-92ec-896c647938ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916243518 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_tes
t.916243518
Directory /workspace/32.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.2323113105
Short name T897
Test name
Test status
Simulation time 2013589079 ps
CPU time 4.62 seconds
Started May 23 01:39:03 PM PDT 24
Finished May 23 01:39:09 PM PDT 24
Peak memory 201260 kb
Host smart-61148673-af01-4d28-8ba1-8f89b197d8c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323113105 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_te
st.2323113105
Directory /workspace/33.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.1394872826
Short name T800
Test name
Test status
Simulation time 2035129218 ps
CPU time 2.03 seconds
Started May 23 01:39:05 PM PDT 24
Finished May 23 01:39:10 PM PDT 24
Peak memory 201344 kb
Host smart-bf4e16fc-cf94-4c14-b1a3-0d53b60e7dd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394872826 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_te
st.1394872826
Directory /workspace/34.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.2812171208
Short name T843
Test name
Test status
Simulation time 2009516423 ps
CPU time 5.57 seconds
Started May 23 01:39:06 PM PDT 24
Finished May 23 01:39:14 PM PDT 24
Peak memory 201580 kb
Host smart-5000d069-e4a3-4226-a885-9bf4161f05b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812171208 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_te
st.2812171208
Directory /workspace/35.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.2457515198
Short name T895
Test name
Test status
Simulation time 2014322442 ps
CPU time 6 seconds
Started May 23 01:39:05 PM PDT 24
Finished May 23 01:39:13 PM PDT 24
Peak memory 201292 kb
Host smart-fe1e3042-1b21-4666-ac95-3a7cd82a1c17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457515198 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_te
st.2457515198
Directory /workspace/36.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.1336881558
Short name T876
Test name
Test status
Simulation time 2062477875 ps
CPU time 1.46 seconds
Started May 23 01:39:06 PM PDT 24
Finished May 23 01:39:10 PM PDT 24
Peak memory 201512 kb
Host smart-fa8c1462-60f4-439e-92ef-b41f6ab0260d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336881558 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_te
st.1336881558
Directory /workspace/37.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.1797491328
Short name T807
Test name
Test status
Simulation time 2018767299 ps
CPU time 3.08 seconds
Started May 23 01:39:08 PM PDT 24
Finished May 23 01:39:14 PM PDT 24
Peak memory 201264 kb
Host smart-3b55a79e-c926-4778-8214-8c24fedae3a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797491328 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_te
st.1797491328
Directory /workspace/38.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.878228220
Short name T826
Test name
Test status
Simulation time 2014886487 ps
CPU time 5.99 seconds
Started May 23 01:39:06 PM PDT 24
Finished May 23 01:39:14 PM PDT 24
Peak memory 201568 kb
Host smart-2c190dba-a649-49b6-b42c-ce3c2a52127b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878228220 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_tes
t.878228220
Directory /workspace/39.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.3694094578
Short name T318
Test name
Test status
Simulation time 2399315561 ps
CPU time 2.74 seconds
Started May 23 01:38:38 PM PDT 24
Finished May 23 01:38:41 PM PDT 24
Peak memory 201852 kb
Host smart-3563fe6b-b2b2-46e0-9b4a-8ca6412d2a7c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694094578 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_aliasing.3694094578
Directory /workspace/4.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.2113461371
Short name T313
Test name
Test status
Simulation time 22058002020 ps
CPU time 7.04 seconds
Started May 23 01:38:41 PM PDT 24
Finished May 23 01:38:49 PM PDT 24
Peak memory 201956 kb
Host smart-f242d886-16a1-4dc2-9727-73dd015d2cc9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113461371 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_bit_bash.2113461371
Directory /workspace/4.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.3011856731
Short name T27
Test name
Test status
Simulation time 4075933105 ps
CPU time 2.51 seconds
Started May 23 01:38:42 PM PDT 24
Finished May 23 01:38:45 PM PDT 24
Peak memory 201808 kb
Host smart-d23d52f3-4072-44c3-81f8-a2efcbe88196
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011856731 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_hw_reset.3011856731
Directory /workspace/4.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1179895032
Short name T816
Test name
Test status
Simulation time 2070367255 ps
CPU time 6.15 seconds
Started May 23 01:38:39 PM PDT 24
Finished May 23 01:38:47 PM PDT 24
Peak memory 201744 kb
Host smart-e3a9f625-3584-49dc-b159-d8a7d282c379
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179895032 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1179895032
Directory /workspace/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.693297478
Short name T320
Test name
Test status
Simulation time 2045786908 ps
CPU time 6.55 seconds
Started May 23 01:38:42 PM PDT 24
Finished May 23 01:38:49 PM PDT 24
Peak memory 201768 kb
Host smart-9c0d2391-5886-4ca9-9efb-32649df8ff79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693297478 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_rw
.693297478
Directory /workspace/4.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.4131873401
Short name T890
Test name
Test status
Simulation time 2118906045 ps
CPU time 1 seconds
Started May 23 01:38:38 PM PDT 24
Finished May 23 01:38:40 PM PDT 24
Peak memory 201560 kb
Host smart-8fc952ce-f0d3-46d7-9d10-b25e207eae8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131873401 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_tes
t.4131873401
Directory /workspace/4.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.4197304480
Short name T834
Test name
Test status
Simulation time 4783185183 ps
CPU time 6.53 seconds
Started May 23 01:38:40 PM PDT 24
Finished May 23 01:38:48 PM PDT 24
Peak memory 202008 kb
Host smart-91dd9bc4-7332-4ddb-b38e-f75f2f46dd2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197304480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.sysrst_ctrl_same_csr_outstanding.4197304480
Directory /workspace/4.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.3887410105
Short name T886
Test name
Test status
Simulation time 2211086753 ps
CPU time 5.2 seconds
Started May 23 01:38:37 PM PDT 24
Finished May 23 01:38:43 PM PDT 24
Peak memory 201880 kb
Host smart-7ef2a7cd-73cc-4037-a5cc-e64b440d779a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887410105 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_error
s.3887410105
Directory /workspace/4.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.413468809
Short name T896
Test name
Test status
Simulation time 43158076440 ps
CPU time 19.99 seconds
Started May 23 01:38:43 PM PDT 24
Finished May 23 01:39:04 PM PDT 24
Peak memory 202040 kb
Host smart-90da8ddf-37cb-4708-974c-461e9aa8f6f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413468809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ct
rl_tl_intg_err.413468809
Directory /workspace/4.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.1380401773
Short name T815
Test name
Test status
Simulation time 2016273308 ps
CPU time 5.83 seconds
Started May 23 01:39:06 PM PDT 24
Finished May 23 01:39:14 PM PDT 24
Peak memory 201548 kb
Host smart-583bde9c-8340-4c3f-8dc8-a7593bd7fd4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380401773 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_te
st.1380401773
Directory /workspace/40.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.2721910792
Short name T835
Test name
Test status
Simulation time 2023765608 ps
CPU time 2.17 seconds
Started May 23 01:39:08 PM PDT 24
Finished May 23 01:39:12 PM PDT 24
Peak memory 201260 kb
Host smart-665cf88e-916a-4f00-9923-a08add9610b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721910792 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_te
st.2721910792
Directory /workspace/41.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.1327039144
Short name T851
Test name
Test status
Simulation time 2011290847 ps
CPU time 5.36 seconds
Started May 23 01:39:04 PM PDT 24
Finished May 23 01:39:11 PM PDT 24
Peak memory 201524 kb
Host smart-5c9d54b8-d312-4ed1-b4e3-7a1cc2784f8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327039144 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_te
st.1327039144
Directory /workspace/42.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.153778017
Short name T806
Test name
Test status
Simulation time 2029342134 ps
CPU time 1.98 seconds
Started May 23 01:39:05 PM PDT 24
Finished May 23 01:39:09 PM PDT 24
Peak memory 201276 kb
Host smart-45bdb409-47e5-4c45-a96d-07ac391e0b0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153778017 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_tes
t.153778017
Directory /workspace/43.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.197171159
Short name T819
Test name
Test status
Simulation time 2021408003 ps
CPU time 3.5 seconds
Started May 23 01:39:06 PM PDT 24
Finished May 23 01:39:11 PM PDT 24
Peak memory 201568 kb
Host smart-847bac5d-073e-46d2-aa95-d0716a034576
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197171159 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_tes
t.197171159
Directory /workspace/44.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.249305666
Short name T797
Test name
Test status
Simulation time 2066285298 ps
CPU time 1.33 seconds
Started May 23 01:39:05 PM PDT 24
Finished May 23 01:39:08 PM PDT 24
Peak memory 201312 kb
Host smart-5649af14-a089-4365-a6c2-27a484aadd73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249305666 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_tes
t.249305666
Directory /workspace/45.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.913202317
Short name T810
Test name
Test status
Simulation time 2011080159 ps
CPU time 6.09 seconds
Started May 23 01:39:04 PM PDT 24
Finished May 23 01:39:11 PM PDT 24
Peak memory 201292 kb
Host smart-97958c00-5e65-4ae1-99c8-3fda06e17b63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913202317 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_tes
t.913202317
Directory /workspace/46.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.2353874035
Short name T871
Test name
Test status
Simulation time 2011722734 ps
CPU time 5.69 seconds
Started May 23 01:39:05 PM PDT 24
Finished May 23 01:39:12 PM PDT 24
Peak memory 201316 kb
Host smart-18bab26d-a85a-4790-8211-48daac64952a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353874035 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_te
st.2353874035
Directory /workspace/47.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.3713027977
Short name T885
Test name
Test status
Simulation time 2038849275 ps
CPU time 1.93 seconds
Started May 23 01:39:05 PM PDT 24
Finished May 23 01:39:09 PM PDT 24
Peak memory 201328 kb
Host smart-d8235ec2-588d-41f4-af00-f5743688b7eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713027977 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_te
st.3713027977
Directory /workspace/48.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.1201848343
Short name T899
Test name
Test status
Simulation time 2009410945 ps
CPU time 6.13 seconds
Started May 23 01:39:08 PM PDT 24
Finished May 23 01:39:17 PM PDT 24
Peak memory 201260 kb
Host smart-1b194f2f-f878-4b74-8f4b-6fc9cc24a8c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201848343 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_te
st.1201848343
Directory /workspace/49.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.2103945620
Short name T282
Test name
Test status
Simulation time 2040121030 ps
CPU time 6.33 seconds
Started May 23 01:38:42 PM PDT 24
Finished May 23 01:38:49 PM PDT 24
Peak memory 201740 kb
Host smart-a636545a-5297-4258-8e3f-03a09c6426b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103945620 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_mem_rw_with_rand_reset.2103945620
Directory /workspace/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.3276277156
Short name T319
Test name
Test status
Simulation time 2085152497 ps
CPU time 2.11 seconds
Started May 23 01:38:39 PM PDT 24
Finished May 23 01:38:42 PM PDT 24
Peak memory 201684 kb
Host smart-ab2f1f54-366c-4a8b-bb89-4542bb3f651a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276277156 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_r
w.3276277156
Directory /workspace/5.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.445704826
Short name T905
Test name
Test status
Simulation time 2012149318 ps
CPU time 5.47 seconds
Started May 23 01:38:44 PM PDT 24
Finished May 23 01:38:50 PM PDT 24
Peak memory 201256 kb
Host smart-13028f69-8580-43d6-8f1c-87713bc8735b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445704826 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_test
.445704826
Directory /workspace/5.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.1776569620
Short name T859
Test name
Test status
Simulation time 4667827493 ps
CPU time 9.93 seconds
Started May 23 01:38:50 PM PDT 24
Finished May 23 01:39:01 PM PDT 24
Peak memory 201944 kb
Host smart-e53d3366-f7db-4012-b9b5-14f93e85a5c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776569620 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5
.sysrst_ctrl_same_csr_outstanding.1776569620
Directory /workspace/5.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.3308535910
Short name T882
Test name
Test status
Simulation time 2183445852 ps
CPU time 6.98 seconds
Started May 23 01:38:38 PM PDT 24
Finished May 23 01:38:46 PM PDT 24
Peak memory 201960 kb
Host smart-7e120b78-b709-42e0-9039-7d3fbd77bbfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308535910 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_error
s.3308535910
Directory /workspace/5.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.3205476340
Short name T865
Test name
Test status
Simulation time 2267913301 ps
CPU time 2.05 seconds
Started May 23 01:38:40 PM PDT 24
Finished May 23 01:38:43 PM PDT 24
Peak memory 201808 kb
Host smart-7157abc6-23ee-43f0-80b4-b8ed8da06268
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205476340 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_mem_rw_with_rand_reset.3205476340
Directory /workspace/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.3394189652
Short name T311
Test name
Test status
Simulation time 2046796247 ps
CPU time 2.12 seconds
Started May 23 01:38:40 PM PDT 24
Finished May 23 01:38:43 PM PDT 24
Peak memory 201684 kb
Host smart-fddf6349-8da7-4f64-b091-8a7e9c2e7ebc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394189652 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_r
w.3394189652
Directory /workspace/6.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.4059888154
Short name T900
Test name
Test status
Simulation time 2013189547 ps
CPU time 5.8 seconds
Started May 23 01:38:40 PM PDT 24
Finished May 23 01:38:47 PM PDT 24
Peak memory 201340 kb
Host smart-ba5c264c-2376-4b24-8b3d-db00f3a36749
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059888154 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_tes
t.4059888154
Directory /workspace/6.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.2343540539
Short name T869
Test name
Test status
Simulation time 5509968210 ps
CPU time 3.88 seconds
Started May 23 01:38:39 PM PDT 24
Finished May 23 01:38:44 PM PDT 24
Peak memory 201964 kb
Host smart-b45e0eac-05ca-41b4-b096-9b1577e59346
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343540539 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6
.sysrst_ctrl_same_csr_outstanding.2343540539
Directory /workspace/6.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.1961633403
Short name T277
Test name
Test status
Simulation time 2106134946 ps
CPU time 2.71 seconds
Started May 23 01:38:49 PM PDT 24
Finished May 23 01:38:53 PM PDT 24
Peak memory 201940 kb
Host smart-20d44ab3-9622-4a45-a9bd-b092b6a6feae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961633403 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_error
s.1961633403
Directory /workspace/6.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.1247838573
Short name T823
Test name
Test status
Simulation time 22182926955 ps
CPU time 58.2 seconds
Started May 23 01:38:39 PM PDT 24
Finished May 23 01:39:39 PM PDT 24
Peak memory 201944 kb
Host smart-cfcc0255-df67-4de9-8a03-8abf8cec91c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247838573 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_tl_intg_err.1247838573
Directory /workspace/6.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3994935278
Short name T283
Test name
Test status
Simulation time 2132446224 ps
CPU time 6.89 seconds
Started May 23 01:38:42 PM PDT 24
Finished May 23 01:38:50 PM PDT 24
Peak memory 201696 kb
Host smart-cfc81229-d654-4588-8157-0b5513972dd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994935278 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3994935278
Directory /workspace/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.317227671
Short name T862
Test name
Test status
Simulation time 2103277659 ps
CPU time 2.27 seconds
Started May 23 01:38:47 PM PDT 24
Finished May 23 01:38:51 PM PDT 24
Peak memory 201776 kb
Host smart-b3a2542c-d6b2-4742-ab99-d4da7acd348c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317227671 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_rw
.317227671
Directory /workspace/7.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.2942108597
Short name T842
Test name
Test status
Simulation time 2012733098 ps
CPU time 5.7 seconds
Started May 23 01:38:47 PM PDT 24
Finished May 23 01:38:54 PM PDT 24
Peak memory 201584 kb
Host smart-984e0ebe-74a0-451a-8dd6-4d817a4a71b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942108597 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_tes
t.2942108597
Directory /workspace/7.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.2651509869
Short name T19
Test name
Test status
Simulation time 4435800749 ps
CPU time 17.34 seconds
Started May 23 01:38:39 PM PDT 24
Finished May 23 01:38:58 PM PDT 24
Peak memory 201768 kb
Host smart-9b4292fa-44d1-45ac-b995-a6526717b4c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651509869 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7
.sysrst_ctrl_same_csr_outstanding.2651509869
Directory /workspace/7.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.2873677315
Short name T268
Test name
Test status
Simulation time 2081891936 ps
CPU time 3.88 seconds
Started May 23 01:38:42 PM PDT 24
Finished May 23 01:38:48 PM PDT 24
Peak memory 201836 kb
Host smart-e3c2f981-ecb6-498c-8bd6-3d952c855c31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873677315 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_error
s.2873677315
Directory /workspace/7.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.1731566226
Short name T849
Test name
Test status
Simulation time 22297703662 ps
CPU time 29.97 seconds
Started May 23 01:38:48 PM PDT 24
Finished May 23 01:39:19 PM PDT 24
Peak memory 201952 kb
Host smart-a89e5d25-02d9-4c32-9c08-920847679340
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731566226 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_tl_intg_err.1731566226
Directory /workspace/7.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.2887287327
Short name T267
Test name
Test status
Simulation time 2153442985 ps
CPU time 3.63 seconds
Started May 23 01:38:38 PM PDT 24
Finished May 23 01:38:42 PM PDT 24
Peak memory 201884 kb
Host smart-0f655e8b-08be-459d-8f9a-61b095d21967
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887287327 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_mem_rw_with_rand_reset.2887287327
Directory /workspace/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.984252142
Short name T893
Test name
Test status
Simulation time 2050415209 ps
CPU time 5.78 seconds
Started May 23 01:38:38 PM PDT 24
Finished May 23 01:38:45 PM PDT 24
Peak memory 201716 kb
Host smart-08964a65-a0ca-4023-a1b2-7888d114a618
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984252142 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_rw
.984252142
Directory /workspace/8.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.895902128
Short name T838
Test name
Test status
Simulation time 2069964550 ps
CPU time 1.12 seconds
Started May 23 01:38:40 PM PDT 24
Finished May 23 01:38:42 PM PDT 24
Peak memory 201584 kb
Host smart-9ad745e9-c87d-45a7-83cc-40a508344375
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895902128 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_test
.895902128
Directory /workspace/8.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.404596573
Short name T870
Test name
Test status
Simulation time 5657213514 ps
CPU time 20.11 seconds
Started May 23 01:38:38 PM PDT 24
Finished May 23 01:38:59 PM PDT 24
Peak memory 201980 kb
Host smart-6274a453-7a15-4d53-ae28-6774c000effa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404596573 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
sysrst_ctrl_same_csr_outstanding.404596573
Directory /workspace/8.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.246224159
Short name T820
Test name
Test status
Simulation time 22235710224 ps
CPU time 60.93 seconds
Started May 23 01:38:42 PM PDT 24
Finished May 23 01:39:44 PM PDT 24
Peak memory 202000 kb
Host smart-757b8be7-846a-4029-898d-616f8f636d29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246224159 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ct
rl_tl_intg_err.246224159
Directory /workspace/8.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.1343302783
Short name T817
Test name
Test status
Simulation time 2113275166 ps
CPU time 2.41 seconds
Started May 23 01:38:40 PM PDT 24
Finished May 23 01:38:44 PM PDT 24
Peak memory 201656 kb
Host smart-1efaa1bf-ee46-42f2-8850-0009ff2318eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343302783 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_mem_rw_with_rand_reset.1343302783
Directory /workspace/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.1562083919
Short name T324
Test name
Test status
Simulation time 2042942427 ps
CPU time 5.71 seconds
Started May 23 01:38:40 PM PDT 24
Finished May 23 01:38:47 PM PDT 24
Peak memory 201772 kb
Host smart-752a86f1-b152-4878-93b6-dd891265d713
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562083919 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_r
w.1562083919
Directory /workspace/9.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.3605289185
Short name T802
Test name
Test status
Simulation time 2027961632 ps
CPU time 1.92 seconds
Started May 23 01:38:39 PM PDT 24
Finished May 23 01:38:42 PM PDT 24
Peak memory 201584 kb
Host smart-f7c8f0d8-38cd-4b62-ba58-cae83f0a5cd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605289185 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_tes
t.3605289185
Directory /workspace/9.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.2503519537
Short name T889
Test name
Test status
Simulation time 7457783523 ps
CPU time 13.4 seconds
Started May 23 01:38:38 PM PDT 24
Finished May 23 01:38:52 PM PDT 24
Peak memory 201988 kb
Host smart-2dc4341a-a480-47f1-8088-a804890d89ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503519537 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9
.sysrst_ctrl_same_csr_outstanding.2503519537
Directory /workspace/9.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.2899028010
Short name T281
Test name
Test status
Simulation time 2053253661 ps
CPU time 6.55 seconds
Started May 23 01:38:38 PM PDT 24
Finished May 23 01:38:45 PM PDT 24
Peak memory 201872 kb
Host smart-08c88b33-96ba-4246-bdce-92917a070643
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899028010 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_error
s.2899028010
Directory /workspace/9.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.2499364680
Short name T339
Test name
Test status
Simulation time 22236094304 ps
CPU time 46.58 seconds
Started May 23 01:38:42 PM PDT 24
Finished May 23 01:39:29 PM PDT 24
Peak memory 202024 kb
Host smart-96feb689-6a59-444c-9117-c2be24ace8d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499364680 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_tl_intg_err.2499364680
Directory /workspace/9.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_alert_test.202789939
Short name T692
Test name
Test status
Simulation time 2025536787 ps
CPU time 1.99 seconds
Started May 23 12:53:51 PM PDT 24
Finished May 23 12:53:54 PM PDT 24
Peak memory 202004 kb
Host smart-4216554b-1d09-4ef4-a145-6f8827c157b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202789939 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_test
.202789939
Directory /workspace/0.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.1243603070
Short name T487
Test name
Test status
Simulation time 3545433120 ps
CPU time 2.46 seconds
Started May 23 12:53:49 PM PDT 24
Finished May 23 12:53:53 PM PDT 24
Peak memory 202172 kb
Host smart-b07a1192-b1a6-4289-b2f3-fc74103fb058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243603070 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.1243603070
Directory /workspace/0.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect.2480193891
Short name T266
Test name
Test status
Simulation time 66881840361 ps
CPU time 171 seconds
Started May 23 12:53:49 PM PDT 24
Finished May 23 12:56:42 PM PDT 24
Peak memory 202300 kb
Host smart-6b10d767-be2e-44c9-8b01-1b7fff08d4f2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480193891 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_combo_detect.2480193891
Directory /workspace/0.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.1760465939
Short name T202
Test name
Test status
Simulation time 2209298513 ps
CPU time 2.09 seconds
Started May 23 12:53:34 PM PDT 24
Finished May 23 12:53:39 PM PDT 24
Peak memory 202104 kb
Host smart-eeac65ea-a748-4107-bd91-0e4f9a71c0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760465939 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.1760465939
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.223465322
Short name T246
Test name
Test status
Simulation time 2351047571 ps
CPU time 2.04 seconds
Started May 23 12:53:33 PM PDT 24
Finished May 23 12:53:38 PM PDT 24
Peak memory 202000 kb
Host smart-e1697e82-33b4-4be2-9a08-e39bc33601e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223465322 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_
cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_det
ect_ec_rst_with_pre_cond.223465322
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.1089420435
Short name T611
Test name
Test status
Simulation time 4218389258 ps
CPU time 11.8 seconds
Started May 23 12:53:49 PM PDT 24
Finished May 23 12:54:03 PM PDT 24
Peak memory 202016 kb
Host smart-212932ab-1b69-45b6-bb14-91be98ad313a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089420435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_ec_pwr_on_rst.1089420435
Directory /workspace/0.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_edge_detect.3924803555
Short name T241
Test name
Test status
Simulation time 3053495480 ps
CPU time 2.4 seconds
Started May 23 12:53:53 PM PDT 24
Finished May 23 12:53:57 PM PDT 24
Peak memory 201968 kb
Host smart-53e73029-e158-4560-96bf-44c03c7cb120
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924803555 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctr
l_edge_detect.3924803555
Directory /workspace/0.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.1603116887
Short name T625
Test name
Test status
Simulation time 2612198101 ps
CPU time 4.99 seconds
Started May 23 12:53:48 PM PDT 24
Finished May 23 12:53:55 PM PDT 24
Peak memory 202032 kb
Host smart-5da6fa21-a996-4e77-b4b3-de6ff3b50d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603116887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.1603116887
Directory /workspace/0.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.3871769181
Short name T569
Test name
Test status
Simulation time 2462930301 ps
CPU time 2.4 seconds
Started May 23 12:53:32 PM PDT 24
Finished May 23 12:53:37 PM PDT 24
Peak memory 202008 kb
Host smart-63c5ed59-dd80-4a9b-9c2a-63b92d5bb1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871769181 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.3871769181
Directory /workspace/0.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.4196372073
Short name T565
Test name
Test status
Simulation time 2185658810 ps
CPU time 5.72 seconds
Started May 23 12:53:50 PM PDT 24
Finished May 23 12:53:58 PM PDT 24
Peak memory 201992 kb
Host smart-07163b68-6ba5-4acb-9e44-5f8e95756790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196372073 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.4196372073
Directory /workspace/0.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.286543276
Short name T498
Test name
Test status
Simulation time 2515137501 ps
CPU time 6.83 seconds
Started May 23 12:53:47 PM PDT 24
Finished May 23 12:53:55 PM PDT 24
Peak memory 202020 kb
Host smart-91aa25c2-8826-4775-8aa5-5b55e1c3de3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286543276 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.286543276
Directory /workspace/0.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_sec_cm.3070524891
Short name T286
Test name
Test status
Simulation time 22062112784 ps
CPU time 15.22 seconds
Started May 23 12:53:58 PM PDT 24
Finished May 23 12:54:16 PM PDT 24
Peak memory 221672 kb
Host smart-9a1042cb-9ad2-4dbf-94ed-7bec31a5dc92
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070524891 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.3070524891
Directory /workspace/0.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_smoke.2928854945
Short name T426
Test name
Test status
Simulation time 2109177900 ps
CPU time 5.61 seconds
Started May 23 12:53:37 PM PDT 24
Finished May 23 12:53:45 PM PDT 24
Peak memory 201932 kb
Host smart-0984b5dc-356e-4151-aa10-91cd1924b389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928854945 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.2928854945
Directory /workspace/0.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all.2120787691
Short name T15
Test name
Test status
Simulation time 12868929508 ps
CPU time 34.08 seconds
Started May 23 12:53:48 PM PDT 24
Finished May 23 12:54:24 PM PDT 24
Peak memory 202004 kb
Host smart-9464a3e3-312b-4975-9e1b-17c7d5485e6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120787691 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_st
ress_all.2120787691
Directory /workspace/0.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.257903316
Short name T56
Test name
Test status
Simulation time 21723397142 ps
CPU time 26.52 seconds
Started May 23 12:53:50 PM PDT 24
Finished May 23 12:54:18 PM PDT 24
Peak memory 210596 kb
Host smart-91d3c0b8-b8af-4022-bc05-f719a8d6a2c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257903316 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all_with_rand_reset.257903316
Directory /workspace/0.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.2463595099
Short name T615
Test name
Test status
Simulation time 2849240019 ps
CPU time 1.26 seconds
Started May 23 12:53:49 PM PDT 24
Finished May 23 12:53:53 PM PDT 24
Peak memory 201960 kb
Host smart-8d4e85f4-3ab3-45d8-95a0-1dcd806bdefb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463595099 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_ultra_low_pwr.2463595099
Directory /workspace/0.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_alert_test.1076942577
Short name T520
Test name
Test status
Simulation time 2013426424 ps
CPU time 5.4 seconds
Started May 23 12:53:51 PM PDT 24
Finished May 23 12:53:58 PM PDT 24
Peak memory 201948 kb
Host smart-7fe4a273-138a-4798-abfd-250b66edc4e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076942577 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_tes
t.1076942577
Directory /workspace/1.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.2584414933
Short name T412
Test name
Test status
Simulation time 3232969589 ps
CPU time 2.65 seconds
Started May 23 12:53:58 PM PDT 24
Finished May 23 12:54:03 PM PDT 24
Peak memory 202084 kb
Host smart-dc9e6384-4e1d-4279-a834-17aadee018ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584414933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.2584414933
Directory /workspace/1.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect.2669022002
Short name T330
Test name
Test status
Simulation time 28565959672 ps
CPU time 72.66 seconds
Started May 23 12:53:51 PM PDT 24
Finished May 23 12:55:05 PM PDT 24
Peak memory 202188 kb
Host smart-8a465be0-764d-4032-89d0-afcbb6c1aa0a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669022002 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ct
rl_combo_detect.2669022002
Directory /workspace/1.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.567913749
Short name T196
Test name
Test status
Simulation time 2228370714 ps
CPU time 2.05 seconds
Started May 23 12:53:47 PM PDT 24
Finished May 23 12:53:51 PM PDT 24
Peak memory 202112 kb
Host smart-b8f7c73f-883d-45c5-ba3d-46790e18f556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567913749 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.567913749
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3599686312
Short name T689
Test name
Test status
Simulation time 2305021795 ps
CPU time 6.41 seconds
Started May 23 12:53:49 PM PDT 24
Finished May 23 12:53:58 PM PDT 24
Peak memory 202008 kb
Host smart-1af4d345-a8e2-49ec-833a-c0fd88ad147e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599686312 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.3599686312
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.3085820584
Short name T589
Test name
Test status
Simulation time 1035179365053 ps
CPU time 1362.74 seconds
Started May 23 12:53:51 PM PDT 24
Finished May 23 01:16:36 PM PDT 24
Peak memory 202116 kb
Host smart-2bffab3e-c57d-4aca-894b-5598cf0fdc8d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085820584 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ec_pwr_on_rst.3085820584
Directory /workspace/1.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_edge_detect.2267648585
Short name T6
Test name
Test status
Simulation time 5451181717 ps
CPU time 3.79 seconds
Started May 23 12:53:49 PM PDT 24
Finished May 23 12:53:54 PM PDT 24
Peak memory 202032 kb
Host smart-453c003a-a4c9-4512-9f4c-23df1fdbc66d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267648585 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctr
l_edge_detect.2267648585
Directory /workspace/1.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.3319077937
Short name T778
Test name
Test status
Simulation time 2636625138 ps
CPU time 2.15 seconds
Started May 23 12:53:46 PM PDT 24
Finished May 23 12:53:49 PM PDT 24
Peak memory 202132 kb
Host smart-374deebb-2faf-41c0-921d-e9103fa8388f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319077937 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.3319077937
Directory /workspace/1.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.2198818142
Short name T295
Test name
Test status
Simulation time 2493188539 ps
CPU time 1.38 seconds
Started May 23 12:53:51 PM PDT 24
Finished May 23 12:53:54 PM PDT 24
Peak memory 202036 kb
Host smart-5b218263-b5fd-4758-9dd0-3f04c11d9fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198818142 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.2198818142
Directory /workspace/1.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.1307354465
Short name T483
Test name
Test status
Simulation time 2250778720 ps
CPU time 6.66 seconds
Started May 23 12:53:48 PM PDT 24
Finished May 23 12:53:56 PM PDT 24
Peak memory 202012 kb
Host smart-1e13cf47-9f9a-4ef5-a3ef-e079fc5923fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307354465 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.1307354465
Directory /workspace/1.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.3800134997
Short name T522
Test name
Test status
Simulation time 2507754841 ps
CPU time 7.02 seconds
Started May 23 12:53:59 PM PDT 24
Finished May 23 12:54:08 PM PDT 24
Peak memory 201868 kb
Host smart-97d32367-063b-41d3-b37a-319ebab1b2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800134997 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.3800134997
Directory /workspace/1.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_smoke.1478328191
Short name T715
Test name
Test status
Simulation time 2129855603 ps
CPU time 2.07 seconds
Started May 23 12:53:53 PM PDT 24
Finished May 23 12:53:57 PM PDT 24
Peak memory 201804 kb
Host smart-dbb442f1-11f8-4a8b-b9ab-a484f7b56561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478328191 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.1478328191
Directory /workspace/1.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all.1695814605
Short name T251
Test name
Test status
Simulation time 51164735734 ps
CPU time 61.4 seconds
Started May 23 12:53:50 PM PDT 24
Finished May 23 12:54:53 PM PDT 24
Peak memory 202264 kb
Host smart-e8fea18c-b553-4925-b443-f5f7e59a09d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695814605 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_st
ress_all.1695814605
Directory /workspace/1.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.754297691
Short name T548
Test name
Test status
Simulation time 10864969255 ps
CPU time 4.7 seconds
Started May 23 12:53:47 PM PDT 24
Finished May 23 12:53:53 PM PDT 24
Peak memory 202032 kb
Host smart-79b1f66a-76ea-4a1e-9c12-94760f472c3a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754297691 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ct
rl_ultra_low_pwr.754297691
Directory /workspace/1.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_alert_test.2895026379
Short name T729
Test name
Test status
Simulation time 2028249891 ps
CPU time 2.03 seconds
Started May 23 12:54:41 PM PDT 24
Finished May 23 12:54:45 PM PDT 24
Peak memory 201956 kb
Host smart-7a489525-7e16-4715-974e-e86532a77e40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895026379 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_te
st.2895026379
Directory /workspace/10.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.3401823096
Short name T481
Test name
Test status
Simulation time 3287557156 ps
CPU time 2.86 seconds
Started May 23 12:54:40 PM PDT 24
Finished May 23 12:54:44 PM PDT 24
Peak memory 202084 kb
Host smart-21f633f7-32b4-4076-8515-1de2bb78fd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401823096 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.3
401823096
Directory /workspace/10.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect.1112807298
Short name T292
Test name
Test status
Simulation time 150901251617 ps
CPU time 84.47 seconds
Started May 23 12:54:39 PM PDT 24
Finished May 23 12:56:05 PM PDT 24
Peak memory 202304 kb
Host smart-f6a3cf8f-be40-4f55-af61-b96197a57431
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112807298 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_c
trl_combo_detect.1112807298
Directory /workspace/10.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.507700842
Short name T671
Test name
Test status
Simulation time 117703718251 ps
CPU time 300.1 seconds
Started May 23 12:54:41 PM PDT 24
Finished May 23 12:59:43 PM PDT 24
Peak memory 202264 kb
Host smart-e707469b-34fb-4097-bc10-be6faab76390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507700842 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect_wi
th_pre_cond.507700842
Directory /workspace/10.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.288984858
Short name T697
Test name
Test status
Simulation time 4348938804 ps
CPU time 11.5 seconds
Started May 23 12:54:44 PM PDT 24
Finished May 23 12:54:56 PM PDT 24
Peak memory 201984 kb
Host smart-bb9f35f3-e3e8-48a5-acc0-152bf3d790f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288984858 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_c
trl_ec_pwr_on_rst.288984858
Directory /workspace/10.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_edge_detect.4253139576
Short name T500
Test name
Test status
Simulation time 3486601449 ps
CPU time 2.11 seconds
Started May 23 12:54:40 PM PDT 24
Finished May 23 12:54:44 PM PDT 24
Peak memory 201988 kb
Host smart-4ccd16e0-ef9f-4e9c-8b0b-06f3c1a583a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253139576 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ct
rl_edge_detect.4253139576
Directory /workspace/10.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.141510838
Short name T730
Test name
Test status
Simulation time 2636314122 ps
CPU time 2.5 seconds
Started May 23 12:54:42 PM PDT 24
Finished May 23 12:54:46 PM PDT 24
Peak memory 202016 kb
Host smart-3aee55b5-cae9-460e-8d54-e80c6030c9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141510838 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.141510838
Directory /workspace/10.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.1937296198
Short name T538
Test name
Test status
Simulation time 2511162828 ps
CPU time 1.49 seconds
Started May 23 12:54:39 PM PDT 24
Finished May 23 12:54:41 PM PDT 24
Peak memory 202112 kb
Host smart-10774d77-680d-4a28-a3c5-fab8aeb0edf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937296198 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.1937296198
Directory /workspace/10.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.979900776
Short name T780
Test name
Test status
Simulation time 2208354445 ps
CPU time 6.51 seconds
Started May 23 12:54:41 PM PDT 24
Finished May 23 12:54:49 PM PDT 24
Peak memory 202084 kb
Host smart-c4a638ed-d6c0-4a63-9f4c-7271001649d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979900776 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.979900776
Directory /workspace/10.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.1211675666
Short name T639
Test name
Test status
Simulation time 2510399914 ps
CPU time 7.56 seconds
Started May 23 12:54:40 PM PDT 24
Finished May 23 12:54:50 PM PDT 24
Peak memory 202016 kb
Host smart-5c8c84fb-4c79-41b7-854b-eb99d22a6f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211675666 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.1211675666
Directory /workspace/10.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_smoke.3377305417
Short name T648
Test name
Test status
Simulation time 2118872039 ps
CPU time 3.14 seconds
Started May 23 12:54:40 PM PDT 24
Finished May 23 12:54:45 PM PDT 24
Peak memory 201864 kb
Host smart-4f9753e8-e958-4f51-8416-a7d239e71c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377305417 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_smoke.3377305417
Directory /workspace/10.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all.1775232945
Short name T790
Test name
Test status
Simulation time 12358579873 ps
CPU time 10.94 seconds
Started May 23 12:54:42 PM PDT 24
Finished May 23 12:54:54 PM PDT 24
Peak memory 201956 kb
Host smart-ff77d596-1297-48ee-b471-88947161f3c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775232945 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_s
tress_all.1775232945
Directory /workspace/10.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.1419468239
Short name T305
Test name
Test status
Simulation time 24435933632 ps
CPU time 11.05 seconds
Started May 23 12:54:39 PM PDT 24
Finished May 23 12:54:52 PM PDT 24
Peak memory 202404 kb
Host smart-f89c3175-e224-498c-b07b-f5b951d60dc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419468239 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all_with_rand_reset.1419468239
Directory /workspace/10.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.158279068
Short name T546
Test name
Test status
Simulation time 2129129662043 ps
CPU time 17.52 seconds
Started May 23 12:54:39 PM PDT 24
Finished May 23 12:54:59 PM PDT 24
Peak memory 202072 kb
Host smart-7a04981b-b9d9-4daf-b685-8e702bd69038
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158279068 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_c
trl_ultra_low_pwr.158279068
Directory /workspace/10.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_alert_test.2467165435
Short name T670
Test name
Test status
Simulation time 2042712033 ps
CPU time 1.92 seconds
Started May 23 12:54:54 PM PDT 24
Finished May 23 12:54:57 PM PDT 24
Peak memory 202100 kb
Host smart-2576c8fc-384c-4d5c-ace4-3dc0b06deb5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467165435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_te
st.2467165435
Directory /workspace/11.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.3255532727
Short name T582
Test name
Test status
Simulation time 3104652744 ps
CPU time 4.68 seconds
Started May 23 12:54:41 PM PDT 24
Finished May 23 12:54:48 PM PDT 24
Peak memory 202148 kb
Host smart-1f304197-82a1-43e0-b35f-b52d4b5c2684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255532727 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.3
255532727
Directory /workspace/11.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect.1361457613
Short name T255
Test name
Test status
Simulation time 66860621601 ps
CPU time 87.57 seconds
Started May 23 12:54:53 PM PDT 24
Finished May 23 12:56:22 PM PDT 24
Peak memory 202348 kb
Host smart-877604d2-7296-4b65-85e1-ffd89116a2c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361457613 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_c
trl_combo_detect.1361457613
Directory /workspace/11.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.546021055
Short name T170
Test name
Test status
Simulation time 58870729538 ps
CPU time 152.53 seconds
Started May 23 12:54:53 PM PDT 24
Finished May 23 12:57:27 PM PDT 24
Peak memory 202272 kb
Host smart-7720faf8-b1b2-46ca-84cb-74237d65b20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546021055 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect_wi
th_pre_cond.546021055
Directory /workspace/11.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.4199010887
Short name T149
Test name
Test status
Simulation time 4766608264 ps
CPU time 6.52 seconds
Started May 23 12:54:41 PM PDT 24
Finished May 23 12:54:49 PM PDT 24
Peak memory 201984 kb
Host smart-8688e759-4740-42cc-90e1-eef0d94314c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199010887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_ec_pwr_on_rst.4199010887
Directory /workspace/11.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.1878606266
Short name T180
Test name
Test status
Simulation time 2671957299 ps
CPU time 1.56 seconds
Started May 23 12:54:40 PM PDT 24
Finished May 23 12:54:43 PM PDT 24
Peak memory 201992 kb
Host smart-d20eb5b7-fa1c-41a5-94d5-33b43620356b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878606266 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.1878606266
Directory /workspace/11.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.955933004
Short name T108
Test name
Test status
Simulation time 2467114307 ps
CPU time 6.69 seconds
Started May 23 12:54:41 PM PDT 24
Finished May 23 12:54:50 PM PDT 24
Peak memory 202020 kb
Host smart-1640fc70-2151-444a-99ac-e66f9c55f324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955933004 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.955933004
Directory /workspace/11.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.1272852059
Short name T396
Test name
Test status
Simulation time 2111455903 ps
CPU time 1.96 seconds
Started May 23 12:54:39 PM PDT 24
Finished May 23 12:54:42 PM PDT 24
Peak memory 201892 kb
Host smart-93596dac-2b49-4451-aca4-e67f7ee900d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272852059 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.1272852059
Directory /workspace/11.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.2465587328
Short name T737
Test name
Test status
Simulation time 2532991026 ps
CPU time 2.47 seconds
Started May 23 12:54:40 PM PDT 24
Finished May 23 12:54:44 PM PDT 24
Peak memory 202132 kb
Host smart-c0d7a49b-42d0-4d94-ba78-58c813333254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465587328 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.2465587328
Directory /workspace/11.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_smoke.549881719
Short name T619
Test name
Test status
Simulation time 2115613688 ps
CPU time 3.88 seconds
Started May 23 12:54:41 PM PDT 24
Finished May 23 12:54:46 PM PDT 24
Peak memory 201944 kb
Host smart-f43c4d47-c8c1-4176-bdce-e33a44d31e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549881719 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.549881719
Directory /workspace/11.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all.3296181314
Short name T462
Test name
Test status
Simulation time 8417558036 ps
CPU time 2.33 seconds
Started May 23 12:54:51 PM PDT 24
Finished May 23 12:54:55 PM PDT 24
Peak memory 202028 kb
Host smart-97fefdd8-486e-4820-8191-e272c5d984ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296181314 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_s
tress_all.3296181314
Directory /workspace/11.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.1959415128
Short name T562
Test name
Test status
Simulation time 4594448730 ps
CPU time 7.43 seconds
Started May 23 12:54:53 PM PDT 24
Finished May 23 12:55:02 PM PDT 24
Peak memory 201956 kb
Host smart-a1bc3826-3a60-4d8a-9d1c-c1ef5922c4f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959415128 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_ultra_low_pwr.1959415128
Directory /workspace/11.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_alert_test.3089263762
Short name T472
Test name
Test status
Simulation time 2009357125 ps
CPU time 6.02 seconds
Started May 23 12:54:56 PM PDT 24
Finished May 23 12:55:04 PM PDT 24
Peak memory 201928 kb
Host smart-b0837585-fb9c-4f9a-a944-c69dcf42efa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089263762 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_te
st.3089263762
Directory /workspace/12.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.4259231748
Short name T289
Test name
Test status
Simulation time 3355007109 ps
CPU time 2.98 seconds
Started May 23 12:54:52 PM PDT 24
Finished May 23 12:54:57 PM PDT 24
Peak memory 202156 kb
Host smart-321806c5-c1e8-4bce-8265-2daafba8a694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259231748 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.4
259231748
Directory /workspace/12.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.1364915259
Short name T622
Test name
Test status
Simulation time 4410196329 ps
CPU time 3.36 seconds
Started May 23 12:54:52 PM PDT 24
Finished May 23 12:54:57 PM PDT 24
Peak memory 201992 kb
Host smart-ed92601e-38fe-4d74-9b86-2a49a419a2a0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364915259 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ec_pwr_on_rst.1364915259
Directory /workspace/12.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_edge_detect.1925259149
Short name T209
Test name
Test status
Simulation time 4034777658 ps
CPU time 2.71 seconds
Started May 23 12:54:52 PM PDT 24
Finished May 23 12:54:56 PM PDT 24
Peak memory 202096 kb
Host smart-5c308461-9d24-4d84-9264-5ee8587edd79
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925259149 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ct
rl_edge_detect.1925259149
Directory /workspace/12.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.3583126999
Short name T382
Test name
Test status
Simulation time 2616772159 ps
CPU time 4.21 seconds
Started May 23 12:54:53 PM PDT 24
Finished May 23 12:54:59 PM PDT 24
Peak memory 202020 kb
Host smart-f2211e1f-3e82-41ea-97d5-bd88f53472ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583126999 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.3583126999
Directory /workspace/12.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.2653259195
Short name T436
Test name
Test status
Simulation time 2475578136 ps
CPU time 2.37 seconds
Started May 23 12:54:53 PM PDT 24
Finished May 23 12:54:57 PM PDT 24
Peak memory 202040 kb
Host smart-547977ff-067a-417d-91c6-14ede38186dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653259195 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.2653259195
Directory /workspace/12.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.639040584
Short name T559
Test name
Test status
Simulation time 2061944186 ps
CPU time 2.07 seconds
Started May 23 12:54:53 PM PDT 24
Finished May 23 12:54:57 PM PDT 24
Peak memory 201900 kb
Host smart-986d68bf-ce04-458e-9f0d-365386f76c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639040584 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.639040584
Directory /workspace/12.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.2611790649
Short name T297
Test name
Test status
Simulation time 2515452052 ps
CPU time 4.13 seconds
Started May 23 12:54:52 PM PDT 24
Finished May 23 12:54:57 PM PDT 24
Peak memory 202132 kb
Host smart-a783148b-2ea0-4355-8f1f-915d33ae8a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611790649 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.2611790649
Directory /workspace/12.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_smoke.1655003923
Short name T636
Test name
Test status
Simulation time 2111961212 ps
CPU time 5.98 seconds
Started May 23 12:54:55 PM PDT 24
Finished May 23 12:55:02 PM PDT 24
Peak memory 202044 kb
Host smart-f28d206f-675d-47ed-91a0-528a6dfa55c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655003923 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.1655003923
Directory /workspace/12.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all.862220717
Short name T258
Test name
Test status
Simulation time 83349006683 ps
CPU time 221.09 seconds
Started May 23 12:54:53 PM PDT 24
Finished May 23 12:58:36 PM PDT 24
Peak memory 202272 kb
Host smart-4dc4d811-bfb9-4857-9148-227dd6e0cee5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862220717 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_st
ress_all.862220717
Directory /workspace/12.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.2060296054
Short name T118
Test name
Test status
Simulation time 29099127773 ps
CPU time 33.55 seconds
Started May 23 12:54:55 PM PDT 24
Finished May 23 12:55:30 PM PDT 24
Peak memory 210700 kb
Host smart-297c8748-ced8-4bfc-93fb-7c99795ae66c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060296054 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all_with_rand_reset.2060296054
Directory /workspace/12.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.3104765297
Short name T573
Test name
Test status
Simulation time 5077472075 ps
CPU time 6.8 seconds
Started May 23 12:54:53 PM PDT 24
Finished May 23 12:55:01 PM PDT 24
Peak memory 202104 kb
Host smart-cfd83925-3304-4dc4-a866-bd784d579c33
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104765297 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ultra_low_pwr.3104765297
Directory /workspace/12.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_alert_test.2838588349
Short name T577
Test name
Test status
Simulation time 2017835540 ps
CPU time 2.95 seconds
Started May 23 12:54:53 PM PDT 24
Finished May 23 12:54:58 PM PDT 24
Peak memory 202048 kb
Host smart-254d3114-36e6-423f-9ad3-5b71de20a6c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838588349 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_te
st.2838588349
Directory /workspace/13.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.3097686244
Short name T51
Test name
Test status
Simulation time 3466116173 ps
CPU time 5.21 seconds
Started May 23 12:54:56 PM PDT 24
Finished May 23 12:55:02 PM PDT 24
Peak memory 202224 kb
Host smart-3f5becd3-fe2e-4c62-af52-5185682a5912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097686244 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.3
097686244
Directory /workspace/13.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect.2966757523
Short name T30
Test name
Test status
Simulation time 37104382634 ps
CPU time 17.99 seconds
Started May 23 12:54:51 PM PDT 24
Finished May 23 12:55:10 PM PDT 24
Peak memory 202328 kb
Host smart-6447a7ef-5849-4d0a-b790-0d78f833cbc0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966757523 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_c
trl_combo_detect.2966757523
Directory /workspace/13.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.3733309562
Short name T773
Test name
Test status
Simulation time 27589476040 ps
CPU time 37.72 seconds
Started May 23 12:54:53 PM PDT 24
Finished May 23 12:55:32 PM PDT 24
Peak memory 202340 kb
Host smart-69483310-423c-435c-bdb7-bdac20e058a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733309562 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect_w
ith_pre_cond.3733309562
Directory /workspace/13.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.1491433883
Short name T410
Test name
Test status
Simulation time 4418202052 ps
CPU time 7.72 seconds
Started May 23 12:54:56 PM PDT 24
Finished May 23 12:55:05 PM PDT 24
Peak memory 201984 kb
Host smart-60026cfb-277e-4913-8db3-588515607615
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491433883 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ec_pwr_on_rst.1491433883
Directory /workspace/13.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_edge_detect.1101203979
Short name T213
Test name
Test status
Simulation time 4775546258 ps
CPU time 7.3 seconds
Started May 23 12:54:53 PM PDT 24
Finished May 23 12:55:02 PM PDT 24
Peak memory 202108 kb
Host smart-fb81e0e5-546c-4452-9e80-c79cac9ac251
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101203979 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ct
rl_edge_detect.1101203979
Directory /workspace/13.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.1383503288
Short name T664
Test name
Test status
Simulation time 2620639126 ps
CPU time 4.05 seconds
Started May 23 12:54:54 PM PDT 24
Finished May 23 12:54:59 PM PDT 24
Peak memory 201956 kb
Host smart-73de9686-e451-4057-b10e-c82ae479cbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383503288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.1383503288
Directory /workspace/13.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.2035065691
Short name T224
Test name
Test status
Simulation time 2469138680 ps
CPU time 2.21 seconds
Started May 23 12:54:53 PM PDT 24
Finished May 23 12:54:57 PM PDT 24
Peak memory 202108 kb
Host smart-86c9908f-50d4-40cc-bf20-9507d1c63974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035065691 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.2035065691
Directory /workspace/13.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.222323993
Short name T544
Test name
Test status
Simulation time 2183698186 ps
CPU time 0.89 seconds
Started May 23 12:54:52 PM PDT 24
Finished May 23 12:54:54 PM PDT 24
Peak memory 202064 kb
Host smart-fdde7f7c-a0cc-4059-adbe-860b5dfb986b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222323993 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.222323993
Directory /workspace/13.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.3144429500
Short name T469
Test name
Test status
Simulation time 2509573517 ps
CPU time 7.26 seconds
Started May 23 12:54:52 PM PDT 24
Finished May 23 12:55:01 PM PDT 24
Peak memory 202104 kb
Host smart-f4b82bac-8509-4f2a-b117-a954283e210f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144429500 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.3144429500
Directory /workspace/13.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_smoke.4265125779
Short name T158
Test name
Test status
Simulation time 2126507663 ps
CPU time 1.92 seconds
Started May 23 12:54:53 PM PDT 24
Finished May 23 12:54:57 PM PDT 24
Peak memory 201960 kb
Host smart-891729d4-6d57-4488-a169-40cc0509d346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265125779 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.4265125779
Directory /workspace/13.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all.1595125833
Short name T560
Test name
Test status
Simulation time 13339976319 ps
CPU time 8.34 seconds
Started May 23 12:54:52 PM PDT 24
Finished May 23 12:55:02 PM PDT 24
Peak memory 201952 kb
Host smart-1a795348-3cc3-494b-aa9b-5c50dcb37597
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595125833 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_s
tress_all.1595125833
Directory /workspace/13.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.3240656181
Short name T370
Test name
Test status
Simulation time 1332063300262 ps
CPU time 117.64 seconds
Started May 23 12:54:54 PM PDT 24
Finished May 23 12:56:53 PM PDT 24
Peak memory 210616 kb
Host smart-d5cdc775-02f7-450d-91d3-1cbdcd6be0e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240656181 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all_with_rand_reset.3240656181
Directory /workspace/13.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.3919285443
Short name T231
Test name
Test status
Simulation time 6160755424 ps
CPU time 3.81 seconds
Started May 23 12:54:52 PM PDT 24
Finished May 23 12:54:57 PM PDT 24
Peak memory 202032 kb
Host smart-926b033a-ddff-47a2-998a-977b5551ddf5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919285443 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ultra_low_pwr.3919285443
Directory /workspace/13.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_alert_test.1948366924
Short name T463
Test name
Test status
Simulation time 2018289239 ps
CPU time 3.18 seconds
Started May 23 12:55:06 PM PDT 24
Finished May 23 12:55:11 PM PDT 24
Peak memory 201884 kb
Host smart-31c18a18-0e30-4675-bf27-226385c5cd1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948366924 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_te
st.1948366924
Directory /workspace/14.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.1114590703
Short name T647
Test name
Test status
Simulation time 3171483127 ps
CPU time 8.26 seconds
Started May 23 12:55:05 PM PDT 24
Finished May 23 12:55:15 PM PDT 24
Peak memory 202068 kb
Host smart-0a9d28d9-07e3-4509-a6a9-d82c1c6d62bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114590703 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.1
114590703
Directory /workspace/14.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.2998024274
Short name T252
Test name
Test status
Simulation time 84186416902 ps
CPU time 217.64 seconds
Started May 23 12:55:04 PM PDT 24
Finished May 23 12:58:44 PM PDT 24
Peak memory 202304 kb
Host smart-e9e5624f-2250-43e1-bb08-fe03e82b72af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998024274 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect_w
ith_pre_cond.2998024274
Directory /workspace/14.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.4117533546
Short name T761
Test name
Test status
Simulation time 4634913039 ps
CPU time 12.44 seconds
Started May 23 12:54:55 PM PDT 24
Finished May 23 12:55:09 PM PDT 24
Peak memory 202092 kb
Host smart-9b421f97-6bb7-4872-a6ae-3ab56ab07803
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117533546 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ec_pwr_on_rst.4117533546
Directory /workspace/14.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_edge_detect.2702014853
Short name T188
Test name
Test status
Simulation time 2643825954 ps
CPU time 1.57 seconds
Started May 23 12:55:06 PM PDT 24
Finished May 23 12:55:09 PM PDT 24
Peak memory 202120 kb
Host smart-32bd788b-727c-454d-9367-6ee064f1aa4a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702014853 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ct
rl_edge_detect.2702014853
Directory /workspace/14.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.4018239113
Short name T455
Test name
Test status
Simulation time 2617021643 ps
CPU time 3.8 seconds
Started May 23 12:54:56 PM PDT 24
Finished May 23 12:55:01 PM PDT 24
Peak memory 202120 kb
Host smart-0f573bce-99b4-497b-8740-002753415f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018239113 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.4018239113
Directory /workspace/14.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.3646150212
Short name T61
Test name
Test status
Simulation time 2491723294 ps
CPU time 8.29 seconds
Started May 23 12:54:56 PM PDT 24
Finished May 23 12:55:05 PM PDT 24
Peak memory 202116 kb
Host smart-260734e0-f305-4a5a-b25f-4aa7f5ab3890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646150212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.3646150212
Directory /workspace/14.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.34879439
Short name T551
Test name
Test status
Simulation time 2229730862 ps
CPU time 6.16 seconds
Started May 23 12:54:53 PM PDT 24
Finished May 23 12:55:01 PM PDT 24
Peak memory 202084 kb
Host smart-912e5782-3af1-4116-a651-c8488e697eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34879439 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.34879439
Directory /workspace/14.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_smoke.3481858659
Short name T796
Test name
Test status
Simulation time 2120953442 ps
CPU time 3.2 seconds
Started May 23 12:54:55 PM PDT 24
Finished May 23 12:54:59 PM PDT 24
Peak memory 201956 kb
Host smart-aee67191-a263-4fd3-903d-bd542ec6f88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481858659 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.3481858659
Directory /workspace/14.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all.3917834422
Short name T549
Test name
Test status
Simulation time 7280190383 ps
CPU time 5.38 seconds
Started May 23 12:55:07 PM PDT 24
Finished May 23 12:55:15 PM PDT 24
Peak memory 202032 kb
Host smart-990d35dd-6096-46a5-81cf-a008ead26939
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917834422 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_s
tress_all.3917834422
Directory /workspace/14.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.1333217839
Short name T304
Test name
Test status
Simulation time 19630514695 ps
CPU time 49.3 seconds
Started May 23 12:55:06 PM PDT 24
Finished May 23 12:55:58 PM PDT 24
Peak memory 202324 kb
Host smart-504b38ca-ff1d-4757-a9ca-c9d953ce06ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333217839 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all_with_rand_reset.1333217839
Directory /workspace/14.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.2372532635
Short name T683
Test name
Test status
Simulation time 3165055715 ps
CPU time 8.53 seconds
Started May 23 12:55:05 PM PDT 24
Finished May 23 12:55:16 PM PDT 24
Peak memory 202056 kb
Host smart-7fe7fb89-e9de-482e-a3d1-af7fb8c4bfdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372532635 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.2
372532635
Directory /workspace/15.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect.3658501681
Short name T107
Test name
Test status
Simulation time 111967945717 ps
CPU time 308.2 seconds
Started May 23 12:55:10 PM PDT 24
Finished May 23 01:00:19 PM PDT 24
Peak memory 202256 kb
Host smart-20fcd741-4ed6-4a73-ae68-ad3d457d0186
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658501681 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_c
trl_combo_detect.3658501681
Directory /workspace/15.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.796929021
Short name T349
Test name
Test status
Simulation time 53816497262 ps
CPU time 15.41 seconds
Started May 23 12:55:05 PM PDT 24
Finished May 23 12:55:22 PM PDT 24
Peak memory 202360 kb
Host smart-3cdc0254-43c7-4f17-a284-b6d51c620038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796929021 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect_wi
th_pre_cond.796929021
Directory /workspace/15.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.554939650
Short name T393
Test name
Test status
Simulation time 3763106646 ps
CPU time 3.19 seconds
Started May 23 12:55:04 PM PDT 24
Finished May 23 12:55:09 PM PDT 24
Peak memory 202056 kb
Host smart-fd022543-9a89-430b-a65e-4a5c4f2ea505
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554939650 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_c
trl_ec_pwr_on_rst.554939650
Directory /workspace/15.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_edge_detect.1565441542
Short name T166
Test name
Test status
Simulation time 5582147829 ps
CPU time 9.04 seconds
Started May 23 12:55:05 PM PDT 24
Finished May 23 12:55:16 PM PDT 24
Peak memory 202008 kb
Host smart-5b60678c-22eb-4286-a891-9a9fd045a7fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565441542 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ct
rl_edge_detect.1565441542
Directory /workspace/15.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.2223920504
Short name T509
Test name
Test status
Simulation time 2618545912 ps
CPU time 2.7 seconds
Started May 23 12:55:08 PM PDT 24
Finished May 23 12:55:13 PM PDT 24
Peak memory 202000 kb
Host smart-d3cfaae1-cd4f-41be-9495-a75f39435640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223920504 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.2223920504
Directory /workspace/15.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.1539624738
Short name T226
Test name
Test status
Simulation time 2458922273 ps
CPU time 2.94 seconds
Started May 23 12:55:07 PM PDT 24
Finished May 23 12:55:12 PM PDT 24
Peak memory 202028 kb
Host smart-d32fab19-7364-4536-a1d8-77c5ed121114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539624738 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.1539624738
Directory /workspace/15.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_smoke.3420470377
Short name T184
Test name
Test status
Simulation time 2116231334 ps
CPU time 3.45 seconds
Started May 23 12:55:10 PM PDT 24
Finished May 23 12:55:15 PM PDT 24
Peak memory 201964 kb
Host smart-e55fa3c9-9f13-4b7e-991b-5b54bb834924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420470377 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.3420470377
Directory /workspace/15.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all.964186605
Short name T725
Test name
Test status
Simulation time 15337779474 ps
CPU time 2.79 seconds
Started May 23 12:55:07 PM PDT 24
Finished May 23 12:55:13 PM PDT 24
Peak memory 201972 kb
Host smart-fed0c9be-f05b-4887-8621-35e8160aae55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964186605 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_st
ress_all.964186605
Directory /workspace/15.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.1402126621
Short name T380
Test name
Test status
Simulation time 7660535900 ps
CPU time 7.05 seconds
Started May 23 12:55:04 PM PDT 24
Finished May 23 12:55:12 PM PDT 24
Peak memory 202088 kb
Host smart-c93083f0-5ccc-46f6-afad-6a701c8fcba2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402126621 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ultra_low_pwr.1402126621
Directory /workspace/15.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_alert_test.541731204
Short name T235
Test name
Test status
Simulation time 2033150472 ps
CPU time 2.16 seconds
Started May 23 12:55:06 PM PDT 24
Finished May 23 12:55:10 PM PDT 24
Peak memory 202040 kb
Host smart-6a24ec57-cff6-47dd-9f99-45b3925d834c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541731204 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_tes
t.541731204
Directory /workspace/16.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.612998150
Short name T52
Test name
Test status
Simulation time 3139821432 ps
CPU time 2.52 seconds
Started May 23 12:55:04 PM PDT 24
Finished May 23 12:55:08 PM PDT 24
Peak memory 202148 kb
Host smart-a3590a45-92e8-4668-9ad7-2ee6dc4481db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612998150 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.612998150
Directory /workspace/16.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect.2069176422
Short name T189
Test name
Test status
Simulation time 33999447267 ps
CPU time 42.44 seconds
Started May 23 12:55:07 PM PDT 24
Finished May 23 12:55:52 PM PDT 24
Peak memory 202184 kb
Host smart-2947cfe8-3e82-44c6-9201-ce0c5b44ffb8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069176422 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_c
trl_combo_detect.2069176422
Directory /workspace/16.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.2127591041
Short name T529
Test name
Test status
Simulation time 21832627408 ps
CPU time 56.16 seconds
Started May 23 12:55:06 PM PDT 24
Finished May 23 12:56:04 PM PDT 24
Peak memory 202452 kb
Host smart-01301212-40e4-461e-b5b5-428682d55817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127591041 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect_w
ith_pre_cond.2127591041
Directory /workspace/16.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.1091801431
Short name T518
Test name
Test status
Simulation time 4813407507 ps
CPU time 13.41 seconds
Started May 23 12:55:07 PM PDT 24
Finished May 23 12:55:23 PM PDT 24
Peak memory 201992 kb
Host smart-b64e41d4-a012-4be4-aeac-69c56c91e6d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091801431 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ec_pwr_on_rst.1091801431
Directory /workspace/16.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_edge_detect.3722975862
Short name T782
Test name
Test status
Simulation time 3962369219 ps
CPU time 9.12 seconds
Started May 23 12:55:07 PM PDT 24
Finished May 23 12:55:18 PM PDT 24
Peak memory 202108 kb
Host smart-40d9eb82-d361-43ca-8cff-36a1f0713a4b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722975862 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ct
rl_edge_detect.3722975862
Directory /workspace/16.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.3279335264
Short name T422
Test name
Test status
Simulation time 2610272772 ps
CPU time 6.81 seconds
Started May 23 12:55:05 PM PDT 24
Finished May 23 12:55:14 PM PDT 24
Peak memory 202004 kb
Host smart-3dee0061-9be4-4110-9d87-100ce877d401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279335264 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.3279335264
Directory /workspace/16.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.311190783
Short name T22
Test name
Test status
Simulation time 2478143406 ps
CPU time 4.02 seconds
Started May 23 12:55:07 PM PDT 24
Finished May 23 12:55:13 PM PDT 24
Peak memory 202036 kb
Host smart-2e4640da-b0ac-4da6-bf64-24890daf572c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311190783 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.311190783
Directory /workspace/16.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.3034555334
Short name T676
Test name
Test status
Simulation time 2096149326 ps
CPU time 1.52 seconds
Started May 23 12:55:04 PM PDT 24
Finished May 23 12:55:08 PM PDT 24
Peak memory 201876 kb
Host smart-d36850f1-60a7-4bf7-bbaf-b0533e656752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034555334 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.3034555334
Directory /workspace/16.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.1914017158
Short name T526
Test name
Test status
Simulation time 2538489665 ps
CPU time 1.89 seconds
Started May 23 12:55:06 PM PDT 24
Finished May 23 12:55:09 PM PDT 24
Peak memory 202048 kb
Host smart-34a83a39-81ed-47df-859a-b4f02ec96bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914017158 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.1914017158
Directory /workspace/16.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_smoke.2054189294
Short name T788
Test name
Test status
Simulation time 2125088664 ps
CPU time 1.88 seconds
Started May 23 12:55:09 PM PDT 24
Finished May 23 12:55:13 PM PDT 24
Peak memory 201968 kb
Host smart-3fca2efe-c1ba-4e14-ab23-2b00c2fcb35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054189294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.2054189294
Directory /workspace/16.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all.2617608511
Short name T220
Test name
Test status
Simulation time 11729413386 ps
CPU time 4.83 seconds
Started May 23 12:55:04 PM PDT 24
Finished May 23 12:55:10 PM PDT 24
Peak memory 202012 kb
Host smart-39c4f4ed-97cf-4541-819a-78c2c12eca9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617608511 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_s
tress_all.2617608511
Directory /workspace/16.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.1599898517
Short name T94
Test name
Test status
Simulation time 1273866084838 ps
CPU time 332.03 seconds
Started May 23 12:55:05 PM PDT 24
Finished May 23 01:00:39 PM PDT 24
Peak memory 210756 kb
Host smart-ae0eb7f0-5308-4080-a4c7-b164868efca9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599898517 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all_with_rand_reset.1599898517
Directory /workspace/16.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.3739969094
Short name T211
Test name
Test status
Simulation time 2676328804 ps
CPU time 1.91 seconds
Started May 23 12:55:06 PM PDT 24
Finished May 23 12:55:10 PM PDT 24
Peak memory 201992 kb
Host smart-4bda1de9-92fe-4c7b-89c5-f7605be9c4c6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739969094 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ultra_low_pwr.3739969094
Directory /workspace/16.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_alert_test.2026081267
Short name T578
Test name
Test status
Simulation time 2070478358 ps
CPU time 1.35 seconds
Started May 23 12:55:21 PM PDT 24
Finished May 23 12:55:24 PM PDT 24
Peak memory 202052 kb
Host smart-d06de1e6-4ace-42b6-adfe-5b8d246b0d15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026081267 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_te
st.2026081267
Directory /workspace/17.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.1808575616
Short name T456
Test name
Test status
Simulation time 2895224299 ps
CPU time 8.23 seconds
Started May 23 12:55:19 PM PDT 24
Finished May 23 12:55:29 PM PDT 24
Peak memory 202044 kb
Host smart-523ed6b5-bc4c-42ac-90cc-6f6ae0510701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808575616 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.1
808575616
Directory /workspace/17.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.1694310795
Short name T600
Test name
Test status
Simulation time 91813353866 ps
CPU time 43.5 seconds
Started May 23 12:55:18 PM PDT 24
Finished May 23 12:56:03 PM PDT 24
Peak memory 202336 kb
Host smart-568e5d07-afdc-48a2-a1d3-53cd0c648a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694310795 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect_w
ith_pre_cond.1694310795
Directory /workspace/17.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.3651621199
Short name T603
Test name
Test status
Simulation time 5404973691 ps
CPU time 1.41 seconds
Started May 23 12:55:19 PM PDT 24
Finished May 23 12:55:22 PM PDT 24
Peak memory 202076 kb
Host smart-456998de-c751-494f-9986-52ed4cdb9032
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651621199 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_ec_pwr_on_rst.3651621199
Directory /workspace/17.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_edge_detect.3461574615
Short name T218
Test name
Test status
Simulation time 4100256673 ps
CPU time 2.39 seconds
Started May 23 12:55:19 PM PDT 24
Finished May 23 12:55:23 PM PDT 24
Peak memory 201956 kb
Host smart-d3c73ace-bf2b-41c4-8825-f9c670cc54f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461574615 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ct
rl_edge_detect.3461574615
Directory /workspace/17.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.1711499986
Short name T623
Test name
Test status
Simulation time 2610098723 ps
CPU time 7.78 seconds
Started May 23 12:55:18 PM PDT 24
Finished May 23 12:55:27 PM PDT 24
Peak memory 202132 kb
Host smart-527b0272-e900-41d4-8d7e-4121ddaa4b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711499986 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.1711499986
Directory /workspace/17.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.3336697531
Short name T429
Test name
Test status
Simulation time 2492831702 ps
CPU time 1.99 seconds
Started May 23 12:55:07 PM PDT 24
Finished May 23 12:55:12 PM PDT 24
Peak memory 202016 kb
Host smart-a69b7a11-5038-4eb3-9e4e-7650f38705ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336697531 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.3336697531
Directory /workspace/17.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.111422888
Short name T667
Test name
Test status
Simulation time 2035196560 ps
CPU time 1.76 seconds
Started May 23 12:55:03 PM PDT 24
Finished May 23 12:55:06 PM PDT 24
Peak memory 201992 kb
Host smart-68772330-45b3-4520-aa84-26de45f43018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111422888 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.111422888
Directory /workspace/17.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.2300961735
Short name T555
Test name
Test status
Simulation time 2510061776 ps
CPU time 5.28 seconds
Started May 23 12:55:18 PM PDT 24
Finished May 23 12:55:24 PM PDT 24
Peak memory 202032 kb
Host smart-9b963e62-d8fb-41a5-acab-b25543e3dd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300961735 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.2300961735
Directory /workspace/17.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_smoke.698539437
Short name T540
Test name
Test status
Simulation time 2114273497 ps
CPU time 6.07 seconds
Started May 23 12:55:04 PM PDT 24
Finished May 23 12:55:12 PM PDT 24
Peak memory 201852 kb
Host smart-1b8517fc-0ebe-4e90-99d6-382c003bde29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698539437 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.698539437
Directory /workspace/17.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all.67767533
Short name T146
Test name
Test status
Simulation time 12043925141 ps
CPU time 31.89 seconds
Started May 23 12:55:19 PM PDT 24
Finished May 23 12:55:53 PM PDT 24
Peak memory 202064 kb
Host smart-00445def-72f4-4335-b695-3d7d0c4f2b9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67767533 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_str
ess_all.67767533
Directory /workspace/17.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.2559314393
Short name T114
Test name
Test status
Simulation time 71022271259 ps
CPU time 80.16 seconds
Started May 23 12:55:20 PM PDT 24
Finished May 23 12:56:42 PM PDT 24
Peak memory 218664 kb
Host smart-022d3df3-39f1-493f-9fb3-b9c676fdc969
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559314393 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_stress_all_with_rand_reset.2559314393
Directory /workspace/17.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_alert_test.2008730696
Short name T515
Test name
Test status
Simulation time 2010231384 ps
CPU time 5.84 seconds
Started May 23 12:55:18 PM PDT 24
Finished May 23 12:55:26 PM PDT 24
Peak memory 201960 kb
Host smart-0ca36e26-2734-4b34-8c4d-12b27419740f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008730696 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_te
st.2008730696
Directory /workspace/18.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.2497888316
Short name T556
Test name
Test status
Simulation time 314275099931 ps
CPU time 862.73 seconds
Started May 23 12:55:20 PM PDT 24
Finished May 23 01:09:45 PM PDT 24
Peak memory 202088 kb
Host smart-0427fe00-bddd-4e05-96c6-67d71e9f3be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497888316 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.2
497888316
Directory /workspace/18.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect.3869058883
Short name T331
Test name
Test status
Simulation time 57376330353 ps
CPU time 35.73 seconds
Started May 23 12:55:19 PM PDT 24
Finished May 23 12:55:56 PM PDT 24
Peak memory 202216 kb
Host smart-88c42703-9c44-4be6-8db4-57446dfdd68b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869058883 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_combo_detect.3869058883
Directory /workspace/18.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.489965586
Short name T557
Test name
Test status
Simulation time 5545266199 ps
CPU time 1.34 seconds
Started May 23 12:55:20 PM PDT 24
Finished May 23 12:55:23 PM PDT 24
Peak memory 202052 kb
Host smart-42e92729-44fa-4e7c-95d7-e7f75962ae3d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489965586 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_ec_pwr_on_rst.489965586
Directory /workspace/18.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.566833779
Short name T398
Test name
Test status
Simulation time 2617254745 ps
CPU time 4.09 seconds
Started May 23 12:55:18 PM PDT 24
Finished May 23 12:55:24 PM PDT 24
Peak memory 202040 kb
Host smart-041a1531-44c0-4f2c-9d7c-c5d1726d79be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566833779 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.566833779
Directory /workspace/18.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.2242887374
Short name T792
Test name
Test status
Simulation time 2464709698 ps
CPU time 2.18 seconds
Started May 23 12:55:19 PM PDT 24
Finished May 23 12:55:23 PM PDT 24
Peak memory 202096 kb
Host smart-a3dd7b02-a71a-4cc3-9a5e-0761f6e49a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242887374 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.2242887374
Directory /workspace/18.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.1182581146
Short name T513
Test name
Test status
Simulation time 2019534911 ps
CPU time 3.14 seconds
Started May 23 12:55:20 PM PDT 24
Finished May 23 12:55:25 PM PDT 24
Peak memory 201816 kb
Host smart-1b1e3c55-caa3-4db6-87b1-5462814945c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182581146 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.1182581146
Directory /workspace/18.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.2512023212
Short name T586
Test name
Test status
Simulation time 2512441617 ps
CPU time 7.36 seconds
Started May 23 12:55:19 PM PDT 24
Finished May 23 12:55:28 PM PDT 24
Peak memory 202084 kb
Host smart-652f4862-1b87-4f9e-827f-05588afe83f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512023212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.2512023212
Directory /workspace/18.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_smoke.3199956562
Short name T465
Test name
Test status
Simulation time 2114446142 ps
CPU time 6.25 seconds
Started May 23 12:55:19 PM PDT 24
Finished May 23 12:55:27 PM PDT 24
Peak memory 201952 kb
Host smart-79ea31a9-5113-43a7-aa22-2cc4de4e517e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199956562 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.3199956562
Directory /workspace/18.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all.3073584280
Short name T206
Test name
Test status
Simulation time 18044042282 ps
CPU time 8.39 seconds
Started May 23 12:55:21 PM PDT 24
Finished May 23 12:55:31 PM PDT 24
Peak memory 202020 kb
Host smart-8ad87281-897e-4f3f-8cbd-ab89835bfb5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073584280 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_s
tress_all.3073584280
Directory /workspace/18.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.4060103883
Short name T95
Test name
Test status
Simulation time 94188891771 ps
CPU time 62.38 seconds
Started May 23 12:55:18 PM PDT 24
Finished May 23 12:56:22 PM PDT 24
Peak memory 210568 kb
Host smart-9ecc9d8c-9931-4147-a090-1c80ebb0d78c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060103883 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all_with_rand_reset.4060103883
Directory /workspace/18.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.486360606
Short name T767
Test name
Test status
Simulation time 3844879473 ps
CPU time 3.39 seconds
Started May 23 12:55:19 PM PDT 24
Finished May 23 12:55:24 PM PDT 24
Peak memory 202008 kb
Host smart-a6251c25-8fc2-4df8-aded-b2d277220093
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486360606 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_ultra_low_pwr.486360606
Directory /workspace/18.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_alert_test.1095582373
Short name T680
Test name
Test status
Simulation time 2028405354 ps
CPU time 1.92 seconds
Started May 23 12:55:20 PM PDT 24
Finished May 23 12:55:24 PM PDT 24
Peak memory 201892 kb
Host smart-9edb3aab-b258-4c07-9324-e0d896649684
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095582373 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_te
st.1095582373
Directory /workspace/19.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.3066326630
Short name T290
Test name
Test status
Simulation time 3237648185 ps
CPU time 4.53 seconds
Started May 23 12:55:21 PM PDT 24
Finished May 23 12:55:27 PM PDT 24
Peak memory 202100 kb
Host smart-d9a9d13b-a377-42a3-881d-8eb3cf49d44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066326630 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.3
066326630
Directory /workspace/19.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.1102657209
Short name T666
Test name
Test status
Simulation time 54646474466 ps
CPU time 133.09 seconds
Started May 23 12:55:18 PM PDT 24
Finished May 23 12:57:32 PM PDT 24
Peak memory 202392 kb
Host smart-ee4d14a5-452e-4506-b51c-4a6c8f7f9e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102657209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect_w
ith_pre_cond.1102657209
Directory /workspace/19.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.1578404108
Short name T530
Test name
Test status
Simulation time 4049190311 ps
CPU time 5.53 seconds
Started May 23 12:55:20 PM PDT 24
Finished May 23 12:55:27 PM PDT 24
Peak memory 202096 kb
Host smart-0a85b012-52a4-4553-9347-4f3128ad113c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578404108 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_ec_pwr_on_rst.1578404108
Directory /workspace/19.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_edge_detect.2534159352
Short name T222
Test name
Test status
Simulation time 3976945349 ps
CPU time 2.48 seconds
Started May 23 12:55:18 PM PDT 24
Finished May 23 12:55:23 PM PDT 24
Peak memory 202100 kb
Host smart-dde4f6fb-79e8-4dd9-a4be-53b2e245696b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534159352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ct
rl_edge_detect.2534159352
Directory /workspace/19.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.2054753484
Short name T388
Test name
Test status
Simulation time 2613611816 ps
CPU time 7.27 seconds
Started May 23 12:55:21 PM PDT 24
Finished May 23 12:55:30 PM PDT 24
Peak memory 202112 kb
Host smart-453679cc-91b1-4e24-af48-e681de2bf852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054753484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.2054753484
Directory /workspace/19.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.3322233141
Short name T407
Test name
Test status
Simulation time 2453915450 ps
CPU time 6.57 seconds
Started May 23 12:55:21 PM PDT 24
Finished May 23 12:55:29 PM PDT 24
Peak memory 202096 kb
Host smart-b6c23e91-d8c4-4000-a07a-6b4878bfd614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322233141 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.3322233141
Directory /workspace/19.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.1018552219
Short name T105
Test name
Test status
Simulation time 2236811851 ps
CPU time 3.37 seconds
Started May 23 12:55:21 PM PDT 24
Finished May 23 12:55:25 PM PDT 24
Peak memory 201980 kb
Host smart-c661a145-600c-4082-b2c5-8c1c9f6edb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018552219 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.1018552219
Directory /workspace/19.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.12705123
Short name T403
Test name
Test status
Simulation time 2577381614 ps
CPU time 1.51 seconds
Started May 23 12:55:20 PM PDT 24
Finished May 23 12:55:23 PM PDT 24
Peak memory 202204 kb
Host smart-6e621c2c-4ac6-4e24-9926-2266f332ca5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12705123 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.12705123
Directory /workspace/19.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_smoke.2885756325
Short name T497
Test name
Test status
Simulation time 2145070111 ps
CPU time 1.41 seconds
Started May 23 12:55:21 PM PDT 24
Finished May 23 12:55:24 PM PDT 24
Peak memory 201876 kb
Host smart-bdd35517-1016-4f38-af78-f2424657d2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885756325 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.2885756325
Directory /workspace/19.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.495423791
Short name T54
Test name
Test status
Simulation time 3770636726 ps
CPU time 2.52 seconds
Started May 23 12:55:19 PM PDT 24
Finished May 23 12:55:24 PM PDT 24
Peak memory 202104 kb
Host smart-d62adea4-e1bb-42f4-8a60-8f1e0fc33d64
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495423791 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_ultra_low_pwr.495423791
Directory /workspace/19.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_alert_test.2881561104
Short name T402
Test name
Test status
Simulation time 2010703872 ps
CPU time 5.91 seconds
Started May 23 12:54:00 PM PDT 24
Finished May 23 12:54:08 PM PDT 24
Peak memory 202044 kb
Host smart-792c9b33-2942-4af1-ba09-70f50f303092
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881561104 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_tes
t.2881561104
Directory /workspace/2.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.2520097429
Short name T745
Test name
Test status
Simulation time 3313157555 ps
CPU time 5.19 seconds
Started May 23 12:54:01 PM PDT 24
Finished May 23 12:54:08 PM PDT 24
Peak memory 202236 kb
Host smart-d6f730bc-48e9-4d2b-97fe-b2d57934526e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520097429 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.2520097429
Directory /workspace/2.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect.4289077145
Short name T264
Test name
Test status
Simulation time 129287506167 ps
CPU time 159.25 seconds
Started May 23 12:53:59 PM PDT 24
Finished May 23 12:56:40 PM PDT 24
Peak memory 202280 kb
Host smart-f07d7c32-0961-4137-898c-e90df8692ab0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289077145 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ct
rl_combo_detect.4289077145
Directory /workspace/2.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.372735723
Short name T594
Test name
Test status
Simulation time 2214346013 ps
CPU time 6.45 seconds
Started May 23 12:53:51 PM PDT 24
Finished May 23 12:53:59 PM PDT 24
Peak memory 202112 kb
Host smart-5e198701-8881-449f-840f-f017213edaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372735723 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.372735723
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.4230641508
Short name T171
Test name
Test status
Simulation time 2551004282 ps
CPU time 4.77 seconds
Started May 23 12:53:58 PM PDT 24
Finished May 23 12:54:05 PM PDT 24
Peak memory 202036 kb
Host smart-f04d50e4-db8f-4016-96f7-285223c4d993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230641508 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.4230641508
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_edge_detect.1925049651
Short name T38
Test name
Test status
Simulation time 3663000754 ps
CPU time 1.41 seconds
Started May 23 12:53:58 PM PDT 24
Finished May 23 12:54:02 PM PDT 24
Peak memory 202028 kb
Host smart-7c8c79b3-a87b-4bdb-81f7-74228ac7f53d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925049651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctr
l_edge_detect.1925049651
Directory /workspace/2.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.3085469651
Short name T467
Test name
Test status
Simulation time 2610079184 ps
CPU time 7.04 seconds
Started May 23 12:54:06 PM PDT 24
Finished May 23 12:54:15 PM PDT 24
Peak memory 201996 kb
Host smart-8bd63277-e59a-481d-ab8d-a34182fd7aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085469651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.3085469651
Directory /workspace/2.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.5621399
Short name T656
Test name
Test status
Simulation time 2460354903 ps
CPU time 4.09 seconds
Started May 23 12:53:49 PM PDT 24
Finished May 23 12:53:55 PM PDT 24
Peak memory 202060 kb
Host smart-cd8c4833-7626-458a-91df-11a801f93b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5621399 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.5621399
Directory /workspace/2.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.1144021968
Short name T781
Test name
Test status
Simulation time 2276840545 ps
CPU time 1.44 seconds
Started May 23 12:53:49 PM PDT 24
Finished May 23 12:53:52 PM PDT 24
Peak memory 201972 kb
Host smart-dc225289-e1fa-4824-b550-d7d84d751300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144021968 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.1144021968
Directory /workspace/2.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.3007967507
Short name T510
Test name
Test status
Simulation time 2510060770 ps
CPU time 7.41 seconds
Started May 23 12:53:58 PM PDT 24
Finished May 23 12:54:08 PM PDT 24
Peak memory 202036 kb
Host smart-06169243-bce1-4e4a-959c-72911686700f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007967507 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.3007967507
Directory /workspace/2.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_sec_cm.389933248
Short name T193
Test name
Test status
Simulation time 22075070834 ps
CPU time 13.86 seconds
Started May 23 12:53:58 PM PDT 24
Finished May 23 12:54:13 PM PDT 24
Peak memory 221740 kb
Host smart-f758cd37-04c5-4707-839f-ce58fb4d4cbf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389933248 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.389933248
Directory /workspace/2.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_smoke.3273927800
Short name T458
Test name
Test status
Simulation time 2113395231 ps
CPU time 6.41 seconds
Started May 23 12:53:50 PM PDT 24
Finished May 23 12:53:58 PM PDT 24
Peak memory 201952 kb
Host smart-b9a57bb4-4c82-4cec-9de1-8acadd08e8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273927800 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.3273927800
Directory /workspace/2.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all.2385786596
Short name T216
Test name
Test status
Simulation time 10517482972 ps
CPU time 23.98 seconds
Started May 23 12:53:58 PM PDT 24
Finished May 23 12:54:23 PM PDT 24
Peak memory 202080 kb
Host smart-2be50a3f-84a3-4fdb-9187-3940f85eba4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385786596 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_st
ress_all.2385786596
Directory /workspace/2.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.2046230329
Short name T741
Test name
Test status
Simulation time 59226083139 ps
CPU time 37.07 seconds
Started May 23 12:54:00 PM PDT 24
Finished May 23 12:54:39 PM PDT 24
Peak memory 210704 kb
Host smart-d13a9293-76fd-4217-a434-29c7c4edbb2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046230329 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all_with_rand_reset.2046230329
Directory /workspace/2.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.2991089628
Short name T566
Test name
Test status
Simulation time 10657848920 ps
CPU time 4.34 seconds
Started May 23 12:53:59 PM PDT 24
Finished May 23 12:54:05 PM PDT 24
Peak memory 202120 kb
Host smart-ec8973da-611f-4209-a7cb-36b91cddf39b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991089628 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_ultra_low_pwr.2991089628
Directory /workspace/2.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_alert_test.1535463842
Short name T591
Test name
Test status
Simulation time 2019122674 ps
CPU time 2.73 seconds
Started May 23 12:55:34 PM PDT 24
Finished May 23 12:55:39 PM PDT 24
Peak memory 201928 kb
Host smart-4e6d8f42-575d-4c87-a53d-162ab439be3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535463842 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_te
st.1535463842
Directory /workspace/20.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.4025543101
Short name T597
Test name
Test status
Simulation time 47153978042 ps
CPU time 121.51 seconds
Started May 23 12:55:36 PM PDT 24
Finished May 23 12:57:39 PM PDT 24
Peak memory 202100 kb
Host smart-6f58a56c-074c-4226-ac01-a994c05d1d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025543101 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.4
025543101
Directory /workspace/20.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect.2372600002
Short name T100
Test name
Test status
Simulation time 43752333966 ps
CPU time 61.18 seconds
Started May 23 12:55:33 PM PDT 24
Finished May 23 12:56:36 PM PDT 24
Peak memory 202284 kb
Host smart-60fe6c61-24cc-450d-905e-e59c03d48b90
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372600002 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_c
trl_combo_detect.2372600002
Directory /workspace/20.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.3562821985
Short name T44
Test name
Test status
Simulation time 67883660117 ps
CPU time 46.57 seconds
Started May 23 12:55:31 PM PDT 24
Finished May 23 12:56:19 PM PDT 24
Peak memory 202324 kb
Host smart-68d9c3be-2345-4def-a557-713fa2ee1dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562821985 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect_w
ith_pre_cond.3562821985
Directory /workspace/20.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.2474834558
Short name T419
Test name
Test status
Simulation time 942912799791 ps
CPU time 462.42 seconds
Started May 23 12:55:37 PM PDT 24
Finished May 23 01:03:21 PM PDT 24
Peak memory 202152 kb
Host smart-b0b3ba21-97f0-478e-8606-f7c068611b56
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474834558 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ec_pwr_on_rst.2474834558
Directory /workspace/20.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_edge_detect.2248051443
Short name T492
Test name
Test status
Simulation time 4499200629 ps
CPU time 5.71 seconds
Started May 23 12:55:36 PM PDT 24
Finished May 23 12:55:44 PM PDT 24
Peak memory 202028 kb
Host smart-0150da95-5307-413f-af2f-8b0778df6b4b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248051443 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ct
rl_edge_detect.2248051443
Directory /workspace/20.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.14566669
Short name T488
Test name
Test status
Simulation time 2612830393 ps
CPU time 3.72 seconds
Started May 23 12:55:19 PM PDT 24
Finished May 23 12:55:25 PM PDT 24
Peak memory 201960 kb
Host smart-0f782320-4676-4d4e-ae6b-b360ba2abeb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14566669 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.14566669
Directory /workspace/20.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.3576298689
Short name T585
Test name
Test status
Simulation time 2491761458 ps
CPU time 2.65 seconds
Started May 23 12:55:18 PM PDT 24
Finished May 23 12:55:22 PM PDT 24
Peak memory 202004 kb
Host smart-3cea6153-b38b-48ba-b475-cd367b4604a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576298689 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.3576298689
Directory /workspace/20.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.2716282070
Short name T447
Test name
Test status
Simulation time 2242962700 ps
CPU time 5.99 seconds
Started May 23 12:55:21 PM PDT 24
Finished May 23 12:55:28 PM PDT 24
Peak memory 202072 kb
Host smart-3de0f407-7fa4-4039-bc49-93118abd6ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716282070 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.2716282070
Directory /workspace/20.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.4239093468
Short name T651
Test name
Test status
Simulation time 2509111144 ps
CPU time 6.99 seconds
Started May 23 12:55:19 PM PDT 24
Finished May 23 12:55:27 PM PDT 24
Peak memory 202024 kb
Host smart-c4ac7aed-072b-4771-9d6f-99f7118e20dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239093468 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.4239093468
Directory /workspace/20.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_smoke.462021608
Short name T640
Test name
Test status
Simulation time 2110539029 ps
CPU time 5.63 seconds
Started May 23 12:55:18 PM PDT 24
Finished May 23 12:55:26 PM PDT 24
Peak memory 201940 kb
Host smart-ec519ccb-4138-493e-8535-fa3bedc9300c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462021608 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.462021608
Directory /workspace/20.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all.4262972390
Short name T660
Test name
Test status
Simulation time 15062078354 ps
CPU time 36.62 seconds
Started May 23 12:55:33 PM PDT 24
Finished May 23 12:56:11 PM PDT 24
Peak memory 202032 kb
Host smart-7fd1fe83-2a4d-40f8-bc29-db79a85e7f83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262972390 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_s
tress_all.4262972390
Directory /workspace/20.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.1131675867
Short name T287
Test name
Test status
Simulation time 12128657708 ps
CPU time 33.17 seconds
Started May 23 12:55:33 PM PDT 24
Finished May 23 12:56:08 PM PDT 24
Peak memory 202500 kb
Host smart-0fc2affb-5d5f-4f2f-9361-cfe53562f42d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131675867 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all_with_rand_reset.1131675867
Directory /workspace/20.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_alert_test.2551836586
Short name T572
Test name
Test status
Simulation time 2020772203 ps
CPU time 3.43 seconds
Started May 23 12:55:39 PM PDT 24
Finished May 23 12:55:44 PM PDT 24
Peak memory 201948 kb
Host smart-b83d06c9-ce04-45c3-bbb4-02f8e09b2821
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551836586 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_te
st.2551836586
Directory /workspace/21.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.2968416870
Short name T494
Test name
Test status
Simulation time 3413768425 ps
CPU time 2.77 seconds
Started May 23 12:55:38 PM PDT 24
Finished May 23 12:55:42 PM PDT 24
Peak memory 202044 kb
Host smart-5acf50ca-9aac-4e5d-bf02-addf5372c15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968416870 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.2
968416870
Directory /workspace/21.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect.444984630
Short name T587
Test name
Test status
Simulation time 133994614893 ps
CPU time 56.66 seconds
Started May 23 12:55:34 PM PDT 24
Finished May 23 12:56:33 PM PDT 24
Peak memory 202212 kb
Host smart-501d4966-c8b2-4990-9ca1-11d9efa9c91f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444984630 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ct
rl_combo_detect.444984630
Directory /workspace/21.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.938852115
Short name T735
Test name
Test status
Simulation time 3034335189 ps
CPU time 2.6 seconds
Started May 23 12:55:39 PM PDT 24
Finished May 23 12:55:43 PM PDT 24
Peak memory 202100 kb
Host smart-0ba45d1d-c1bd-4ef7-89ff-eed5ea7df5c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938852115 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_c
trl_ec_pwr_on_rst.938852115
Directory /workspace/21.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_edge_detect.1252028727
Short name T169
Test name
Test status
Simulation time 4801564286 ps
CPU time 8.32 seconds
Started May 23 12:55:35 PM PDT 24
Finished May 23 12:55:45 PM PDT 24
Peak memory 202128 kb
Host smart-aa5a0b87-ae15-4a83-8a7b-b633b1ef4d15
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252028727 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ct
rl_edge_detect.1252028727
Directory /workspace/21.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.1755747237
Short name T477
Test name
Test status
Simulation time 2651052430 ps
CPU time 1.6 seconds
Started May 23 12:55:36 PM PDT 24
Finished May 23 12:55:40 PM PDT 24
Peak memory 202088 kb
Host smart-6caa8777-5d73-4b8e-84d2-026e60654427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755747237 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.1755747237
Directory /workspace/21.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.2864228571
Short name T181
Test name
Test status
Simulation time 2470140086 ps
CPU time 3.66 seconds
Started May 23 12:55:32 PM PDT 24
Finished May 23 12:55:37 PM PDT 24
Peak memory 201952 kb
Host smart-2cedc0fb-4b8f-4c01-874f-778c1100f2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864228571 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.2864228571
Directory /workspace/21.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.3364250860
Short name T568
Test name
Test status
Simulation time 2267603218 ps
CPU time 2.1 seconds
Started May 23 12:55:36 PM PDT 24
Finished May 23 12:55:40 PM PDT 24
Peak memory 202076 kb
Host smart-e8958554-4a9b-4fcc-bc31-994a2006f9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364250860 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.3364250860
Directory /workspace/21.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.2980281184
Short name T468
Test name
Test status
Simulation time 2513945751 ps
CPU time 5.65 seconds
Started May 23 12:55:33 PM PDT 24
Finished May 23 12:55:40 PM PDT 24
Peak memory 202108 kb
Host smart-c5a168bd-fbaf-4653-b3a9-e93e41a4bd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980281184 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.2980281184
Directory /workspace/21.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_smoke.3618790855
Short name T136
Test name
Test status
Simulation time 2115945585 ps
CPU time 3.27 seconds
Started May 23 12:55:36 PM PDT 24
Finished May 23 12:55:41 PM PDT 24
Peak memory 201864 kb
Host smart-a3b6ec54-adb5-46a0-b86a-e560e571b0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618790855 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.3618790855
Directory /workspace/21.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all.824903566
Short name T742
Test name
Test status
Simulation time 9065277698 ps
CPU time 6.58 seconds
Started May 23 12:55:37 PM PDT 24
Finished May 23 12:55:45 PM PDT 24
Peak memory 201956 kb
Host smart-866d2963-c453-4270-9e12-c42065c9cd60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824903566 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_st
ress_all.824903566
Directory /workspace/21.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_alert_test.184483173
Short name T609
Test name
Test status
Simulation time 2023148953 ps
CPU time 3.22 seconds
Started May 23 12:55:35 PM PDT 24
Finished May 23 12:55:40 PM PDT 24
Peak memory 201940 kb
Host smart-6de1cb82-12bb-46e6-af02-c1b88bc059d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184483173 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_tes
t.184483173
Directory /workspace/22.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.2113111711
Short name T618
Test name
Test status
Simulation time 3236733730 ps
CPU time 9.42 seconds
Started May 23 12:55:35 PM PDT 24
Finished May 23 12:55:46 PM PDT 24
Peak memory 202184 kb
Host smart-c7395166-f432-4e98-a150-d3b790471352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113111711 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.2
113111711
Directory /workspace/22.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.2489565330
Short name T243
Test name
Test status
Simulation time 37602077307 ps
CPU time 47.72 seconds
Started May 23 12:55:34 PM PDT 24
Finished May 23 12:56:24 PM PDT 24
Peak memory 202384 kb
Host smart-23b47550-83db-46a1-ba93-dfcbdcf8a321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489565330 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect_w
ith_pre_cond.2489565330
Directory /workspace/22.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.988721777
Short name T377
Test name
Test status
Simulation time 4584086291 ps
CPU time 11.96 seconds
Started May 23 12:55:38 PM PDT 24
Finished May 23 12:55:52 PM PDT 24
Peak memory 202096 kb
Host smart-0b3a66aa-3d21-4bf3-a3b8-b558f66cfd19
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988721777 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_c
trl_ec_pwr_on_rst.988721777
Directory /workspace/22.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_edge_detect.2743672681
Short name T217
Test name
Test status
Simulation time 4418147837 ps
CPU time 6.01 seconds
Started May 23 12:55:37 PM PDT 24
Finished May 23 12:55:45 PM PDT 24
Peak memory 202120 kb
Host smart-1b5bf515-94ec-44ef-bf30-444aacd05313
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743672681 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ct
rl_edge_detect.2743672681
Directory /workspace/22.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.3594293149
Short name T785
Test name
Test status
Simulation time 2626976247 ps
CPU time 2.31 seconds
Started May 23 12:55:36 PM PDT 24
Finished May 23 12:55:40 PM PDT 24
Peak memory 202100 kb
Host smart-b1ba142d-3abb-4cfa-a1ed-a3daa32e0521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594293149 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.3594293149
Directory /workspace/22.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.2300445668
Short name T684
Test name
Test status
Simulation time 2460749161 ps
CPU time 3.93 seconds
Started May 23 12:55:37 PM PDT 24
Finished May 23 12:55:42 PM PDT 24
Peak memory 202020 kb
Host smart-dec4c303-cfc6-4b8b-b735-cdda8eda2f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300445668 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.2300445668
Directory /workspace/22.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.1973274573
Short name T628
Test name
Test status
Simulation time 2190439538 ps
CPU time 1.8 seconds
Started May 23 12:55:37 PM PDT 24
Finished May 23 12:55:41 PM PDT 24
Peak memory 201932 kb
Host smart-c14a8e49-b398-4ecf-8f74-41f5ac78937f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973274573 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.1973274573
Directory /workspace/22.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.4203047120
Short name T525
Test name
Test status
Simulation time 2515651003 ps
CPU time 5.62 seconds
Started May 23 12:55:36 PM PDT 24
Finished May 23 12:55:43 PM PDT 24
Peak memory 202012 kb
Host smart-f93bd63e-f4df-4688-a2c8-2ca41a14a944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203047120 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.4203047120
Directory /workspace/22.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_smoke.2130114317
Short name T674
Test name
Test status
Simulation time 2114113760 ps
CPU time 6.18 seconds
Started May 23 12:55:36 PM PDT 24
Finished May 23 12:55:44 PM PDT 24
Peak memory 201956 kb
Host smart-04b696e5-d1cd-42cc-a2e8-7b6361d973a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130114317 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.2130114317
Directory /workspace/22.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all.283199999
Short name T86
Test name
Test status
Simulation time 10350769477 ps
CPU time 13.75 seconds
Started May 23 12:55:39 PM PDT 24
Finished May 23 12:55:54 PM PDT 24
Peak memory 202016 kb
Host smart-4466dfc9-b64d-4e56-96e3-96578d7490af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283199999 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_st
ress_all.283199999
Directory /workspace/22.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.1717206664
Short name T134
Test name
Test status
Simulation time 12364873172 ps
CPU time 5.55 seconds
Started May 23 12:55:36 PM PDT 24
Finished May 23 12:55:43 PM PDT 24
Peak memory 202120 kb
Host smart-02e5cc9d-ec45-4b5f-ba19-d601429419af
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717206664 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ultra_low_pwr.1717206664
Directory /workspace/22.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_alert_test.3003870921
Short name T613
Test name
Test status
Simulation time 2031422235 ps
CPU time 1.84 seconds
Started May 23 12:55:37 PM PDT 24
Finished May 23 12:55:41 PM PDT 24
Peak memory 202104 kb
Host smart-4fbd6912-a363-4386-bdb5-7149057fd65d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003870921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_te
st.3003870921
Directory /workspace/23.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.2893053915
Short name T428
Test name
Test status
Simulation time 3351820777 ps
CPU time 3.22 seconds
Started May 23 12:55:37 PM PDT 24
Finished May 23 12:55:42 PM PDT 24
Peak memory 202156 kb
Host smart-9caec875-24d6-43bf-8d44-a8262ae757d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893053915 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.2
893053915
Directory /workspace/23.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect.196401408
Short name T229
Test name
Test status
Simulation time 132984340055 ps
CPU time 353.19 seconds
Started May 23 12:55:36 PM PDT 24
Finished May 23 01:01:31 PM PDT 24
Peak memory 202244 kb
Host smart-fb38cb5f-3cf2-4cb1-9d7d-b370d85dd8ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196401408 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ct
rl_combo_detect.196401408
Directory /workspace/23.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.1056230494
Short name T306
Test name
Test status
Simulation time 2457674215 ps
CPU time 2.13 seconds
Started May 23 12:55:36 PM PDT 24
Finished May 23 12:55:40 PM PDT 24
Peak memory 202008 kb
Host smart-be548f0d-61d6-4e58-a320-39c6091111fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056230494 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_
ctrl_ec_pwr_on_rst.1056230494
Directory /workspace/23.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_edge_detect.3243299141
Short name T210
Test name
Test status
Simulation time 3894468813 ps
CPU time 8.83 seconds
Started May 23 12:55:36 PM PDT 24
Finished May 23 12:55:47 PM PDT 24
Peak memory 202024 kb
Host smart-7d456cff-908e-457e-89bc-b15670d4ab33
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243299141 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ct
rl_edge_detect.3243299141
Directory /workspace/23.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.780238046
Short name T575
Test name
Test status
Simulation time 2613353535 ps
CPU time 7 seconds
Started May 23 12:55:36 PM PDT 24
Finished May 23 12:55:45 PM PDT 24
Peak memory 202088 kb
Host smart-e6483325-4047-472e-a768-4b681ae201c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780238046 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.780238046
Directory /workspace/23.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.1031353273
Short name T416
Test name
Test status
Simulation time 2466451393 ps
CPU time 6.94 seconds
Started May 23 12:55:34 PM PDT 24
Finished May 23 12:55:43 PM PDT 24
Peak memory 202116 kb
Host smart-367f05ad-aef4-448b-826d-2a5dc921b784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031353273 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.1031353273
Directory /workspace/23.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.1366046182
Short name T448
Test name
Test status
Simulation time 2054055463 ps
CPU time 5.4 seconds
Started May 23 12:55:36 PM PDT 24
Finished May 23 12:55:43 PM PDT 24
Peak memory 201880 kb
Host smart-841869bf-939a-4973-8192-f17c5126c79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366046182 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.1366046182
Directory /workspace/23.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.153579789
Short name T203
Test name
Test status
Simulation time 2520404096 ps
CPU time 4.15 seconds
Started May 23 12:55:38 PM PDT 24
Finished May 23 12:55:43 PM PDT 24
Peak memory 201996 kb
Host smart-eaaf3df6-0640-4208-a947-5932e4d1bbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153579789 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.153579789
Directory /workspace/23.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_smoke.1003299915
Short name T199
Test name
Test status
Simulation time 2125148550 ps
CPU time 2.01 seconds
Started May 23 12:55:35 PM PDT 24
Finished May 23 12:55:39 PM PDT 24
Peak memory 201948 kb
Host smart-7de70a60-ca0d-452b-9681-e98beb98686d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003299915 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.1003299915
Directory /workspace/23.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all.4199308306
Short name T84
Test name
Test status
Simulation time 14484579868 ps
CPU time 17.63 seconds
Started May 23 12:55:33 PM PDT 24
Finished May 23 12:55:52 PM PDT 24
Peak memory 202000 kb
Host smart-3122f351-737f-4f52-b7b9-5f35666b67f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199308306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_s
tress_all.4199308306
Directory /workspace/23.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.268052385
Short name T288
Test name
Test status
Simulation time 24700414459 ps
CPU time 66.04 seconds
Started May 23 12:55:36 PM PDT 24
Finished May 23 12:56:44 PM PDT 24
Peak memory 210656 kb
Host smart-02e24439-dca9-4db9-a8a2-78cc8baf2a59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268052385 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all_with_rand_reset.268052385
Directory /workspace/23.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.3380498740
Short name T793
Test name
Test status
Simulation time 5959505291 ps
CPU time 8.05 seconds
Started May 23 12:55:34 PM PDT 24
Finished May 23 12:55:44 PM PDT 24
Peak memory 202016 kb
Host smart-194429c9-3cd6-45b8-ba13-78d02723037e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380498740 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_
ctrl_ultra_low_pwr.3380498740
Directory /workspace/23.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_alert_test.2704898450
Short name T392
Test name
Test status
Simulation time 2014312468 ps
CPU time 5.93 seconds
Started May 23 12:55:34 PM PDT 24
Finished May 23 12:55:41 PM PDT 24
Peak memory 201928 kb
Host smart-339eedd0-6eac-4699-9f09-365ad689ee5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704898450 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_te
st.2704898450
Directory /workspace/24.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.105932302
Short name T480
Test name
Test status
Simulation time 3619030152 ps
CPU time 2.89 seconds
Started May 23 12:55:36 PM PDT 24
Finished May 23 12:55:40 PM PDT 24
Peak memory 202100 kb
Host smart-bf232701-1cc3-49e0-89e1-89bca2d117bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105932302 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.105932302
Directory /workspace/24.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect.357302185
Short name T657
Test name
Test status
Simulation time 59563602111 ps
CPU time 39.74 seconds
Started May 23 12:55:37 PM PDT 24
Finished May 23 12:56:19 PM PDT 24
Peak memory 202172 kb
Host smart-b43b46b1-4253-4f10-a889-000b17082875
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357302185 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ct
rl_combo_detect.357302185
Directory /workspace/24.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.3835370335
Short name T247
Test name
Test status
Simulation time 118902567994 ps
CPU time 320.08 seconds
Started May 23 12:55:34 PM PDT 24
Finished May 23 01:00:55 PM PDT 24
Peak memory 202360 kb
Host smart-410ed6f8-6583-46b1-aa04-8797a8cf6099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835370335 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect_w
ith_pre_cond.3835370335
Directory /workspace/24.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.352649651
Short name T710
Test name
Test status
Simulation time 1313404764375 ps
CPU time 518.35 seconds
Started May 23 12:55:35 PM PDT 24
Finished May 23 01:04:15 PM PDT 24
Peak memory 201984 kb
Host smart-df9785e1-5a52-4860-8891-d2c2ec25cf7f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352649651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_c
trl_ec_pwr_on_rst.352649651
Directory /workspace/24.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_edge_detect.2105631275
Short name T1
Test name
Test status
Simulation time 2605769112 ps
CPU time 7.13 seconds
Started May 23 12:55:38 PM PDT 24
Finished May 23 12:55:47 PM PDT 24
Peak memory 202072 kb
Host smart-19d00937-2fde-4abe-bfe7-0c360e439fbf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105631275 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ct
rl_edge_detect.2105631275
Directory /workspace/24.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.1799846626
Short name T387
Test name
Test status
Simulation time 2624327062 ps
CPU time 2.45 seconds
Started May 23 12:55:34 PM PDT 24
Finished May 23 12:55:38 PM PDT 24
Peak memory 202096 kb
Host smart-6dc505cc-4194-4580-85f7-005ed6ed01b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799846626 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.1799846626
Directory /workspace/24.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.888873110
Short name T632
Test name
Test status
Simulation time 2480738706 ps
CPU time 3.63 seconds
Started May 23 12:55:36 PM PDT 24
Finished May 23 12:55:41 PM PDT 24
Peak memory 202028 kb
Host smart-2d44327b-a699-454a-8ad9-f477d6447dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888873110 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.888873110
Directory /workspace/24.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.914316972
Short name T552
Test name
Test status
Simulation time 2117742325 ps
CPU time 1.85 seconds
Started May 23 12:55:36 PM PDT 24
Finished May 23 12:55:39 PM PDT 24
Peak memory 201988 kb
Host smart-1547d3f2-913b-4f87-86f2-7c6f4a3dc57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914316972 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.914316972
Directory /workspace/24.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.1430569520
Short name T496
Test name
Test status
Simulation time 2535278169 ps
CPU time 2.54 seconds
Started May 23 12:55:38 PM PDT 24
Finished May 23 12:55:42 PM PDT 24
Peak memory 202036 kb
Host smart-4549b6b1-bb6d-4401-ba5b-2a1728d27478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430569520 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.1430569520
Directory /workspace/24.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_smoke.2054371608
Short name T53
Test name
Test status
Simulation time 2111646458 ps
CPU time 6.07 seconds
Started May 23 12:55:35 PM PDT 24
Finished May 23 12:55:42 PM PDT 24
Peak memory 201848 kb
Host smart-b3e26ea5-4348-4d40-a4c8-e11eb54bb52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054371608 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.2054371608
Directory /workspace/24.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all.1505518355
Short name T201
Test name
Test status
Simulation time 13345006356 ps
CPU time 32.99 seconds
Started May 23 12:55:37 PM PDT 24
Finished May 23 12:56:12 PM PDT 24
Peak memory 201908 kb
Host smart-3d94a8f8-c325-4781-8890-0657035d670d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505518355 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_s
tress_all.1505518355
Directory /workspace/24.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.2701463069
Short name T528
Test name
Test status
Simulation time 365165143208 ps
CPU time 234.71 seconds
Started May 23 12:55:39 PM PDT 24
Finished May 23 12:59:36 PM PDT 24
Peak memory 218316 kb
Host smart-54b9eaad-c21b-4f96-8f7a-59a747b9dc27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701463069 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all_with_rand_reset.2701463069
Directory /workspace/24.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.1817896761
Short name T121
Test name
Test status
Simulation time 8506829329 ps
CPU time 2.05 seconds
Started May 23 12:55:35 PM PDT 24
Finished May 23 12:55:39 PM PDT 24
Peak memory 202108 kb
Host smart-9a5d4dc4-03d7-4844-a4fb-62936412559f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817896761 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ultra_low_pwr.1817896761
Directory /workspace/24.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_alert_test.2408434805
Short name T454
Test name
Test status
Simulation time 2015139172 ps
CPU time 5.85 seconds
Started May 23 12:55:49 PM PDT 24
Finished May 23 12:55:56 PM PDT 24
Peak memory 202032 kb
Host smart-b5a86bf4-3196-4110-bd2a-c5161342fe15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408434805 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_te
st.2408434805
Directory /workspace/25.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.1438786958
Short name T493
Test name
Test status
Simulation time 3634700366 ps
CPU time 5.71 seconds
Started May 23 12:55:53 PM PDT 24
Finished May 23 12:56:00 PM PDT 24
Peak memory 202176 kb
Host smart-0ec75cb7-86c2-45f1-8dc8-12e7f73a1d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438786958 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.1
438786958
Directory /workspace/25.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.146611409
Short name T347
Test name
Test status
Simulation time 100853100321 ps
CPU time 46.86 seconds
Started May 23 12:55:49 PM PDT 24
Finished May 23 12:56:37 PM PDT 24
Peak memory 202316 kb
Host smart-e14a9bac-c3d9-4234-a547-0cb4fc810b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146611409 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect_wi
th_pre_cond.146611409
Directory /workspace/25.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.2251887889
Short name T567
Test name
Test status
Simulation time 2992731341 ps
CPU time 2.59 seconds
Started May 23 12:55:48 PM PDT 24
Finished May 23 12:55:52 PM PDT 24
Peak memory 202012 kb
Host smart-99e2bb85-2aa0-4c2a-b947-2d8d16d146f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251887889 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_
ctrl_ec_pwr_on_rst.2251887889
Directory /workspace/25.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_edge_detect.3021859871
Short name T240
Test name
Test status
Simulation time 5642815508 ps
CPU time 3.86 seconds
Started May 23 12:55:54 PM PDT 24
Finished May 23 12:55:59 PM PDT 24
Peak memory 202020 kb
Host smart-bcbaecaf-d356-4025-b49d-e83021b193c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021859871 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ct
rl_edge_detect.3021859871
Directory /workspace/25.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.1395229670
Short name T395
Test name
Test status
Simulation time 2697797181 ps
CPU time 1.27 seconds
Started May 23 12:55:50 PM PDT 24
Finished May 23 12:55:52 PM PDT 24
Peak memory 202012 kb
Host smart-686bc459-50e1-4517-aabe-4ad2456d8dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395229670 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.1395229670
Directory /workspace/25.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.3855149108
Short name T62
Test name
Test status
Simulation time 2466432319 ps
CPU time 6.38 seconds
Started May 23 12:55:49 PM PDT 24
Finished May 23 12:55:57 PM PDT 24
Peak memory 202120 kb
Host smart-95b91f67-6883-438b-af36-36fd47d9fa85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855149108 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.3855149108
Directory /workspace/25.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.4211830583
Short name T183
Test name
Test status
Simulation time 2121968238 ps
CPU time 1.9 seconds
Started May 23 12:55:48 PM PDT 24
Finished May 23 12:55:50 PM PDT 24
Peak memory 201864 kb
Host smart-f37ce49f-b18c-4ec3-bc7f-134b4fc2c6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211830583 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.4211830583
Directory /workspace/25.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.4252281681
Short name T769
Test name
Test status
Simulation time 2509935868 ps
CPU time 7.78 seconds
Started May 23 12:55:48 PM PDT 24
Finished May 23 12:55:57 PM PDT 24
Peak memory 202032 kb
Host smart-94d801e1-a584-4ca5-b0dd-7323c0a4caa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252281681 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.4252281681
Directory /workspace/25.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_smoke.3126357623
Short name T605
Test name
Test status
Simulation time 2119503443 ps
CPU time 3.3 seconds
Started May 23 12:55:51 PM PDT 24
Finished May 23 12:55:56 PM PDT 24
Peak memory 201872 kb
Host smart-81b64fb1-3026-452e-afb7-246bcfd5a37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126357623 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.3126357623
Directory /workspace/25.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all.1262083443
Short name T87
Test name
Test status
Simulation time 14876959582 ps
CPU time 36.52 seconds
Started May 23 12:55:50 PM PDT 24
Finished May 23 12:56:28 PM PDT 24
Peak memory 202392 kb
Host smart-48828427-ed92-4f6f-9eeb-9680474bf984
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262083443 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_s
tress_all.1262083443
Directory /workspace/25.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.3943130997
Short name T406
Test name
Test status
Simulation time 3225815880 ps
CPU time 1.91 seconds
Started May 23 12:55:49 PM PDT 24
Finished May 23 12:55:52 PM PDT 24
Peak memory 202064 kb
Host smart-2febe8e1-a9ae-4ef7-bbe7-47866f9fbc2a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943130997 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_
ctrl_ultra_low_pwr.3943130997
Directory /workspace/25.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_alert_test.1315599057
Short name T779
Test name
Test status
Simulation time 2025414248 ps
CPU time 1.89 seconds
Started May 23 12:55:50 PM PDT 24
Finished May 23 12:55:54 PM PDT 24
Peak memory 202040 kb
Host smart-fc967284-01f1-4df5-a989-8916853cd61c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315599057 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_te
st.1315599057
Directory /workspace/26.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.3103711551
Short name T771
Test name
Test status
Simulation time 3347662216 ps
CPU time 2.69 seconds
Started May 23 12:55:51 PM PDT 24
Finished May 23 12:55:55 PM PDT 24
Peak memory 202068 kb
Host smart-393894db-a854-4beb-8096-7dad9ce806e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103711551 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.3
103711551
Directory /workspace/26.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect.1356357440
Short name T354
Test name
Test status
Simulation time 194776988532 ps
CPU time 478.81 seconds
Started May 23 12:55:49 PM PDT 24
Finished May 23 01:03:49 PM PDT 24
Peak memory 202340 kb
Host smart-b75f8e57-a14f-4308-9675-d9386d1212a5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356357440 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_c
trl_combo_detect.1356357440
Directory /workspace/26.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.1074361234
Short name T232
Test name
Test status
Simulation time 66864608632 ps
CPU time 45.83 seconds
Started May 23 12:55:48 PM PDT 24
Finished May 23 12:56:35 PM PDT 24
Peak memory 202364 kb
Host smart-00541040-46b0-4809-9d79-397e4f2d5b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074361234 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect_w
ith_pre_cond.1074361234
Directory /workspace/26.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.900443005
Short name T482
Test name
Test status
Simulation time 773138706373 ps
CPU time 1941.11 seconds
Started May 23 12:55:49 PM PDT 24
Finished May 23 01:28:11 PM PDT 24
Peak memory 202072 kb
Host smart-cddfadd0-3b51-412b-9a03-7692f578d706
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900443005 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_c
trl_ec_pwr_on_rst.900443005
Directory /workspace/26.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_edge_detect.2840849898
Short name T3
Test name
Test status
Simulation time 3855497069 ps
CPU time 2.42 seconds
Started May 23 12:55:49 PM PDT 24
Finished May 23 12:55:53 PM PDT 24
Peak memory 202004 kb
Host smart-92d01c1b-0ddd-44d0-bec7-8f54dd3e7b4c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840849898 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ct
rl_edge_detect.2840849898
Directory /workspace/26.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.1087996610
Short name T374
Test name
Test status
Simulation time 2611619750 ps
CPU time 7.43 seconds
Started May 23 12:55:54 PM PDT 24
Finished May 23 12:56:02 PM PDT 24
Peak memory 202108 kb
Host smart-05d7fb08-552e-41bb-ac15-4e1ab1fc3aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087996610 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.1087996610
Directory /workspace/26.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.2683377168
Short name T696
Test name
Test status
Simulation time 2457074292 ps
CPU time 7.14 seconds
Started May 23 12:55:50 PM PDT 24
Finished May 23 12:55:58 PM PDT 24
Peak memory 202016 kb
Host smart-f6238ead-beab-422c-81aa-c9b58d6e91d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683377168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.2683377168
Directory /workspace/26.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.3313411994
Short name T694
Test name
Test status
Simulation time 2029688323 ps
CPU time 5.51 seconds
Started May 23 12:55:53 PM PDT 24
Finished May 23 12:56:00 PM PDT 24
Peak memory 201888 kb
Host smart-56f97a66-68b0-41fc-99b0-108c326cbb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313411994 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.3313411994
Directory /workspace/26.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.3618782465
Short name T614
Test name
Test status
Simulation time 2512585422 ps
CPU time 7.72 seconds
Started May 23 12:55:48 PM PDT 24
Finished May 23 12:55:57 PM PDT 24
Peak memory 202104 kb
Host smart-d04c6db5-31b4-41c7-b70c-947fba43fe63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618782465 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.3618782465
Directory /workspace/26.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_smoke.2184679433
Short name T533
Test name
Test status
Simulation time 2119716466 ps
CPU time 3.39 seconds
Started May 23 12:55:50 PM PDT 24
Finished May 23 12:55:55 PM PDT 24
Peak memory 201860 kb
Host smart-b0684093-49b4-4c1a-9c12-4cb105cfb5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184679433 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.2184679433
Directory /workspace/26.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all.2759276977
Short name T366
Test name
Test status
Simulation time 18468902460 ps
CPU time 10.21 seconds
Started May 23 12:55:51 PM PDT 24
Finished May 23 12:56:03 PM PDT 24
Peak memory 202228 kb
Host smart-e338b0e7-8830-47cc-b6f8-64f9dfc4705b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759276977 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_s
tress_all.2759276977
Directory /workspace/26.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.3284084599
Short name T135
Test name
Test status
Simulation time 13352144220 ps
CPU time 8.24 seconds
Started May 23 12:55:53 PM PDT 24
Finished May 23 12:56:03 PM PDT 24
Peak memory 202088 kb
Host smart-422d4628-3d12-4cdf-bb06-76a8ce323999
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284084599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_
ctrl_ultra_low_pwr.3284084599
Directory /workspace/26.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_alert_test.3904379922
Short name T612
Test name
Test status
Simulation time 2022669778 ps
CPU time 3.46 seconds
Started May 23 12:55:50 PM PDT 24
Finished May 23 12:55:54 PM PDT 24
Peak memory 202024 kb
Host smart-82eb1ef9-8a16-4dcb-a9d1-1abbfb1ee977
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904379922 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_te
st.3904379922
Directory /workspace/27.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.4070331087
Short name T423
Test name
Test status
Simulation time 3903660544 ps
CPU time 2.99 seconds
Started May 23 12:55:51 PM PDT 24
Finished May 23 12:55:56 PM PDT 24
Peak memory 202228 kb
Host smart-5fafc602-893c-4dfa-bc01-b546a3f2b894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070331087 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.4
070331087
Directory /workspace/27.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.2279720641
Short name T719
Test name
Test status
Simulation time 25843300463 ps
CPU time 17.54 seconds
Started May 23 12:55:49 PM PDT 24
Finished May 23 12:56:07 PM PDT 24
Peak memory 202264 kb
Host smart-c4e9cb0f-2d46-43e7-bfbe-94fc4c2d6a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279720641 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect_w
ith_pre_cond.2279720641
Directory /workspace/27.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.3368390567
Short name T621
Test name
Test status
Simulation time 3840632210 ps
CPU time 2.99 seconds
Started May 23 12:55:50 PM PDT 24
Finished May 23 12:55:54 PM PDT 24
Peak memory 202088 kb
Host smart-a0f44357-95b1-4322-b87f-43aff07e01cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368390567 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ec_pwr_on_rst.3368390567
Directory /workspace/27.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_edge_detect.3884387923
Short name T186
Test name
Test status
Simulation time 3475602597 ps
CPU time 9.98 seconds
Started May 23 12:55:51 PM PDT 24
Finished May 23 12:56:03 PM PDT 24
Peak memory 202088 kb
Host smart-a3a4d6a2-a847-4568-b2f8-01c6b655cb06
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884387923 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ct
rl_edge_detect.3884387923
Directory /workspace/27.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.1102575844
Short name T233
Test name
Test status
Simulation time 2624679509 ps
CPU time 2.64 seconds
Started May 23 12:55:50 PM PDT 24
Finished May 23 12:55:53 PM PDT 24
Peak memory 202036 kb
Host smart-0be85447-31f3-4016-a2b7-c27756dadc47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102575844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.1102575844
Directory /workspace/27.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.1563985172
Short name T634
Test name
Test status
Simulation time 2512463988 ps
CPU time 1.43 seconds
Started May 23 12:55:54 PM PDT 24
Finished May 23 12:55:56 PM PDT 24
Peak memory 202116 kb
Host smart-afbc4812-054e-4575-8b02-e8cfac67781c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563985172 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.1563985172
Directory /workspace/27.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.4265269622
Short name T446
Test name
Test status
Simulation time 2156838577 ps
CPU time 3.06 seconds
Started May 23 12:55:51 PM PDT 24
Finished May 23 12:55:56 PM PDT 24
Peak memory 202012 kb
Host smart-ec1a02df-53e9-47ab-9bf5-84ad3de75fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265269622 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.4265269622
Directory /workspace/27.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.3814838312
Short name T743
Test name
Test status
Simulation time 2527220416 ps
CPU time 2.04 seconds
Started May 23 12:55:53 PM PDT 24
Finished May 23 12:55:57 PM PDT 24
Peak memory 202036 kb
Host smart-007c9832-2a1b-4475-8c90-deef126606c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814838312 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.3814838312
Directory /workspace/27.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_smoke.4131726073
Short name T461
Test name
Test status
Simulation time 2123171854 ps
CPU time 2.1 seconds
Started May 23 12:55:50 PM PDT 24
Finished May 23 12:55:53 PM PDT 24
Peak memory 201796 kb
Host smart-c81943f4-0427-4c52-ad0d-12ece7bb880b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131726073 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.4131726073
Directory /workspace/27.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all.3833469595
Short name T750
Test name
Test status
Simulation time 6248014920 ps
CPU time 17.48 seconds
Started May 23 12:55:50 PM PDT 24
Finished May 23 12:56:08 PM PDT 24
Peak memory 202016 kb
Host smart-d6c741fb-cf21-4917-b572-9beddd9ea685
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833469595 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_s
tress_all.3833469595
Directory /workspace/27.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.1561423355
Short name T174
Test name
Test status
Simulation time 506100657961 ps
CPU time 90.35 seconds
Started May 23 12:55:53 PM PDT 24
Finished May 23 12:57:25 PM PDT 24
Peak memory 210680 kb
Host smart-962cf75c-d321-4428-b6c0-023182a34cbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561423355 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all_with_rand_reset.1561423355
Directory /workspace/27.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_alert_test.2175209345
Short name T732
Test name
Test status
Simulation time 2037790251 ps
CPU time 1.81 seconds
Started May 23 12:56:05 PM PDT 24
Finished May 23 12:56:08 PM PDT 24
Peak memory 201964 kb
Host smart-5c477f27-970f-43b2-85db-464c3a57c3e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175209345 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_te
st.2175209345
Directory /workspace/28.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.3807605064
Short name T466
Test name
Test status
Simulation time 3365386063 ps
CPU time 4.91 seconds
Started May 23 12:56:03 PM PDT 24
Finished May 23 12:56:09 PM PDT 24
Peak memory 202164 kb
Host smart-ff1df130-f7bc-45b0-b2c8-bd091f051a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807605064 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.3
807605064
Directory /workspace/28.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect.1542636030
Short name T111
Test name
Test status
Simulation time 133388484856 ps
CPU time 53.78 seconds
Started May 23 12:56:05 PM PDT 24
Finished May 23 12:57:00 PM PDT 24
Peak memory 202188 kb
Host smart-ae3c7a5f-7970-4cd0-aeda-30437e20f9f1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542636030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_c
trl_combo_detect.1542636030
Directory /workspace/28.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.814698154
Short name T71
Test name
Test status
Simulation time 28102320081 ps
CPU time 20.35 seconds
Started May 23 12:56:06 PM PDT 24
Finished May 23 12:56:27 PM PDT 24
Peak memory 202324 kb
Host smart-7b8c45f8-f775-42b7-afc6-e6ac7d2576d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814698154 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect_wi
th_pre_cond.814698154
Directory /workspace/28.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.3185439592
Short name T714
Test name
Test status
Simulation time 471227812872 ps
CPU time 322.96 seconds
Started May 23 12:55:49 PM PDT 24
Finished May 23 01:01:13 PM PDT 24
Peak memory 202020 kb
Host smart-368aab6a-bdf3-4285-9504-7bc0988023fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185439592 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_
ctrl_ec_pwr_on_rst.3185439592
Directory /workspace/28.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_edge_detect.4293048728
Short name T749
Test name
Test status
Simulation time 3590324592 ps
CPU time 2.07 seconds
Started May 23 12:56:07 PM PDT 24
Finished May 23 12:56:10 PM PDT 24
Peak memory 201960 kb
Host smart-37e2c8aa-028f-4a69-b042-23fe931cbc6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293048728 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ct
rl_edge_detect.4293048728
Directory /workspace/28.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.129022067
Short name T669
Test name
Test status
Simulation time 2610370698 ps
CPU time 7.19 seconds
Started May 23 12:55:51 PM PDT 24
Finished May 23 12:56:00 PM PDT 24
Peak memory 202036 kb
Host smart-714d1560-6f05-4128-8642-8c1c00c5f888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129022067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.129022067
Directory /workspace/28.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.1236691178
Short name T512
Test name
Test status
Simulation time 2467887244 ps
CPU time 3.57 seconds
Started May 23 12:55:54 PM PDT 24
Finished May 23 12:55:59 PM PDT 24
Peak memory 202020 kb
Host smart-02a11992-5054-4565-8c95-dc97c095caef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236691178 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.1236691178
Directory /workspace/28.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.781322673
Short name T400
Test name
Test status
Simulation time 2193164500 ps
CPU time 1.97 seconds
Started May 23 12:55:48 PM PDT 24
Finished May 23 12:55:51 PM PDT 24
Peak memory 202104 kb
Host smart-071e80d0-1c7e-4a6b-9662-7d1673d0fdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781322673 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.781322673
Directory /workspace/28.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.2635726813
Short name T404
Test name
Test status
Simulation time 2520810417 ps
CPU time 3.98 seconds
Started May 23 12:55:52 PM PDT 24
Finished May 23 12:55:58 PM PDT 24
Peak memory 202048 kb
Host smart-ed86a7ae-f4cb-451c-a4c3-7af6658a87b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635726813 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.2635726813
Directory /workspace/28.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_smoke.657455533
Short name T627
Test name
Test status
Simulation time 2111987565 ps
CPU time 6.34 seconds
Started May 23 12:55:51 PM PDT 24
Finished May 23 12:55:58 PM PDT 24
Peak memory 201820 kb
Host smart-e4d13251-b6fd-4093-808d-254b16809133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657455533 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.657455533
Directory /workspace/28.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all.3279062416
Short name T748
Test name
Test status
Simulation time 407092865343 ps
CPU time 263.71 seconds
Started May 23 12:56:05 PM PDT 24
Finished May 23 01:00:30 PM PDT 24
Peak memory 202012 kb
Host smart-e932780e-8415-45dd-b1f5-a7d8288c00a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279062416 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_s
tress_all.3279062416
Directory /workspace/28.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.2873091872
Short name T113
Test name
Test status
Simulation time 61764759463 ps
CPU time 38.94 seconds
Started May 23 12:56:05 PM PDT 24
Finished May 23 12:56:45 PM PDT 24
Peak memory 210624 kb
Host smart-7e34da15-ab97-48cd-bcf4-5a4fb6efe185
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873091872 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all_with_rand_reset.2873091872
Directory /workspace/28.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.2365530512
Short name T115
Test name
Test status
Simulation time 6235954572 ps
CPU time 7.57 seconds
Started May 23 12:56:03 PM PDT 24
Finished May 23 12:56:11 PM PDT 24
Peak memory 202024 kb
Host smart-43de4b1d-a602-4c39-a1fa-b064ee578486
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365530512 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_
ctrl_ultra_low_pwr.2365530512
Directory /workspace/28.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_alert_test.3151922711
Short name T5
Test name
Test status
Simulation time 2013165065 ps
CPU time 6.26 seconds
Started May 23 12:56:05 PM PDT 24
Finished May 23 12:56:12 PM PDT 24
Peak memory 202012 kb
Host smart-8803a049-3778-4ba8-a7a9-f5f2646bcfab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151922711 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_te
st.3151922711
Directory /workspace/29.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.894136092
Short name T476
Test name
Test status
Simulation time 3746336733 ps
CPU time 5.24 seconds
Started May 23 12:56:08 PM PDT 24
Finished May 23 12:56:14 PM PDT 24
Peak memory 202176 kb
Host smart-3213b5a3-4650-40b3-a28b-e6628ecd1125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894136092 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.894136092
Directory /workspace/29.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.2089239710
Short name T717
Test name
Test status
Simulation time 64071816161 ps
CPU time 175.35 seconds
Started May 23 12:56:06 PM PDT 24
Finished May 23 12:59:03 PM PDT 24
Peak memory 202268 kb
Host smart-6363c644-0fce-4f1d-996e-758beaebcff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089239710 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect_w
ith_pre_cond.2089239710
Directory /workspace/29.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.2732325204
Short name T532
Test name
Test status
Simulation time 4588832622 ps
CPU time 2.96 seconds
Started May 23 12:56:03 PM PDT 24
Finished May 23 12:56:08 PM PDT 24
Peak memory 202072 kb
Host smart-ae4db6bf-de09-48ff-8694-8a76ad551711
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732325204 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ec_pwr_on_rst.2732325204
Directory /workspace/29.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_edge_detect.3021813079
Short name T185
Test name
Test status
Simulation time 3248304882 ps
CPU time 9.43 seconds
Started May 23 12:56:05 PM PDT 24
Finished May 23 12:56:16 PM PDT 24
Peak memory 202164 kb
Host smart-9ecc099a-1e14-460d-a363-1f6c5faf22e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021813079 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ct
rl_edge_detect.3021813079
Directory /workspace/29.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.1768756334
Short name T65
Test name
Test status
Simulation time 2633080105 ps
CPU time 2.38 seconds
Started May 23 12:56:04 PM PDT 24
Finished May 23 12:56:07 PM PDT 24
Peak memory 202132 kb
Host smart-5180a5d4-8e3e-4434-adf2-ee41445e77eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768756334 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.1768756334
Directory /workspace/29.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.2375726865
Short name T296
Test name
Test status
Simulation time 2463062313 ps
CPU time 7.4 seconds
Started May 23 12:56:07 PM PDT 24
Finished May 23 12:56:16 PM PDT 24
Peak memory 201952 kb
Host smart-ceced0fa-a0e8-4ef2-b5cc-bfb5a629e60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375726865 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.2375726865
Directory /workspace/29.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.2283566671
Short name T263
Test name
Test status
Simulation time 2291755779 ps
CPU time 1.07 seconds
Started May 23 12:56:03 PM PDT 24
Finished May 23 12:56:05 PM PDT 24
Peak memory 201984 kb
Host smart-08b110d1-e017-498a-91fb-d489e2f9a5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283566671 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.2283566671
Directory /workspace/29.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.1279832882
Short name T654
Test name
Test status
Simulation time 2548807794 ps
CPU time 1.6 seconds
Started May 23 12:56:05 PM PDT 24
Finished May 23 12:56:08 PM PDT 24
Peak memory 202048 kb
Host smart-d9f4dfd8-0d46-4e5d-8b36-89438dad397a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279832882 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.1279832882
Directory /workspace/29.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_smoke.529422991
Short name T386
Test name
Test status
Simulation time 2108605263 ps
CPU time 6.26 seconds
Started May 23 12:56:07 PM PDT 24
Finished May 23 12:56:15 PM PDT 24
Peak memory 201960 kb
Host smart-f39194ac-2fd3-43d1-b58a-43fc43404e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529422991 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.529422991
Directory /workspace/29.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all.690148049
Short name T531
Test name
Test status
Simulation time 13441102989 ps
CPU time 33.64 seconds
Started May 23 12:56:02 PM PDT 24
Finished May 23 12:56:37 PM PDT 24
Peak memory 202076 kb
Host smart-59d34c73-f46d-4dd6-99d6-63fdb4fa81b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690148049 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_st
ress_all.690148049
Directory /workspace/29.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.3941026746
Short name T302
Test name
Test status
Simulation time 47269031599 ps
CPU time 129.58 seconds
Started May 23 12:56:07 PM PDT 24
Finished May 23 12:58:19 PM PDT 24
Peak memory 215532 kb
Host smart-d189fa50-3378-4e6f-bb01-66c3cb98755b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941026746 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all_with_rand_reset.3941026746
Directory /workspace/29.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_alert_test.3476923535
Short name T673
Test name
Test status
Simulation time 2013678041 ps
CPU time 5.83 seconds
Started May 23 12:53:59 PM PDT 24
Finished May 23 12:54:07 PM PDT 24
Peak memory 201956 kb
Host smart-b4fd13a4-1ed9-43b0-88a8-9b706044c36f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476923535 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_tes
t.3476923535
Directory /workspace/3.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.3628783325
Short name T88
Test name
Test status
Simulation time 214515569268 ps
CPU time 569.52 seconds
Started May 23 12:53:58 PM PDT 24
Finished May 23 01:03:29 PM PDT 24
Peak memory 202160 kb
Host smart-f7344602-4938-43ec-bc67-ff10ffe039ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628783325 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.3628783325
Directory /workspace/3.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.2435615515
Short name T479
Test name
Test status
Simulation time 2454453058 ps
CPU time 2.29 seconds
Started May 23 12:53:56 PM PDT 24
Finished May 23 12:54:00 PM PDT 24
Peak memory 201988 kb
Host smart-868c2cf6-5f33-44f5-8357-56f69572e08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435615515 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.2435615515
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1570870112
Short name T553
Test name
Test status
Simulation time 2546750197 ps
CPU time 2.22 seconds
Started May 23 12:53:59 PM PDT 24
Finished May 23 12:54:04 PM PDT 24
Peak memory 202116 kb
Host smart-72789c87-e4b7-4ff8-afda-0c2e4be8aa66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570870112 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.1570870112
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.1330719070
Short name T355
Test name
Test status
Simulation time 37587756009 ps
CPU time 97.98 seconds
Started May 23 12:54:06 PM PDT 24
Finished May 23 12:55:45 PM PDT 24
Peak memory 202260 kb
Host smart-62db9d25-9289-49aa-adf1-3a786a9e8a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330719070 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_wi
th_pre_cond.1330719070
Directory /workspace/3.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.826536161
Short name T574
Test name
Test status
Simulation time 2592568912 ps
CPU time 6.92 seconds
Started May 23 12:53:58 PM PDT 24
Finished May 23 12:54:07 PM PDT 24
Peak memory 202008 kb
Host smart-bf08ba35-5041-4bf1-9a36-a9e2434bb0d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826536161 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ct
rl_ec_pwr_on_rst.826536161
Directory /workspace/3.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_edge_detect.725515053
Short name T165
Test name
Test status
Simulation time 2553688480 ps
CPU time 2 seconds
Started May 23 12:53:58 PM PDT 24
Finished May 23 12:54:02 PM PDT 24
Peak memory 201980 kb
Host smart-e4168950-8bea-4aa0-a633-4f8fd435012c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725515053 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_edge_detect.725515053
Directory /workspace/3.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.3852690434
Short name T24
Test name
Test status
Simulation time 2612270862 ps
CPU time 7.18 seconds
Started May 23 12:53:57 PM PDT 24
Finished May 23 12:54:06 PM PDT 24
Peak memory 202020 kb
Host smart-0fd90dee-51cc-4a17-b3bf-ce2640bd3b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852690434 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.3852690434
Directory /workspace/3.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.1593214076
Short name T759
Test name
Test status
Simulation time 2488279505 ps
CPU time 2.68 seconds
Started May 23 12:53:58 PM PDT 24
Finished May 23 12:54:02 PM PDT 24
Peak memory 201988 kb
Host smart-ecd66477-246a-4bbe-ad73-2351ab30b118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593214076 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.1593214076
Directory /workspace/3.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.2381428508
Short name T511
Test name
Test status
Simulation time 2256897164 ps
CPU time 6.89 seconds
Started May 23 12:54:06 PM PDT 24
Finished May 23 12:54:14 PM PDT 24
Peak memory 201972 kb
Host smart-9f44e4e4-2a46-42e0-91f9-b983315fba8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381428508 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.2381428508
Directory /workspace/3.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.1652763003
Short name T662
Test name
Test status
Simulation time 2540126518 ps
CPU time 1.6 seconds
Started May 23 12:53:59 PM PDT 24
Finished May 23 12:54:03 PM PDT 24
Peak memory 202116 kb
Host smart-13e3a2fe-b789-4375-9b53-ebdb8f673f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652763003 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.1652763003
Directory /workspace/3.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_sec_cm.409515094
Short name T285
Test name
Test status
Simulation time 42016348838 ps
CPU time 58.07 seconds
Started May 23 12:53:57 PM PDT 24
Finished May 23 12:54:56 PM PDT 24
Peak memory 221808 kb
Host smart-b7348a33-5f75-4af6-8b50-ad54aeb60017
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409515094 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.409515094
Directory /workspace/3.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_smoke.4173928871
Short name T394
Test name
Test status
Simulation time 2136678383 ps
CPU time 1.98 seconds
Started May 23 12:54:01 PM PDT 24
Finished May 23 12:54:05 PM PDT 24
Peak memory 202044 kb
Host smart-ab66f687-295e-43ff-b7e9-a05615f9260f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173928871 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.4173928871
Directory /workspace/3.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all.3203133363
Short name T152
Test name
Test status
Simulation time 329322521702 ps
CPU time 227.56 seconds
Started May 23 12:53:58 PM PDT 24
Finished May 23 12:57:47 PM PDT 24
Peak memory 202216 kb
Host smart-717aff82-8001-4963-bc0e-cb9c215910a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203133363 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_st
ress_all.3203133363
Directory /workspace/3.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.2584531782
Short name T36
Test name
Test status
Simulation time 75342568550 ps
CPU time 51.87 seconds
Started May 23 12:53:59 PM PDT 24
Finished May 23 12:54:53 PM PDT 24
Peak memory 210648 kb
Host smart-92b4877c-a7d4-4661-af98-ca2a5869d0de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584531782 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all_with_rand_reset.2584531782
Directory /workspace/3.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.1583215158
Short name T746
Test name
Test status
Simulation time 4061111772 ps
CPU time 2.44 seconds
Started May 23 12:53:58 PM PDT 24
Finished May 23 12:54:03 PM PDT 24
Peak memory 202004 kb
Host smart-84cc4327-635c-4a64-a703-a58e9733fc55
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583215158 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ultra_low_pwr.1583215158
Directory /workspace/3.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_alert_test.2337703631
Short name T672
Test name
Test status
Simulation time 2046720201 ps
CPU time 1.93 seconds
Started May 23 12:56:02 PM PDT 24
Finished May 23 12:56:05 PM PDT 24
Peak memory 202048 kb
Host smart-14cb7df3-52c2-4948-a308-f222c81158bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337703631 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_te
st.2337703631
Directory /workspace/30.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.1474686385
Short name T50
Test name
Test status
Simulation time 3460305130 ps
CPU time 4.92 seconds
Started May 23 12:56:03 PM PDT 24
Finished May 23 12:56:09 PM PDT 24
Peak memory 202072 kb
Host smart-ce255196-e208-4b95-b863-e418912626a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474686385 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.1
474686385
Directory /workspace/30.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect.322826150
Short name T329
Test name
Test status
Simulation time 63984724921 ps
CPU time 78.85 seconds
Started May 23 12:56:04 PM PDT 24
Finished May 23 12:57:23 PM PDT 24
Peak memory 202344 kb
Host smart-aae250ad-9db0-419a-86c8-b8efd061c544
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322826150 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ct
rl_combo_detect.322826150
Directory /workspace/30.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.3944389903
Short name T501
Test name
Test status
Simulation time 65047662313 ps
CPU time 154.68 seconds
Started May 23 12:56:05 PM PDT 24
Finished May 23 12:58:40 PM PDT 24
Peak memory 202172 kb
Host smart-dbd15cde-3cb2-40bf-8918-9d321ad2036c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944389903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect_w
ith_pre_cond.3944389903
Directory /workspace/30.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.3358674009
Short name T405
Test name
Test status
Simulation time 5001893024 ps
CPU time 1.63 seconds
Started May 23 12:56:04 PM PDT 24
Finished May 23 12:56:07 PM PDT 24
Peak memory 202092 kb
Host smart-03108fb4-e0f9-4386-9314-021c90c39307
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358674009 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_
ctrl_ec_pwr_on_rst.3358674009
Directory /workspace/30.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_edge_detect.2726742876
Short name T176
Test name
Test status
Simulation time 4353803506 ps
CPU time 11.85 seconds
Started May 23 12:56:09 PM PDT 24
Finished May 23 12:56:22 PM PDT 24
Peak memory 202012 kb
Host smart-b1a90b9c-442c-4a06-9031-a7bdf02f6a94
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726742876 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ct
rl_edge_detect.2726742876
Directory /workspace/30.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.3460719488
Short name T64
Test name
Test status
Simulation time 2613224770 ps
CPU time 3.84 seconds
Started May 23 12:56:07 PM PDT 24
Finished May 23 12:56:12 PM PDT 24
Peak memory 202128 kb
Host smart-8c183305-c501-4000-a2a6-124782545140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460719488 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.3460719488
Directory /workspace/30.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.2578873973
Short name T564
Test name
Test status
Simulation time 2537624565 ps
CPU time 1.34 seconds
Started May 23 12:56:02 PM PDT 24
Finished May 23 12:56:04 PM PDT 24
Peak memory 202036 kb
Host smart-3ff61414-19dd-49a5-9384-0cd982d55e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578873973 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.2578873973
Directory /workspace/30.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.3357944811
Short name T642
Test name
Test status
Simulation time 2021220684 ps
CPU time 5.8 seconds
Started May 23 12:56:08 PM PDT 24
Finished May 23 12:56:15 PM PDT 24
Peak memory 201972 kb
Host smart-07c522b1-e682-4b69-8a4d-dd23ce8ccd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357944811 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.3357944811
Directory /workspace/30.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.3458472298
Short name T125
Test name
Test status
Simulation time 2509083003 ps
CPU time 7.35 seconds
Started May 23 12:56:06 PM PDT 24
Finished May 23 12:56:15 PM PDT 24
Peak memory 202132 kb
Host smart-29ed50ef-eee0-4d5c-acb8-47c69e0ebcb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458472298 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.3458472298
Directory /workspace/30.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_smoke.350951928
Short name T703
Test name
Test status
Simulation time 2132960491 ps
CPU time 2.16 seconds
Started May 23 12:56:08 PM PDT 24
Finished May 23 12:56:11 PM PDT 24
Peak memory 201964 kb
Host smart-f357aff1-6c05-4350-ac7c-548c78961fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350951928 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.350951928
Directory /workspace/30.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all.1724808114
Short name T23
Test name
Test status
Simulation time 11239378983 ps
CPU time 28.37 seconds
Started May 23 12:56:04 PM PDT 24
Finished May 23 12:56:33 PM PDT 24
Peak memory 202016 kb
Host smart-bcb5c851-d654-4417-88cb-c7bc8e37078d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724808114 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_s
tress_all.1724808114
Directory /workspace/30.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.1965923920
Short name T303
Test name
Test status
Simulation time 61538055578 ps
CPU time 159.14 seconds
Started May 23 12:56:08 PM PDT 24
Finished May 23 12:58:49 PM PDT 24
Peak memory 210676 kb
Host smart-c8f29a1f-a27f-453f-8a1c-bd47bc9cf1a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965923920 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all_with_rand_reset.1965923920
Directory /workspace/30.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.2262889185
Short name T58
Test name
Test status
Simulation time 5887147049 ps
CPU time 6.36 seconds
Started May 23 12:56:02 PM PDT 24
Finished May 23 12:56:10 PM PDT 24
Peak memory 202032 kb
Host smart-0dccac04-29f1-4f30-b8ce-8bb8e340dd5d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262889185 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_
ctrl_ultra_low_pwr.2262889185
Directory /workspace/30.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_alert_test.3079357516
Short name T583
Test name
Test status
Simulation time 2038812305 ps
CPU time 1.86 seconds
Started May 23 12:56:03 PM PDT 24
Finished May 23 12:56:06 PM PDT 24
Peak memory 201924 kb
Host smart-717d40ee-3e5e-4f8f-a5b1-f6c9b3f148c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079357516 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_te
st.3079357516
Directory /workspace/31.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.1699759928
Short name T661
Test name
Test status
Simulation time 3342971010 ps
CPU time 3.35 seconds
Started May 23 12:56:09 PM PDT 24
Finished May 23 12:56:13 PM PDT 24
Peak memory 202144 kb
Host smart-1296c96f-8237-46b1-885c-bfaaf09d8164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699759928 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.1
699759928
Directory /workspace/31.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect.693404781
Short name T242
Test name
Test status
Simulation time 74382820138 ps
CPU time 53.52 seconds
Started May 23 12:56:08 PM PDT 24
Finished May 23 12:57:03 PM PDT 24
Peak memory 202284 kb
Host smart-72e45073-e695-406f-93b2-c54e53990901
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693404781 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ct
rl_combo_detect.693404781
Directory /workspace/31.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.2166450267
Short name T584
Test name
Test status
Simulation time 67648459283 ps
CPU time 133.11 seconds
Started May 23 12:56:03 PM PDT 24
Finished May 23 12:58:18 PM PDT 24
Peak memory 202240 kb
Host smart-a37426ae-4108-4d1b-8c0f-db4c8b14988e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166450267 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect_w
ith_pre_cond.2166450267
Directory /workspace/31.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.1877688868
Short name T238
Test name
Test status
Simulation time 3830031725 ps
CPU time 2.04 seconds
Started May 23 12:56:07 PM PDT 24
Finished May 23 12:56:10 PM PDT 24
Peak memory 201940 kb
Host smart-1966345a-c88d-4634-b850-b69eded9f0a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877688868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ec_pwr_on_rst.1877688868
Directory /workspace/31.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_edge_detect.2709148859
Short name T40
Test name
Test status
Simulation time 5237146722 ps
CPU time 1.86 seconds
Started May 23 12:56:03 PM PDT 24
Finished May 23 12:56:06 PM PDT 24
Peak memory 202132 kb
Host smart-285f431d-5a22-4bc9-986a-cf0a4bc9c6e9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709148859 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ct
rl_edge_detect.2709148859
Directory /workspace/31.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.632110801
Short name T139
Test name
Test status
Simulation time 2609601376 ps
CPU time 7.27 seconds
Started May 23 12:56:05 PM PDT 24
Finished May 23 12:56:13 PM PDT 24
Peak memory 201952 kb
Host smart-aeb97102-f6eb-4d86-b952-1d070f0cc7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632110801 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.632110801
Directory /workspace/31.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.2063663137
Short name T629
Test name
Test status
Simulation time 2484747526 ps
CPU time 2.27 seconds
Started May 23 12:56:05 PM PDT 24
Finished May 23 12:56:09 PM PDT 24
Peak memory 202096 kb
Host smart-9665cfe7-55b5-42bc-b1a9-94ab85bdf12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063663137 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.2063663137
Directory /workspace/31.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.1092799976
Short name T425
Test name
Test status
Simulation time 2089394145 ps
CPU time 2.12 seconds
Started May 23 12:56:08 PM PDT 24
Finished May 23 12:56:12 PM PDT 24
Peak memory 201936 kb
Host smart-4f0d406b-6b3d-4882-82eb-b4f1771651e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092799976 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.1092799976
Directory /workspace/31.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.3509797879
Short name T643
Test name
Test status
Simulation time 2513505320 ps
CPU time 7.45 seconds
Started May 23 12:56:06 PM PDT 24
Finished May 23 12:56:14 PM PDT 24
Peak memory 202108 kb
Host smart-68be7dc0-f641-486f-9362-5ef48f0a0741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509797879 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.3509797879
Directory /workspace/31.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_smoke.4033041851
Short name T399
Test name
Test status
Simulation time 2110697015 ps
CPU time 6.21 seconds
Started May 23 12:56:08 PM PDT 24
Finished May 23 12:56:16 PM PDT 24
Peak memory 201956 kb
Host smart-03d501f4-c214-4fe3-a2c3-4fb456e24e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033041851 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.4033041851
Directory /workspace/31.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all.2706605040
Short name T570
Test name
Test status
Simulation time 17170867963 ps
CPU time 42.75 seconds
Started May 23 12:56:08 PM PDT 24
Finished May 23 12:56:52 PM PDT 24
Peak memory 202088 kb
Host smart-c695912c-7690-43ef-aaef-275197dc695a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706605040 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_s
tress_all.2706605040
Directory /workspace/31.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.3221986329
Short name T59
Test name
Test status
Simulation time 48540655013 ps
CPU time 120.83 seconds
Started May 23 12:56:04 PM PDT 24
Finished May 23 12:58:06 PM PDT 24
Peak memory 218836 kb
Host smart-deaea6e5-1693-43ac-8eb2-0cc12a9cbec9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221986329 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all_with_rand_reset.3221986329
Directory /workspace/31.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.4232641607
Short name T783
Test name
Test status
Simulation time 6380047795 ps
CPU time 7.36 seconds
Started May 23 12:56:08 PM PDT 24
Finished May 23 12:56:17 PM PDT 24
Peak memory 202112 kb
Host smart-c5cae790-a9d2-448a-bdf2-ea19ce7b1510
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232641607 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ultra_low_pwr.4232641607
Directory /workspace/31.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_alert_test.2039231414
Short name T452
Test name
Test status
Simulation time 2009851189 ps
CPU time 5.52 seconds
Started May 23 12:56:17 PM PDT 24
Finished May 23 12:56:24 PM PDT 24
Peak memory 201944 kb
Host smart-ef36753a-dd0b-4116-812e-8bf9266a14df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039231414 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_te
st.2039231414
Directory /workspace/32.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.2944470713
Short name T535
Test name
Test status
Simulation time 3450977840 ps
CPU time 1.92 seconds
Started May 23 12:56:08 PM PDT 24
Finished May 23 12:56:11 PM PDT 24
Peak memory 202184 kb
Host smart-812dbe1a-5f00-4428-86e7-23a2463e3498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944470713 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.2
944470713
Directory /workspace/32.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect.127960369
Short name T138
Test name
Test status
Simulation time 113946816647 ps
CPU time 86.88 seconds
Started May 23 12:56:21 PM PDT 24
Finished May 23 12:57:49 PM PDT 24
Peak memory 202284 kb
Host smart-f8936933-2a88-4f37-b91e-121bc3171624
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127960369 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ct
rl_combo_detect.127960369
Directory /workspace/32.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.2275619115
Short name T523
Test name
Test status
Simulation time 53201935664 ps
CPU time 68.84 seconds
Started May 23 12:56:19 PM PDT 24
Finished May 23 12:57:29 PM PDT 24
Peak memory 202380 kb
Host smart-01f4201c-9201-4c07-a1c1-63034f449671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275619115 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect_w
ith_pre_cond.2275619115
Directory /workspace/32.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.3109935194
Short name T537
Test name
Test status
Simulation time 2877044530 ps
CPU time 2.43 seconds
Started May 23 12:56:02 PM PDT 24
Finished May 23 12:56:06 PM PDT 24
Peak memory 202000 kb
Host smart-63eb07cb-4b45-4984-867e-744da142beb6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109935194 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ec_pwr_on_rst.3109935194
Directory /workspace/32.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_edge_detect.2171782993
Short name T187
Test name
Test status
Simulation time 3208659153 ps
CPU time 2.17 seconds
Started May 23 12:56:19 PM PDT 24
Finished May 23 12:56:23 PM PDT 24
Peak memory 202100 kb
Host smart-7a6019fd-a055-461e-8901-bf8568bfe0bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171782993 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ct
rl_edge_detect.2171782993
Directory /workspace/32.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.3896027836
Short name T588
Test name
Test status
Simulation time 2632120121 ps
CPU time 2.5 seconds
Started May 23 12:56:05 PM PDT 24
Finished May 23 12:56:09 PM PDT 24
Peak memory 202064 kb
Host smart-64da4654-fe99-4a2d-b23b-a587b9eec15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896027836 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.3896027836
Directory /workspace/32.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.3598865267
Short name T294
Test name
Test status
Simulation time 2451621143 ps
CPU time 3.56 seconds
Started May 23 12:56:05 PM PDT 24
Finished May 23 12:56:11 PM PDT 24
Peak memory 202024 kb
Host smart-12ab141d-67db-426e-a872-a63e3bf4f330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598865267 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.3598865267
Directory /workspace/32.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.2135174816
Short name T375
Test name
Test status
Simulation time 2185618163 ps
CPU time 6.16 seconds
Started May 23 12:56:07 PM PDT 24
Finished May 23 12:56:15 PM PDT 24
Peak memory 202096 kb
Host smart-0bb8c558-0dc8-4a8b-ae5b-84ed396f70fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135174816 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.2135174816
Directory /workspace/32.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.2583987381
Short name T372
Test name
Test status
Simulation time 2524087740 ps
CPU time 2.49 seconds
Started May 23 12:56:05 PM PDT 24
Finished May 23 12:56:09 PM PDT 24
Peak memory 202024 kb
Host smart-5a458738-4daf-47da-bc6c-968c714b823e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583987381 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.2583987381
Directory /workspace/32.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_smoke.1480590420
Short name T616
Test name
Test status
Simulation time 2111055022 ps
CPU time 6.29 seconds
Started May 23 12:56:07 PM PDT 24
Finished May 23 12:56:14 PM PDT 24
Peak memory 201800 kb
Host smart-8c58d0cd-c82b-401c-a83f-627b86d4a034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480590420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.1480590420
Directory /workspace/32.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all.1610051558
Short name T123
Test name
Test status
Simulation time 16468119105 ps
CPU time 42.55 seconds
Started May 23 12:56:19 PM PDT 24
Finished May 23 12:57:03 PM PDT 24
Peak memory 202172 kb
Host smart-71f6f5bb-50f1-4409-977d-94254992b3ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610051558 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_s
tress_all.1610051558
Directory /workspace/32.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.1435016878
Short name T237
Test name
Test status
Simulation time 29220043526 ps
CPU time 67.95 seconds
Started May 23 12:56:18 PM PDT 24
Finished May 23 12:57:28 PM PDT 24
Peak memory 212324 kb
Host smart-56927867-d883-4ca0-9403-cb9673339eff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435016878 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all_with_rand_reset.1435016878
Directory /workspace/32.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.949873146
Short name T427
Test name
Test status
Simulation time 2889447768 ps
CPU time 2.14 seconds
Started May 23 12:56:17 PM PDT 24
Finished May 23 12:56:20 PM PDT 24
Peak memory 202032 kb
Host smart-1852bea6-81f8-4e5f-beb0-fa9bbde2ad00
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949873146 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_c
trl_ultra_low_pwr.949873146
Directory /workspace/32.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_alert_test.3483627141
Short name T760
Test name
Test status
Simulation time 2011560531 ps
CPU time 5.66 seconds
Started May 23 12:56:19 PM PDT 24
Finished May 23 12:56:27 PM PDT 24
Peak memory 201884 kb
Host smart-3001264c-4a7e-489d-a3d7-3efc17cc853e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483627141 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_te
st.3483627141
Directory /workspace/33.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.700356628
Short name T706
Test name
Test status
Simulation time 3376645821 ps
CPU time 1.71 seconds
Started May 23 12:56:16 PM PDT 24
Finished May 23 12:56:18 PM PDT 24
Peak memory 202160 kb
Host smart-b2be6e01-492e-4748-a995-9e165ee9740c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700356628 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.700356628
Directory /workspace/33.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect.4155772718
Short name T31
Test name
Test status
Simulation time 98438501727 ps
CPU time 266.43 seconds
Started May 23 12:56:17 PM PDT 24
Finished May 23 01:00:45 PM PDT 24
Peak memory 202168 kb
Host smart-9b124db7-32f8-4bed-a90c-55c14081c12e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155772718 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_c
trl_combo_detect.4155772718
Directory /workspace/33.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.1791578650
Short name T341
Test name
Test status
Simulation time 75599630842 ps
CPU time 201.55 seconds
Started May 23 12:56:19 PM PDT 24
Finished May 23 12:59:43 PM PDT 24
Peak memory 202252 kb
Host smart-81f32674-c0bb-4650-aab9-e9b92d2945e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791578650 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect_w
ith_pre_cond.1791578650
Directory /workspace/33.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.2667767843
Short name T16
Test name
Test status
Simulation time 2976676530 ps
CPU time 2.52 seconds
Started May 23 12:56:18 PM PDT 24
Finished May 23 12:56:22 PM PDT 24
Peak memory 202000 kb
Host smart-1b899a63-c17c-41b4-942a-4fa706bc384f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667767843 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_
ctrl_ec_pwr_on_rst.2667767843
Directory /workspace/33.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_edge_detect.1393162826
Short name T776
Test name
Test status
Simulation time 4474821989 ps
CPU time 3.37 seconds
Started May 23 12:56:23 PM PDT 24
Finished May 23 12:56:28 PM PDT 24
Peak memory 202008 kb
Host smart-005026e9-6336-408f-ad98-6d6a039ac69b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393162826 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ct
rl_edge_detect.1393162826
Directory /workspace/33.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.3060764236
Short name T415
Test name
Test status
Simulation time 2616767255 ps
CPU time 4.05 seconds
Started May 23 12:56:19 PM PDT 24
Finished May 23 12:56:25 PM PDT 24
Peak memory 202032 kb
Host smart-6ac90ca9-2495-4fb0-af96-9effd3199aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060764236 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.3060764236
Directory /workspace/33.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.2730820802
Short name T687
Test name
Test status
Simulation time 2480227518 ps
CPU time 1.79 seconds
Started May 23 12:56:17 PM PDT 24
Finished May 23 12:56:21 PM PDT 24
Peak memory 202032 kb
Host smart-140d5eb5-bcfb-4758-8ff5-568c0328f658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730820802 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.2730820802
Directory /workspace/33.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.3634100086
Short name T502
Test name
Test status
Simulation time 2235748573 ps
CPU time 2.26 seconds
Started May 23 12:56:24 PM PDT 24
Finished May 23 12:56:27 PM PDT 24
Peak memory 201992 kb
Host smart-b9e1ff6f-ed05-475b-8e4a-65a33517442c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634100086 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.3634100086
Directory /workspace/33.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.425560436
Short name T437
Test name
Test status
Simulation time 2512948731 ps
CPU time 6.95 seconds
Started May 23 12:56:17 PM PDT 24
Finished May 23 12:56:24 PM PDT 24
Peak memory 202020 kb
Host smart-4e9b10a4-5aba-46e0-ad9d-1c0170161213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425560436 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.425560436
Directory /workspace/33.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_smoke.940119054
Short name T197
Test name
Test status
Simulation time 2114187443 ps
CPU time 4.74 seconds
Started May 23 12:56:15 PM PDT 24
Finished May 23 12:56:21 PM PDT 24
Peak memory 201932 kb
Host smart-472b9854-5be1-45e8-8f7e-13111fa73045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940119054 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.940119054
Directory /workspace/33.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.3567807818
Short name T367
Test name
Test status
Simulation time 36398184041 ps
CPU time 50.21 seconds
Started May 23 12:56:17 PM PDT 24
Finished May 23 12:57:09 PM PDT 24
Peak memory 210668 kb
Host smart-b5d53d23-43d5-4150-ba66-45004a9aab81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567807818 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all_with_rand_reset.3567807818
Directory /workspace/33.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.3459141934
Short name T691
Test name
Test status
Simulation time 2055431801210 ps
CPU time 71.16 seconds
Started May 23 12:56:17 PM PDT 24
Finished May 23 12:57:30 PM PDT 24
Peak memory 202020 kb
Host smart-50b33747-1114-48f3-85f5-b4b00bcb885f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459141934 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_
ctrl_ultra_low_pwr.3459141934
Directory /workspace/33.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_alert_test.1408979495
Short name T445
Test name
Test status
Simulation time 2072120609 ps
CPU time 1.42 seconds
Started May 23 12:56:17 PM PDT 24
Finished May 23 12:56:20 PM PDT 24
Peak memory 201960 kb
Host smart-9f4d66d3-7df2-4815-a4c1-fd34bfbd1e4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408979495 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_te
st.1408979495
Directory /workspace/34.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.2893478819
Short name T485
Test name
Test status
Simulation time 3209760690 ps
CPU time 2.71 seconds
Started May 23 12:56:19 PM PDT 24
Finished May 23 12:56:24 PM PDT 24
Peak memory 202088 kb
Host smart-149f9858-ba06-4e1c-97d9-cc86bbfe6c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893478819 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.2
893478819
Directory /workspace/34.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect.3830603138
Short name T112
Test name
Test status
Simulation time 161379798686 ps
CPU time 366.71 seconds
Started May 23 12:56:18 PM PDT 24
Finished May 23 01:02:26 PM PDT 24
Peak memory 202412 kb
Host smart-b7f013be-dfcb-4916-801d-7f38c537eaa9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830603138 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_c
trl_combo_detect.3830603138
Directory /workspace/34.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.757246646
Short name T491
Test name
Test status
Simulation time 4010404629 ps
CPU time 10.11 seconds
Started May 23 12:56:18 PM PDT 24
Finished May 23 12:56:29 PM PDT 24
Peak memory 202096 kb
Host smart-6585cd7e-c000-4112-834e-54fbf934734a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757246646 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_c
trl_ec_pwr_on_rst.757246646
Directory /workspace/34.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_edge_detect.1020297288
Short name T41
Test name
Test status
Simulation time 4988421586 ps
CPU time 7 seconds
Started May 23 12:56:16 PM PDT 24
Finished May 23 12:56:24 PM PDT 24
Peak memory 202004 kb
Host smart-28b7e61a-b720-4a10-a8b6-85b14853491b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020297288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ct
rl_edge_detect.1020297288
Directory /workspace/34.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.1314174535
Short name T131
Test name
Test status
Simulation time 2639298402 ps
CPU time 2.38 seconds
Started May 23 12:56:16 PM PDT 24
Finished May 23 12:56:19 PM PDT 24
Peak memory 202024 kb
Host smart-a4805935-5699-48e9-99eb-e40ffa48914a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314174535 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.1314174535
Directory /workspace/34.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.1953763473
Short name T440
Test name
Test status
Simulation time 2451818533 ps
CPU time 7.64 seconds
Started May 23 12:56:16 PM PDT 24
Finished May 23 12:56:25 PM PDT 24
Peak memory 202096 kb
Host smart-efe5660a-065f-4ce1-850b-32c457e4707a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953763473 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.1953763473
Directory /workspace/34.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.179375448
Short name T378
Test name
Test status
Simulation time 2207093224 ps
CPU time 1.98 seconds
Started May 23 12:56:17 PM PDT 24
Finished May 23 12:56:20 PM PDT 24
Peak memory 201976 kb
Host smart-a0c3304b-9411-4057-9f15-b6f9a7388bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179375448 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.179375448
Directory /workspace/34.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.3806437165
Short name T644
Test name
Test status
Simulation time 2514553786 ps
CPU time 3.87 seconds
Started May 23 12:56:16 PM PDT 24
Finished May 23 12:56:21 PM PDT 24
Peak memory 202124 kb
Host smart-603a8061-12ee-44ef-93f8-adda8ffcf48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806437165 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.3806437165
Directory /workspace/34.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_smoke.1258362759
Short name T128
Test name
Test status
Simulation time 2141848488 ps
CPU time 1.78 seconds
Started May 23 12:56:19 PM PDT 24
Finished May 23 12:56:22 PM PDT 24
Peak memory 201936 kb
Host smart-75e73e03-d94f-44c8-925e-a1dd5553efa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258362759 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.1258362759
Directory /workspace/34.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all.748630418
Short name T390
Test name
Test status
Simulation time 7066036080 ps
CPU time 18.43 seconds
Started May 23 12:56:24 PM PDT 24
Finished May 23 12:56:43 PM PDT 24
Peak memory 202008 kb
Host smart-8fd24301-330f-4a13-9868-96dc61699448
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748630418 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_st
ress_all.748630418
Directory /workspace/34.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.1224522964
Short name T221
Test name
Test status
Simulation time 68746446081 ps
CPU time 42.92 seconds
Started May 23 12:56:19 PM PDT 24
Finished May 23 12:57:04 PM PDT 24
Peak memory 212944 kb
Host smart-b1f237c1-8513-48b3-bb72-544ea08951f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224522964 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all_with_rand_reset.1224522964
Directory /workspace/34.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_alert_test.788813650
Short name T604
Test name
Test status
Simulation time 2163758430 ps
CPU time 0.93 seconds
Started May 23 12:56:18 PM PDT 24
Finished May 23 12:56:21 PM PDT 24
Peak memory 202136 kb
Host smart-d369c5c5-8556-4c36-a098-842a7620fb23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788813650 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_tes
t.788813650
Directory /workspace/35.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.1533253702
Short name T48
Test name
Test status
Simulation time 52303540354 ps
CPU time 126.47 seconds
Started May 23 12:56:24 PM PDT 24
Finished May 23 12:58:31 PM PDT 24
Peak memory 202080 kb
Host smart-6b4667c8-5fd0-4a46-967d-ea26ffd91be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533253702 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.1
533253702
Directory /workspace/35.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect.884221601
Short name T358
Test name
Test status
Simulation time 184999872537 ps
CPU time 39.91 seconds
Started May 23 12:56:18 PM PDT 24
Finished May 23 12:57:00 PM PDT 24
Peak memory 202272 kb
Host smart-8ad64875-baf1-4eb2-aa9d-51a49e769c9b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884221601 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ct
rl_combo_detect.884221601
Directory /workspace/35.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.2107162171
Short name T641
Test name
Test status
Simulation time 2648757290 ps
CPU time 7.11 seconds
Started May 23 12:56:19 PM PDT 24
Finished May 23 12:56:28 PM PDT 24
Peak memory 202004 kb
Host smart-f4b44e13-801f-4fcc-adac-938220eaeafa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107162171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_
ctrl_ec_pwr_on_rst.2107162171
Directory /workspace/35.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.2490702424
Short name T633
Test name
Test status
Simulation time 2613125401 ps
CPU time 4.19 seconds
Started May 23 12:56:18 PM PDT 24
Finished May 23 12:56:24 PM PDT 24
Peak memory 202104 kb
Host smart-632b7914-5728-4eb0-be55-63039c7944b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490702424 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.2490702424
Directory /workspace/35.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.183775823
Short name T141
Test name
Test status
Simulation time 2453015366 ps
CPU time 6.66 seconds
Started May 23 12:56:18 PM PDT 24
Finished May 23 12:56:27 PM PDT 24
Peak memory 202024 kb
Host smart-99dde1a1-4cc5-488d-a5d5-a4049cc49dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183775823 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.183775823
Directory /workspace/35.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.877277497
Short name T721
Test name
Test status
Simulation time 2117005894 ps
CPU time 5.89 seconds
Started May 23 12:56:19 PM PDT 24
Finished May 23 12:56:26 PM PDT 24
Peak memory 201840 kb
Host smart-38dbc0bf-2827-4c21-8be5-3b7b81e73242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877277497 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.877277497
Directory /workspace/35.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.1689272332
Short name T300
Test name
Test status
Simulation time 2546286699 ps
CPU time 1.91 seconds
Started May 23 12:56:24 PM PDT 24
Finished May 23 12:56:27 PM PDT 24
Peak memory 202028 kb
Host smart-4e39a49a-e261-4cee-b3cf-a8af281319d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689272332 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.1689272332
Directory /workspace/35.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_smoke.2321672395
Short name T486
Test name
Test status
Simulation time 2132358823 ps
CPU time 1.91 seconds
Started May 23 12:56:17 PM PDT 24
Finished May 23 12:56:20 PM PDT 24
Peak memory 201844 kb
Host smart-3e813736-5bd7-4123-815b-6654d986c112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321672395 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.2321672395
Directory /workspace/35.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all.2500700689
Short name T293
Test name
Test status
Simulation time 10541302382 ps
CPU time 6.95 seconds
Started May 23 12:56:19 PM PDT 24
Finished May 23 12:56:27 PM PDT 24
Peak memory 202108 kb
Host smart-39bbc4f1-cccd-4494-a028-102bf3ababf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500700689 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_s
tress_all.2500700689
Directory /workspace/35.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.367665028
Short name T418
Test name
Test status
Simulation time 29347598390 ps
CPU time 39.31 seconds
Started May 23 12:56:18 PM PDT 24
Finished May 23 12:57:00 PM PDT 24
Peak memory 212240 kb
Host smart-3485ebd0-035a-490c-9892-dcd28d8ee6f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367665028 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all_with_rand_reset.367665028
Directory /workspace/35.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.3492925228
Short name T82
Test name
Test status
Simulation time 796729177923 ps
CPU time 106.7 seconds
Started May 23 12:56:19 PM PDT 24
Finished May 23 12:58:08 PM PDT 24
Peak memory 202028 kb
Host smart-e1c443ce-5580-47a7-afca-b8e2ee4d6a06
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492925228 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_
ctrl_ultra_low_pwr.3492925228
Directory /workspace/35.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_alert_test.3146897690
Short name T665
Test name
Test status
Simulation time 2017108545 ps
CPU time 4.06 seconds
Started May 23 12:56:34 PM PDT 24
Finished May 23 12:56:39 PM PDT 24
Peak memory 202040 kb
Host smart-70cb6a59-13ef-44ca-b020-bee3b0b720fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146897690 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_te
st.3146897690
Directory /workspace/36.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.3338495074
Short name T25
Test name
Test status
Simulation time 3493782786 ps
CPU time 2.84 seconds
Started May 23 12:56:33 PM PDT 24
Finished May 23 12:56:38 PM PDT 24
Peak memory 202172 kb
Host smart-da975f36-ee06-4e6c-822e-9e064c2b6128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338495074 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.3
338495074
Directory /workspace/36.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.2094789095
Short name T162
Test name
Test status
Simulation time 2566968412 ps
CPU time 5.26 seconds
Started May 23 12:56:32 PM PDT 24
Finished May 23 12:56:40 PM PDT 24
Peak memory 201936 kb
Host smart-f48571a3-01aa-402f-92eb-16cb5ae1f7aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094789095 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_
ctrl_ec_pwr_on_rst.2094789095
Directory /workspace/36.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_edge_detect.2476571965
Short name T204
Test name
Test status
Simulation time 4425898762 ps
CPU time 3.06 seconds
Started May 23 12:56:31 PM PDT 24
Finished May 23 12:56:36 PM PDT 24
Peak memory 202004 kb
Host smart-ea1640c2-c8c1-48c2-871d-19fb1084cbc9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476571965 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ct
rl_edge_detect.2476571965
Directory /workspace/36.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.2074191032
Short name T432
Test name
Test status
Simulation time 2632440035 ps
CPU time 2.43 seconds
Started May 23 12:56:34 PM PDT 24
Finished May 23 12:56:38 PM PDT 24
Peak memory 202008 kb
Host smart-7d859de5-f2f0-44d1-9bde-23d6ee4ef1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074191032 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.2074191032
Directory /workspace/36.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.2408584784
Short name T712
Test name
Test status
Simulation time 2478487694 ps
CPU time 1.64 seconds
Started May 23 12:56:24 PM PDT 24
Finished May 23 12:56:27 PM PDT 24
Peak memory 202012 kb
Host smart-9e8f791f-5eee-4e45-9c7b-09e1cd55c6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408584784 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.2408584784
Directory /workspace/36.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.8424982
Short name T102
Test name
Test status
Simulation time 2314473921 ps
CPU time 1.02 seconds
Started May 23 12:56:18 PM PDT 24
Finished May 23 12:56:21 PM PDT 24
Peak memory 202196 kb
Host smart-0e3933e0-6533-40c5-98ed-0728556a0b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8424982 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.8424982
Directory /workspace/36.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.3143424370
Short name T373
Test name
Test status
Simulation time 2530011061 ps
CPU time 2.56 seconds
Started May 23 12:56:32 PM PDT 24
Finished May 23 12:56:36 PM PDT 24
Peak memory 202048 kb
Host smart-3a25b539-334f-48dc-976f-f7eb18fed344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143424370 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.3143424370
Directory /workspace/36.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_smoke.1875304879
Short name T435
Test name
Test status
Simulation time 2118203760 ps
CPU time 3.56 seconds
Started May 23 12:56:18 PM PDT 24
Finished May 23 12:56:24 PM PDT 24
Peak memory 201832 kb
Host smart-03e62e9b-53b6-459b-99b5-b1cdae0087e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875304879 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.1875304879
Directory /workspace/36.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all.799016785
Short name T2
Test name
Test status
Simulation time 153622291554 ps
CPU time 419.16 seconds
Started May 23 12:56:33 PM PDT 24
Finished May 23 01:03:34 PM PDT 24
Peak memory 202280 kb
Host smart-5c81f3c9-f198-4b54-b5e4-cdaf8fbe5129
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799016785 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_st
ress_all.799016785
Directory /workspace/36.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.3311245112
Short name T101
Test name
Test status
Simulation time 108895901531 ps
CPU time 53.23 seconds
Started May 23 12:56:32 PM PDT 24
Finished May 23 12:57:28 PM PDT 24
Peak memory 213464 kb
Host smart-7274b5f1-d0a8-4545-8618-b5425893ef31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311245112 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all_with_rand_reset.3311245112
Directory /workspace/36.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.3411055773
Short name T132
Test name
Test status
Simulation time 6985215696 ps
CPU time 4.72 seconds
Started May 23 12:56:30 PM PDT 24
Finished May 23 12:56:36 PM PDT 24
Peak memory 201956 kb
Host smart-1ab78644-7558-4599-97d2-7359fe3491fc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411055773 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_
ctrl_ultra_low_pwr.3411055773
Directory /workspace/36.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_alert_test.2902536231
Short name T754
Test name
Test status
Simulation time 2022276629 ps
CPU time 3.18 seconds
Started May 23 12:56:32 PM PDT 24
Finished May 23 12:56:37 PM PDT 24
Peak memory 201856 kb
Host smart-025b7b3f-1cb8-40f9-bd58-3e7f95108ad2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902536231 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_te
st.2902536231
Directory /workspace/37.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.4120800497
Short name T738
Test name
Test status
Simulation time 3409808852 ps
CPU time 2.78 seconds
Started May 23 12:56:29 PM PDT 24
Finished May 23 12:56:33 PM PDT 24
Peak memory 202176 kb
Host smart-ebbda31b-cf32-4ec4-9737-eb350e7a4103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120800497 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.4
120800497
Directory /workspace/37.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect.2488796523
Short name T227
Test name
Test status
Simulation time 211071176173 ps
CPU time 263.21 seconds
Started May 23 12:56:30 PM PDT 24
Finished May 23 01:00:54 PM PDT 24
Peak memory 202180 kb
Host smart-c1a98ea3-030e-4dc8-ae8d-a6255ac7065b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488796523 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_c
trl_combo_detect.2488796523
Directory /workspace/37.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.1556322285
Short name T345
Test name
Test status
Simulation time 141877991566 ps
CPU time 365.79 seconds
Started May 23 12:56:30 PM PDT 24
Finished May 23 01:02:37 PM PDT 24
Peak memory 202272 kb
Host smart-6563e375-37a1-4a20-91eb-7e385b5668f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556322285 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect_w
ith_pre_cond.1556322285
Directory /workspace/37.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.1355195029
Short name T581
Test name
Test status
Simulation time 3344127395 ps
CPU time 8.88 seconds
Started May 23 12:56:32 PM PDT 24
Finished May 23 12:56:43 PM PDT 24
Peak memory 201980 kb
Host smart-28892679-e805-43a7-a6b3-12faa3d4f7ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355195029 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ec_pwr_on_rst.1355195029
Directory /workspace/37.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_edge_detect.2686405630
Short name T708
Test name
Test status
Simulation time 2451917516 ps
CPU time 3.56 seconds
Started May 23 12:56:32 PM PDT 24
Finished May 23 12:56:38 PM PDT 24
Peak memory 202024 kb
Host smart-847f65ac-92b2-4c60-9ea2-a0cae594d203
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686405630 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ct
rl_edge_detect.2686405630
Directory /workspace/37.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.1664404228
Short name T539
Test name
Test status
Simulation time 2634503973 ps
CPU time 2.3 seconds
Started May 23 12:56:32 PM PDT 24
Finished May 23 12:56:36 PM PDT 24
Peak memory 202040 kb
Host smart-4bdb2fd1-02f1-41f0-b56d-2ad0e7f41424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664404228 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.1664404228
Directory /workspace/37.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.868712229
Short name T417
Test name
Test status
Simulation time 2459437569 ps
CPU time 2.92 seconds
Started May 23 12:56:31 PM PDT 24
Finished May 23 12:56:35 PM PDT 24
Peak memory 202008 kb
Host smart-30e28bc5-8d7a-4994-a11b-e7a9b0869b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868712229 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.868712229
Directory /workspace/37.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.1972070084
Short name T598
Test name
Test status
Simulation time 2197158908 ps
CPU time 2.04 seconds
Started May 23 12:56:29 PM PDT 24
Finished May 23 12:56:32 PM PDT 24
Peak memory 202084 kb
Host smart-fe680f2d-f959-4510-9112-1b5897a2ede6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972070084 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.1972070084
Directory /workspace/37.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.4043629780
Short name T234
Test name
Test status
Simulation time 2519778801 ps
CPU time 4.3 seconds
Started May 23 12:56:32 PM PDT 24
Finished May 23 12:56:39 PM PDT 24
Peak memory 202084 kb
Host smart-e18f9667-f97d-4640-92df-cd5388950db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043629780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.4043629780
Directory /workspace/37.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_smoke.3767933673
Short name T659
Test name
Test status
Simulation time 2113928098 ps
CPU time 5.74 seconds
Started May 23 12:56:32 PM PDT 24
Finished May 23 12:56:40 PM PDT 24
Peak memory 201860 kb
Host smart-26dabca2-1df7-4e76-8651-207b4ad33a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767933673 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_smoke.3767933673
Directory /workspace/37.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all.2081842058
Short name T744
Test name
Test status
Simulation time 40508143817 ps
CPU time 6.66 seconds
Started May 23 12:56:30 PM PDT 24
Finished May 23 12:56:38 PM PDT 24
Peak memory 202116 kb
Host smart-51d9d4e3-10d7-436d-8eb1-5b248140d35f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081842058 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_s
tress_all.2081842058
Directory /workspace/37.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.3036945085
Short name T214
Test name
Test status
Simulation time 758746689855 ps
CPU time 36.68 seconds
Started May 23 12:56:30 PM PDT 24
Finished May 23 12:57:08 PM PDT 24
Peak memory 212180 kb
Host smart-f11eeed3-dded-45c2-80cd-38140556177d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036945085 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all_with_rand_reset.3036945085
Directory /workspace/37.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.1050437152
Short name T699
Test name
Test status
Simulation time 10331564491 ps
CPU time 2.82 seconds
Started May 23 12:56:31 PM PDT 24
Finished May 23 12:56:35 PM PDT 24
Peak memory 202120 kb
Host smart-5e52de57-ef71-4343-ae99-9e8fe3a71011
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050437152 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ultra_low_pwr.1050437152
Directory /workspace/37.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_alert_test.3464785941
Short name T576
Test name
Test status
Simulation time 2040893129 ps
CPU time 1.85 seconds
Started May 23 12:56:31 PM PDT 24
Finished May 23 12:56:35 PM PDT 24
Peak memory 201964 kb
Host smart-6c1a5333-ed57-4979-8392-e9bc4aa0fa8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464785941 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_te
st.3464785941
Directory /workspace/38.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.934342628
Short name T503
Test name
Test status
Simulation time 3841136760 ps
CPU time 3.06 seconds
Started May 23 12:56:34 PM PDT 24
Finished May 23 12:56:39 PM PDT 24
Peak memory 202180 kb
Host smart-d7e8e82f-e61e-4f48-aa5a-67ff46ba77c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934342628 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.934342628
Directory /workspace/38.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect.3488652098
Short name T536
Test name
Test status
Simulation time 124624938601 ps
CPU time 319.05 seconds
Started May 23 12:56:34 PM PDT 24
Finished May 23 01:01:55 PM PDT 24
Peak memory 202192 kb
Host smart-5645e1dc-cc23-4376-b228-7f25244d79b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488652098 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_combo_detect.3488652098
Directory /workspace/38.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.574312091
Short name T408
Test name
Test status
Simulation time 2433500264 ps
CPU time 6.62 seconds
Started May 23 12:56:30 PM PDT 24
Finished May 23 12:56:38 PM PDT 24
Peak memory 201988 kb
Host smart-f7a251fe-984d-4dfd-acb9-cd9917ef4264
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574312091 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_ec_pwr_on_rst.574312091
Directory /workspace/38.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.2509009797
Short name T389
Test name
Test status
Simulation time 2833405098 ps
CPU time 1.01 seconds
Started May 23 12:56:31 PM PDT 24
Finished May 23 12:56:33 PM PDT 24
Peak memory 202000 kb
Host smart-7cbfe8cf-0e3e-4b01-98fe-06039270dd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509009797 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.2509009797
Directory /workspace/38.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.3735004974
Short name T599
Test name
Test status
Simulation time 2456239104 ps
CPU time 7.22 seconds
Started May 23 12:56:34 PM PDT 24
Finished May 23 12:56:44 PM PDT 24
Peak memory 202036 kb
Host smart-8c9d1d3d-f9a9-4cd1-bf39-b29647496fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735004974 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.3735004974
Directory /workspace/38.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.1157715030
Short name T765
Test name
Test status
Simulation time 2106835712 ps
CPU time 3.01 seconds
Started May 23 12:56:31 PM PDT 24
Finished May 23 12:56:36 PM PDT 24
Peak memory 201972 kb
Host smart-be19b5db-0b4e-4e3f-82f7-2b9a063f117d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157715030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.1157715030
Directory /workspace/38.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.4032481912
Short name T69
Test name
Test status
Simulation time 2513633829 ps
CPU time 6.97 seconds
Started May 23 12:56:30 PM PDT 24
Finished May 23 12:56:38 PM PDT 24
Peak memory 202048 kb
Host smart-7b2a6e61-ca60-4b36-8db9-eb90bf78b210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032481912 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.4032481912
Directory /workspace/38.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_smoke.1349013867
Short name T414
Test name
Test status
Simulation time 2145417161 ps
CPU time 1.51 seconds
Started May 23 12:56:29 PM PDT 24
Finished May 23 12:56:32 PM PDT 24
Peak memory 201948 kb
Host smart-39b88677-f4b1-4763-8f01-fd95070a46c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349013867 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.1349013867
Directory /workspace/38.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all.3151609119
Short name T772
Test name
Test status
Simulation time 13090205483 ps
CPU time 8.95 seconds
Started May 23 12:56:35 PM PDT 24
Finished May 23 12:56:46 PM PDT 24
Peak memory 202112 kb
Host smart-0153910d-c3df-4bac-aebf-1b77a5096561
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151609119 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_s
tress_all.3151609119
Directory /workspace/38.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.3121922569
Short name T650
Test name
Test status
Simulation time 15432527222 ps
CPU time 38.4 seconds
Started May 23 12:56:35 PM PDT 24
Finished May 23 12:57:15 PM PDT 24
Peak memory 212028 kb
Host smart-e1237479-b06b-44fc-a377-96460f41cc8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121922569 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_stress_all_with_rand_reset.3121922569
Directory /workspace/38.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.1233322668
Short name T119
Test name
Test status
Simulation time 3669165650 ps
CPU time 2.31 seconds
Started May 23 12:56:34 PM PDT 24
Finished May 23 12:56:38 PM PDT 24
Peak memory 202032 kb
Host smart-07b7dd2a-bbe4-4f12-b779-e46414451dd2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233322668 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_
ctrl_ultra_low_pwr.1233322668
Directory /workspace/38.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_alert_test.2489891541
Short name T770
Test name
Test status
Simulation time 2049056875 ps
CPU time 1.65 seconds
Started May 23 12:56:41 PM PDT 24
Finished May 23 12:56:44 PM PDT 24
Peak memory 201932 kb
Host smart-8366123f-9ec8-4595-a124-511ccbc676c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489891541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_te
st.2489891541
Directory /workspace/39.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.2774087275
Short name T755
Test name
Test status
Simulation time 40035103701 ps
CPU time 47.85 seconds
Started May 23 12:56:35 PM PDT 24
Finished May 23 12:57:25 PM PDT 24
Peak memory 202152 kb
Host smart-d174d93b-0452-41c2-af72-94e231d7b71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774087275 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.2
774087275
Directory /workspace/39.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect.256613671
Short name T129
Test name
Test status
Simulation time 208192231413 ps
CPU time 530.29 seconds
Started May 23 12:56:31 PM PDT 24
Finished May 23 01:05:24 PM PDT 24
Peak memory 202252 kb
Host smart-882a44ca-6f3b-4cf9-83c6-e190cb61eaa5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256613671 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ct
rl_combo_detect.256613671
Directory /workspace/39.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.2509215754
Short name T545
Test name
Test status
Simulation time 27088172607 ps
CPU time 34.73 seconds
Started May 23 12:56:34 PM PDT 24
Finished May 23 12:57:11 PM PDT 24
Peak memory 202332 kb
Host smart-38aeb9b5-2626-474d-8c92-090d1d77e69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509215754 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect_w
ith_pre_cond.2509215754
Directory /workspace/39.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.3549604445
Short name T658
Test name
Test status
Simulation time 3378233824 ps
CPU time 5.35 seconds
Started May 23 12:56:35 PM PDT 24
Finished May 23 12:56:42 PM PDT 24
Peak memory 201996 kb
Host smart-52db8998-e79d-4153-a5ca-edceced550f1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549604445 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ec_pwr_on_rst.3549604445
Directory /workspace/39.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_edge_detect.3761517600
Short name T554
Test name
Test status
Simulation time 3052607079 ps
CPU time 8.31 seconds
Started May 23 12:56:35 PM PDT 24
Finished May 23 12:56:45 PM PDT 24
Peak memory 202088 kb
Host smart-5e79c090-6442-4e6d-b1e8-8f213c8e11d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761517600 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ct
rl_edge_detect.3761517600
Directory /workspace/39.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.3381568963
Short name T700
Test name
Test status
Simulation time 2617831960 ps
CPU time 4.04 seconds
Started May 23 12:56:37 PM PDT 24
Finished May 23 12:56:42 PM PDT 24
Peak memory 202012 kb
Host smart-bd0e45b7-cbe7-4e8c-a857-6c2d11347891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381568963 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.3381568963
Directory /workspace/39.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.3368915129
Short name T457
Test name
Test status
Simulation time 2460709277 ps
CPU time 8.52 seconds
Started May 23 12:56:33 PM PDT 24
Finished May 23 12:56:44 PM PDT 24
Peak memory 202188 kb
Host smart-6539e80e-e1e6-4175-82f7-d9ad1bc1f4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368915129 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.3368915129
Directory /workspace/39.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.3844115380
Short name T190
Test name
Test status
Simulation time 2231370082 ps
CPU time 3.34 seconds
Started May 23 12:56:33 PM PDT 24
Finished May 23 12:56:39 PM PDT 24
Peak memory 202004 kb
Host smart-51352951-ed8a-4bd9-8b7b-6073a00fba2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844115380 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.3844115380
Directory /workspace/39.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.718776161
Short name T617
Test name
Test status
Simulation time 2529103263 ps
CPU time 2.34 seconds
Started May 23 12:56:31 PM PDT 24
Finished May 23 12:56:35 PM PDT 24
Peak memory 202136 kb
Host smart-78ab960b-42a6-437b-9590-c1c056385c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718776161 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.718776161
Directory /workspace/39.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_smoke.829101342
Short name T775
Test name
Test status
Simulation time 2116695622 ps
CPU time 3.1 seconds
Started May 23 12:56:34 PM PDT 24
Finished May 23 12:56:39 PM PDT 24
Peak memory 201932 kb
Host smart-b98f7276-bb58-4cf4-b274-40c04b6085d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829101342 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.829101342
Directory /workspace/39.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all.2057634797
Short name T260
Test name
Test status
Simulation time 119511121611 ps
CPU time 308.26 seconds
Started May 23 12:56:44 PM PDT 24
Finished May 23 01:01:56 PM PDT 24
Peak memory 202244 kb
Host smart-e638a5e8-d60d-4a6f-8093-5272f2185d9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057634797 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_s
tress_all.2057634797
Directory /workspace/39.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.2694743324
Short name T736
Test name
Test status
Simulation time 4449819712 ps
CPU time 2.26 seconds
Started May 23 12:56:34 PM PDT 24
Finished May 23 12:56:38 PM PDT 24
Peak memory 201976 kb
Host smart-a40bf989-59a8-49bf-b248-b1fe4aaad894
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694743324 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ultra_low_pwr.2694743324
Directory /workspace/39.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_alert_test.2639751233
Short name T401
Test name
Test status
Simulation time 2041634249 ps
CPU time 1.74 seconds
Started May 23 12:54:14 PM PDT 24
Finished May 23 12:54:18 PM PDT 24
Peak memory 201948 kb
Host smart-e987ae5a-ac8a-49cc-b47e-9fa3dca2052c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639751233 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_tes
t.2639751233
Directory /workspace/4.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.2987962515
Short name T449
Test name
Test status
Simulation time 59124933837 ps
CPU time 60.81 seconds
Started May 23 12:54:12 PM PDT 24
Finished May 23 12:55:14 PM PDT 24
Peak memory 202076 kb
Host smart-dfa777d4-5bb9-4518-875f-51f2bf71a09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987962515 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.2987962515
Directory /workspace/4.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect.233847824
Short name T718
Test name
Test status
Simulation time 146871130334 ps
CPU time 195.11 seconds
Started May 23 12:54:13 PM PDT 24
Finished May 23 12:57:30 PM PDT 24
Peak memory 202260 kb
Host smart-ed2cb65b-9759-49b3-9753-695d46d2c108
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233847824 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctr
l_combo_detect.233847824
Directory /workspace/4.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.2829146684
Short name T679
Test name
Test status
Simulation time 2163906698 ps
CPU time 6.07 seconds
Started May 23 12:53:59 PM PDT 24
Finished May 23 12:54:07 PM PDT 24
Peak memory 202032 kb
Host smart-1dd6f3da-0e96-44ef-94fa-f226cda11b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829146684 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.2829146684
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2590408788
Short name T757
Test name
Test status
Simulation time 2539732754 ps
CPU time 3.88 seconds
Started May 23 12:54:00 PM PDT 24
Finished May 23 12:54:06 PM PDT 24
Peak memory 202024 kb
Host smart-d67632c7-5fe6-4c39-a395-9ffb13369f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590408788 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.2590408788
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.109926228
Short name T205
Test name
Test status
Simulation time 23851247371 ps
CPU time 17.86 seconds
Started May 23 12:54:12 PM PDT 24
Finished May 23 12:54:31 PM PDT 24
Peak memory 202352 kb
Host smart-813a9fa3-e20f-4e94-b0ef-0f4d30d94fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109926228 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_wit
h_pre_cond.109926228
Directory /workspace/4.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.4030249166
Short name T489
Test name
Test status
Simulation time 2983332855 ps
CPU time 8.32 seconds
Started May 23 12:54:06 PM PDT 24
Finished May 23 12:54:15 PM PDT 24
Peak memory 201980 kb
Host smart-a13acce2-3019-45f5-a561-90533ace5f2a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030249166 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_ec_pwr_on_rst.4030249166
Directory /workspace/4.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_edge_detect.2186472332
Short name T595
Test name
Test status
Simulation time 128922007351 ps
CPU time 96.73 seconds
Started May 23 12:54:11 PM PDT 24
Finished May 23 12:55:49 PM PDT 24
Peak memory 201996 kb
Host smart-f31a29ba-7230-497f-b05a-f7d040a6f2c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186472332 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctr
l_edge_detect.2186472332
Directory /workspace/4.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.3719513174
Short name T473
Test name
Test status
Simulation time 2609976204 ps
CPU time 7.92 seconds
Started May 23 12:54:01 PM PDT 24
Finished May 23 12:54:11 PM PDT 24
Peak memory 202192 kb
Host smart-1fcb6099-39ee-4784-abfc-591e0aded9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719513174 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.3719513174
Directory /workspace/4.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.1431644737
Short name T593
Test name
Test status
Simulation time 2455703423 ps
CPU time 6.98 seconds
Started May 23 12:53:58 PM PDT 24
Finished May 23 12:54:07 PM PDT 24
Peak memory 202020 kb
Host smart-f5cc9c24-4d4b-4865-9780-10903c45880d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431644737 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.1431644737
Directory /workspace/4.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.4196821192
Short name T430
Test name
Test status
Simulation time 2215891664 ps
CPU time 2.03 seconds
Started May 23 12:54:06 PM PDT 24
Finished May 23 12:54:10 PM PDT 24
Peak memory 201968 kb
Host smart-1aa2c6f7-e20c-4b2b-8d0d-d5e7c51f77c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196821192 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.4196821192
Directory /workspace/4.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.985537727
Short name T67
Test name
Test status
Simulation time 2512474195 ps
CPU time 7.46 seconds
Started May 23 12:53:58 PM PDT 24
Finished May 23 12:54:06 PM PDT 24
Peak memory 202120 kb
Host smart-198bdd38-645b-4211-8d91-067ed9787264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985537727 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.985537727
Directory /workspace/4.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_sec_cm.3528041146
Short name T269
Test name
Test status
Simulation time 22162387200 ps
CPU time 8.45 seconds
Started May 23 12:54:14 PM PDT 24
Finished May 23 12:54:24 PM PDT 24
Peak memory 221428 kb
Host smart-55d155b3-39cb-4c4b-b30d-88561179c03e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528041146 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.3528041146
Directory /workspace/4.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_smoke.3984825260
Short name T645
Test name
Test status
Simulation time 2122673051 ps
CPU time 2.08 seconds
Started May 23 12:54:00 PM PDT 24
Finished May 23 12:54:05 PM PDT 24
Peak memory 201960 kb
Host smart-71834b18-5825-4cfc-a11b-d2f205715237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984825260 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.3984825260
Directory /workspace/4.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all.808153250
Short name T550
Test name
Test status
Simulation time 6622988020 ps
CPU time 17.33 seconds
Started May 23 12:54:14 PM PDT 24
Finished May 23 12:54:33 PM PDT 24
Peak memory 202016 kb
Host smart-13a67af2-4afc-4283-889f-ff67a0050082
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808153250 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_str
ess_all.808153250
Directory /workspace/4.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.392727035
Short name T646
Test name
Test status
Simulation time 134000936868 ps
CPU time 45.86 seconds
Started May 23 12:54:12 PM PDT 24
Finished May 23 12:54:59 PM PDT 24
Peak memory 210628 kb
Host smart-265d4bbc-0cb6-4478-9023-3c916228fbc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392727035 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all_with_rand_reset.392727035
Directory /workspace/4.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.1956516988
Short name T57
Test name
Test status
Simulation time 9233622671 ps
CPU time 1.1 seconds
Started May 23 12:54:14 PM PDT 24
Finished May 23 12:54:17 PM PDT 24
Peak memory 202120 kb
Host smart-454a816e-5e84-422a-b2a7-c4e175d758e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956516988 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_ultra_low_pwr.1956516988
Directory /workspace/4.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_alert_test.3887502122
Short name T195
Test name
Test status
Simulation time 2075203706 ps
CPU time 1.01 seconds
Started May 23 12:56:46 PM PDT 24
Finished May 23 12:56:50 PM PDT 24
Peak memory 201948 kb
Host smart-9de646b4-3b19-4492-a056-57e87f72f2e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887502122 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_te
st.3887502122
Directory /workspace/40.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.1439101108
Short name T527
Test name
Test status
Simulation time 3026864109 ps
CPU time 8.35 seconds
Started May 23 12:56:49 PM PDT 24
Finished May 23 12:57:01 PM PDT 24
Peak memory 202060 kb
Host smart-2dbccc46-5a4c-444e-be96-a1ddd62f3913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439101108 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.1
439101108
Directory /workspace/40.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect.2074918468
Short name T97
Test name
Test status
Simulation time 155455973924 ps
CPU time 103.25 seconds
Started May 23 12:56:45 PM PDT 24
Finished May 23 12:58:32 PM PDT 24
Peak memory 202236 kb
Host smart-19140d31-546b-4745-ada1-d37494e06204
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074918468 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_c
trl_combo_detect.2074918468
Directory /workspace/40.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.445396212
Short name T547
Test name
Test status
Simulation time 3786337720 ps
CPU time 3.22 seconds
Started May 23 12:56:44 PM PDT 24
Finished May 23 12:56:51 PM PDT 24
Peak memory 202064 kb
Host smart-83411642-d5ae-4840-a2bf-45d0b66e1ebc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445396212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_c
trl_ec_pwr_on_rst.445396212
Directory /workspace/40.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_edge_detect.198189219
Short name T164
Test name
Test status
Simulation time 4886118099 ps
CPU time 6.81 seconds
Started May 23 12:56:45 PM PDT 24
Finished May 23 12:56:55 PM PDT 24
Peak memory 202156 kb
Host smart-e4c63587-d8ab-43e1-99fc-c844373bf6bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198189219 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctr
l_edge_detect.198189219
Directory /workspace/40.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.3760391682
Short name T66
Test name
Test status
Simulation time 2635006579 ps
CPU time 2.25 seconds
Started May 23 12:56:42 PM PDT 24
Finished May 23 12:56:46 PM PDT 24
Peak memory 202116 kb
Host smart-3f7fd99a-835a-4ed7-8173-36fb8145ab93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760391682 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.3760391682
Directory /workspace/40.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.3830094343
Short name T478
Test name
Test status
Simulation time 2490821167 ps
CPU time 2.27 seconds
Started May 23 12:56:43 PM PDT 24
Finished May 23 12:56:47 PM PDT 24
Peak memory 202100 kb
Host smart-dc5822f7-f47a-499f-9204-6a1aa032da93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830094343 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.3830094343
Directory /workspace/40.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.1992238937
Short name T103
Test name
Test status
Simulation time 2084248139 ps
CPU time 1.96 seconds
Started May 23 12:56:46 PM PDT 24
Finished May 23 12:56:51 PM PDT 24
Peak memory 201888 kb
Host smart-7b74b69f-7edf-4274-a651-097d7033f74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992238937 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.1992238937
Directory /workspace/40.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.3987660146
Short name T504
Test name
Test status
Simulation time 2528235735 ps
CPU time 2.24 seconds
Started May 23 12:56:46 PM PDT 24
Finished May 23 12:56:51 PM PDT 24
Peak memory 202000 kb
Host smart-c8d1c02f-00c9-4ba0-90dc-c4a9c66e9510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987660146 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.3987660146
Directory /workspace/40.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_smoke.783331054
Short name T713
Test name
Test status
Simulation time 2110098306 ps
CPU time 6.01 seconds
Started May 23 12:56:42 PM PDT 24
Finished May 23 12:56:50 PM PDT 24
Peak memory 201880 kb
Host smart-b8cf27ad-8fc3-47ae-83cd-3afd9241434f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783331054 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.783331054
Directory /workspace/40.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all.377291461
Short name T60
Test name
Test status
Simulation time 6576381818 ps
CPU time 9.05 seconds
Started May 23 12:56:44 PM PDT 24
Finished May 23 12:56:57 PM PDT 24
Peak memory 202076 kb
Host smart-12b6bd8c-3c77-4723-831d-87dc298e980a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377291461 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_st
ress_all.377291461
Directory /workspace/40.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.1679420168
Short name T208
Test name
Test status
Simulation time 118234732557 ps
CPU time 37.07 seconds
Started May 23 12:56:43 PM PDT 24
Finished May 23 12:57:23 PM PDT 24
Peak memory 210684 kb
Host smart-3122e140-9a5a-472f-8234-1309ca88681e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679420168 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all_with_rand_reset.1679420168
Directory /workspace/40.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_alert_test.2240738160
Short name T230
Test name
Test status
Simulation time 2045248880 ps
CPU time 1.73 seconds
Started May 23 12:56:45 PM PDT 24
Finished May 23 12:56:50 PM PDT 24
Peak memory 201960 kb
Host smart-3e33ad38-864b-4eab-a2c0-2803f49e5154
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240738160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_te
st.2240738160
Directory /workspace/41.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.1574159824
Short name T726
Test name
Test status
Simulation time 3120419374 ps
CPU time 8.43 seconds
Started May 23 12:56:46 PM PDT 24
Finished May 23 12:56:58 PM PDT 24
Peak memory 202184 kb
Host smart-d560e599-2704-410f-aa8c-7a424effa729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574159824 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.1
574159824
Directory /workspace/41.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect.1322268174
Short name T265
Test name
Test status
Simulation time 112254640925 ps
CPU time 74.21 seconds
Started May 23 12:56:46 PM PDT 24
Finished May 23 12:58:03 PM PDT 24
Peak memory 202284 kb
Host smart-044c6d5a-8816-4736-8a1c-eab98240eb3e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322268174 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_c
trl_combo_detect.1322268174
Directory /workspace/41.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.1658652540
Short name T363
Test name
Test status
Simulation time 25851266790 ps
CPU time 18.25 seconds
Started May 23 12:56:45 PM PDT 24
Finished May 23 12:57:07 PM PDT 24
Peak memory 202408 kb
Host smart-b354acd9-9024-4763-a06a-5a1cec072ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658652540 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect_w
ith_pre_cond.1658652540
Directory /workspace/41.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.69631892
Short name T505
Test name
Test status
Simulation time 3064436618 ps
CPU time 2.47 seconds
Started May 23 12:56:43 PM PDT 24
Finished May 23 12:56:48 PM PDT 24
Peak memory 202068 kb
Host smart-c7b7b6f0-6af7-4321-be2c-a9633a0cd875
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69631892 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ct
rl_ec_pwr_on_rst.69631892
Directory /workspace/41.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_edge_detect.4000578583
Short name T147
Test name
Test status
Simulation time 5577155159 ps
CPU time 3.26 seconds
Started May 23 12:56:46 PM PDT 24
Finished May 23 12:56:52 PM PDT 24
Peak memory 202116 kb
Host smart-853a95dc-b8d7-48dc-81f2-9636ca7570ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000578583 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ct
rl_edge_detect.4000578583
Directory /workspace/41.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.3217206866
Short name T262
Test name
Test status
Simulation time 2618225098 ps
CPU time 4.35 seconds
Started May 23 12:56:44 PM PDT 24
Finished May 23 12:56:52 PM PDT 24
Peak memory 202000 kb
Host smart-3724920d-d9c2-468c-af0c-8576a9f6522c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217206866 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.3217206866
Directory /workspace/41.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.911818193
Short name T153
Test name
Test status
Simulation time 2446858823 ps
CPU time 6.64 seconds
Started May 23 12:56:50 PM PDT 24
Finished May 23 12:56:59 PM PDT 24
Peak memory 201940 kb
Host smart-48f87152-a299-4f26-9808-fed2465375e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911818193 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.911818193
Directory /workspace/41.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.195709589
Short name T786
Test name
Test status
Simulation time 2112476834 ps
CPU time 5.84 seconds
Started May 23 12:56:41 PM PDT 24
Finished May 23 12:56:49 PM PDT 24
Peak memory 201980 kb
Host smart-93aec936-270d-424e-836b-06713e202596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195709589 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.195709589
Directory /workspace/41.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.587920334
Short name T762
Test name
Test status
Simulation time 2527521380 ps
CPU time 2.31 seconds
Started May 23 12:56:46 PM PDT 24
Finished May 23 12:56:51 PM PDT 24
Peak memory 202052 kb
Host smart-a438899d-f772-4142-98b3-008e6a9a72b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587920334 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.587920334
Directory /workspace/41.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_smoke.1615724011
Short name T558
Test name
Test status
Simulation time 2119139501 ps
CPU time 2.02 seconds
Started May 23 12:56:45 PM PDT 24
Finished May 23 12:56:50 PM PDT 24
Peak memory 201872 kb
Host smart-bcc0968c-184d-4f55-8b3f-63938c008197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615724011 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.1615724011
Directory /workspace/41.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all.541384860
Short name T727
Test name
Test status
Simulation time 11552105904 ps
CPU time 4.99 seconds
Started May 23 12:56:43 PM PDT 24
Finished May 23 12:56:51 PM PDT 24
Peak memory 201588 kb
Host smart-17ec351b-2694-493d-a0aa-f17e8b34ef38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541384860 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_st
ress_all.541384860
Directory /workspace/41.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_alert_test.582551128
Short name T681
Test name
Test status
Simulation time 2034309051 ps
CPU time 1.76 seconds
Started May 23 12:56:43 PM PDT 24
Finished May 23 12:56:48 PM PDT 24
Peak memory 202072 kb
Host smart-6929dccf-e1c4-402c-896b-2caeba55c7ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582551128 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_tes
t.582551128
Directory /workspace/42.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.3059983977
Short name T442
Test name
Test status
Simulation time 3412369091 ps
CPU time 8.65 seconds
Started May 23 12:56:50 PM PDT 24
Finished May 23 12:57:01 PM PDT 24
Peak memory 201988 kb
Host smart-b4b5b4c2-e18d-4fbb-9f1f-516e36afd600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059983977 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.3
059983977
Directory /workspace/42.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect.1165990392
Short name T161
Test name
Test status
Simulation time 89758014671 ps
CPU time 60.27 seconds
Started May 23 12:56:44 PM PDT 24
Finished May 23 12:57:48 PM PDT 24
Peak memory 202316 kb
Host smart-690b4ea7-f776-493b-8168-0c26b54d8967
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165990392 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_c
trl_combo_detect.1165990392
Directory /workspace/42.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.2510474346
Short name T506
Test name
Test status
Simulation time 24597361730 ps
CPU time 16.76 seconds
Started May 23 12:56:44 PM PDT 24
Finished May 23 12:57:04 PM PDT 24
Peak memory 202336 kb
Host smart-1851c2a8-9294-4f1f-ba69-6889130e747f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510474346 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect_w
ith_pre_cond.2510474346
Directory /workspace/42.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.4230169410
Short name T379
Test name
Test status
Simulation time 3655220198 ps
CPU time 3.14 seconds
Started May 23 12:56:46 PM PDT 24
Finished May 23 12:56:52 PM PDT 24
Peak memory 202012 kb
Host smart-8324de10-d178-47e8-9409-93a12f4a4fda
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230169410 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_
ctrl_ec_pwr_on_rst.4230169410
Directory /workspace/42.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_edge_detect.905204515
Short name T7
Test name
Test status
Simulation time 2493333592 ps
CPU time 6.01 seconds
Started May 23 12:56:42 PM PDT 24
Finished May 23 12:56:49 PM PDT 24
Peak memory 202028 kb
Host smart-8f7b1f2b-74af-4723-81a8-25f46152edfd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905204515 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctr
l_edge_detect.905204515
Directory /workspace/42.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.2171104834
Short name T649
Test name
Test status
Simulation time 2631938959 ps
CPU time 2.12 seconds
Started May 23 12:56:44 PM PDT 24
Finished May 23 12:56:49 PM PDT 24
Peak memory 202032 kb
Host smart-24615a8b-49e9-4e35-a962-6edb30c75799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171104834 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.2171104834
Directory /workspace/42.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.479183037
Short name T148
Test name
Test status
Simulation time 2492086946 ps
CPU time 2.27 seconds
Started May 23 12:56:44 PM PDT 24
Finished May 23 12:56:50 PM PDT 24
Peak memory 202108 kb
Host smart-1d5d1ec1-f084-444b-8be3-ca79fcd1395a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479183037 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.479183037
Directory /workspace/42.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.3816717359
Short name T159
Test name
Test status
Simulation time 2185335670 ps
CPU time 1.97 seconds
Started May 23 12:56:47 PM PDT 24
Finished May 23 12:56:52 PM PDT 24
Peak memory 202096 kb
Host smart-30d81ff3-eaab-43eb-b204-ee9a8f5c3550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816717359 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.3816717359
Directory /workspace/42.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.1069079788
Short name T433
Test name
Test status
Simulation time 2515422638 ps
CPU time 6.11 seconds
Started May 23 12:56:46 PM PDT 24
Finished May 23 12:56:55 PM PDT 24
Peak memory 201908 kb
Host smart-4df17700-302a-4c7b-9311-1a4a503f6f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069079788 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.1069079788
Directory /workspace/42.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_smoke.1500961669
Short name T385
Test name
Test status
Simulation time 2113369410 ps
CPU time 5.99 seconds
Started May 23 12:56:44 PM PDT 24
Finished May 23 12:56:53 PM PDT 24
Peak memory 201972 kb
Host smart-fb63f086-cade-4a1a-8c76-ccc978566f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500961669 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.1500961669
Directory /workspace/42.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all.2294148649
Short name T514
Test name
Test status
Simulation time 312638329343 ps
CPU time 204.6 seconds
Started May 23 12:56:45 PM PDT 24
Finished May 23 01:00:13 PM PDT 24
Peak memory 202060 kb
Host smart-0f324786-a600-45e6-83dc-359c90e809cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294148649 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_s
tress_all.2294148649
Directory /workspace/42.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.520183986
Short name T301
Test name
Test status
Simulation time 11288310239 ps
CPU time 8.6 seconds
Started May 23 12:56:44 PM PDT 24
Finished May 23 12:56:55 PM PDT 24
Peak memory 202080 kb
Host smart-851e458f-77ea-40f6-a4ec-0216128c8857
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520183986 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_c
trl_ultra_low_pwr.520183986
Directory /workspace/42.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_alert_test.1380635320
Short name T517
Test name
Test status
Simulation time 2110840891 ps
CPU time 1.04 seconds
Started May 23 12:56:59 PM PDT 24
Finished May 23 12:57:03 PM PDT 24
Peak memory 202008 kb
Host smart-77d2861d-f8a7-4b17-928e-032b45667fef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380635320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_te
st.1380635320
Directory /workspace/43.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.2218958967
Short name T693
Test name
Test status
Simulation time 297839856077 ps
CPU time 778.2 seconds
Started May 23 12:56:45 PM PDT 24
Finished May 23 01:09:46 PM PDT 24
Peak memory 202064 kb
Host smart-2f2036d0-3408-4b54-91e6-113e4f250c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218958967 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.2
218958967
Directory /workspace/43.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect.1511583918
Short name T705
Test name
Test status
Simulation time 135494113238 ps
CPU time 172.08 seconds
Started May 23 12:56:58 PM PDT 24
Finished May 23 12:59:52 PM PDT 24
Peak memory 202200 kb
Host smart-a0939521-e3c1-4561-a1e5-bb8f02de2342
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511583918 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_c
trl_combo_detect.1511583918
Directory /workspace/43.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.3554073600
Short name T438
Test name
Test status
Simulation time 684121464285 ps
CPU time 1890.26 seconds
Started May 23 12:56:46 PM PDT 24
Finished May 23 01:28:19 PM PDT 24
Peak memory 202032 kb
Host smart-dec4d093-03da-4ac4-8d10-929209550df3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554073600 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ec_pwr_on_rst.3554073600
Directory /workspace/43.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_edge_detect.2104044419
Short name T173
Test name
Test status
Simulation time 4003825663 ps
CPU time 10.89 seconds
Started May 23 12:56:55 PM PDT 24
Finished May 23 12:57:09 PM PDT 24
Peak memory 202096 kb
Host smart-77c0df42-bc1e-47d3-b11c-98651b3b67c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104044419 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ct
rl_edge_detect.2104044419
Directory /workspace/43.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.2291957159
Short name T620
Test name
Test status
Simulation time 2637334966 ps
CPU time 2.34 seconds
Started May 23 12:56:42 PM PDT 24
Finished May 23 12:56:45 PM PDT 24
Peak memory 202032 kb
Host smart-6a248850-4fe6-4e0a-a9e7-37503ebb5c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291957159 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.2291957159
Directory /workspace/43.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.3816881564
Short name T475
Test name
Test status
Simulation time 2466743153 ps
CPU time 7.08 seconds
Started May 23 12:56:43 PM PDT 24
Finished May 23 12:56:52 PM PDT 24
Peak memory 202088 kb
Host smart-6a361ada-5c50-4565-b8a2-cfb2305cf5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816881564 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.3816881564
Directory /workspace/43.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.2747193877
Short name T592
Test name
Test status
Simulation time 2177044085 ps
CPU time 1.2 seconds
Started May 23 12:56:50 PM PDT 24
Finished May 23 12:56:54 PM PDT 24
Peak memory 201968 kb
Host smart-37d05d8c-141e-41ad-bedb-ed4a08701cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747193877 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.2747193877
Directory /workspace/43.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_override_test.3933409061
Short name T191
Test name
Test status
Simulation time 2516649041 ps
CPU time 4.71 seconds
Started May 23 12:56:43 PM PDT 24
Finished May 23 12:56:51 PM PDT 24
Peak memory 201552 kb
Host smart-c2f276c7-61fc-47b1-bd83-9f8721d1a392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933409061 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.3933409061
Directory /workspace/43.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_smoke.4076130683
Short name T420
Test name
Test status
Simulation time 2110953582 ps
CPU time 6.14 seconds
Started May 23 12:56:46 PM PDT 24
Finished May 23 12:56:55 PM PDT 24
Peak memory 201704 kb
Host smart-52ed3fb3-a97c-49f0-b3eb-463edc401bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076130683 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.4076130683
Directory /workspace/43.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all.2773246823
Short name T142
Test name
Test status
Simulation time 10776489166 ps
CPU time 22.05 seconds
Started May 23 12:56:58 PM PDT 24
Finished May 23 12:57:23 PM PDT 24
Peak memory 201952 kb
Host smart-f1d4317f-5279-4983-89c4-c300b0fcc8c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773246823 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_s
tress_all.2773246823
Directory /workspace/43.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.486848961
Short name T291
Test name
Test status
Simulation time 36056242784 ps
CPU time 92.44 seconds
Started May 23 12:57:00 PM PDT 24
Finished May 23 12:58:35 PM PDT 24
Peak memory 213524 kb
Host smart-219471da-6fde-430b-b269-a0dea2c1e28a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486848961 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all_with_rand_reset.486848961
Directory /workspace/43.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.1026120458
Short name T543
Test name
Test status
Simulation time 1312131432296 ps
CPU time 366.07 seconds
Started May 23 12:56:56 PM PDT 24
Finished May 23 01:03:04 PM PDT 24
Peak memory 202116 kb
Host smart-9f0d4ff3-5277-44e9-ae7a-78e76868deb5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026120458 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ultra_low_pwr.1026120458
Directory /workspace/43.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_alert_test.3094702334
Short name T716
Test name
Test status
Simulation time 2014562491 ps
CPU time 5.85 seconds
Started May 23 12:56:58 PM PDT 24
Finished May 23 12:57:07 PM PDT 24
Peak memory 201904 kb
Host smart-ebf37e37-71d7-434d-8541-36d637a324c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094702334 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_te
st.3094702334
Directory /workspace/44.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.1042555256
Short name T156
Test name
Test status
Simulation time 3035519642 ps
CPU time 2.78 seconds
Started May 23 12:56:59 PM PDT 24
Finished May 23 12:57:05 PM PDT 24
Peak memory 202016 kb
Host smart-52682275-6424-45e7-8453-29e4dcf82971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042555256 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.1
042555256
Directory /workspace/44.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect.1277782849
Short name T179
Test name
Test status
Simulation time 173932926686 ps
CPU time 111.99 seconds
Started May 23 12:56:57 PM PDT 24
Finished May 23 12:58:52 PM PDT 24
Peak memory 202256 kb
Host smart-14338d69-7469-480b-9306-443cb1fe473d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277782849 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_c
trl_combo_detect.1277782849
Directory /workspace/44.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.3165905674
Short name T724
Test name
Test status
Simulation time 35834171875 ps
CPU time 26.41 seconds
Started May 23 12:56:57 PM PDT 24
Finished May 23 12:57:26 PM PDT 24
Peak memory 202336 kb
Host smart-fc630036-ce3e-4a58-a7ae-373f54ad467b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165905674 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect_w
ith_pre_cond.3165905674
Directory /workspace/44.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.1140073236
Short name T160
Test name
Test status
Simulation time 4785723570 ps
CPU time 12.68 seconds
Started May 23 12:56:55 PM PDT 24
Finished May 23 12:57:10 PM PDT 24
Peak memory 201956 kb
Host smart-248d6f4e-7672-436e-bf4b-a04d36bceb64
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140073236 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ec_pwr_on_rst.1140073236
Directory /workspace/44.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_edge_detect.4218414154
Short name T499
Test name
Test status
Simulation time 3167540053 ps
CPU time 5.57 seconds
Started May 23 12:56:55 PM PDT 24
Finished May 23 12:57:03 PM PDT 24
Peak memory 202020 kb
Host smart-46767e9b-bd29-4302-ab07-a9d442a07266
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218414154 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ct
rl_edge_detect.4218414154
Directory /workspace/44.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.668886142
Short name T397
Test name
Test status
Simulation time 2622488693 ps
CPU time 2.48 seconds
Started May 23 12:56:58 PM PDT 24
Finished May 23 12:57:02 PM PDT 24
Peak memory 202072 kb
Host smart-39083537-7f49-4488-ab5c-d8dc89c44945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668886142 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.668886142
Directory /workspace/44.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.13703516
Short name T610
Test name
Test status
Simulation time 2481208524 ps
CPU time 6.69 seconds
Started May 23 12:56:54 PM PDT 24
Finished May 23 12:57:03 PM PDT 24
Peak memory 202024 kb
Host smart-bc49c7d7-1c4c-4f86-9726-24ce79ccb60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13703516 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.13703516
Directory /workspace/44.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.981420579
Short name T747
Test name
Test status
Simulation time 2128468188 ps
CPU time 1.95 seconds
Started May 23 12:56:54 PM PDT 24
Finished May 23 12:56:57 PM PDT 24
Peak memory 201900 kb
Host smart-99f4eed0-8b77-4c99-a8e8-7596bafe3762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981420579 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.981420579
Directory /workspace/44.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_override_test.513462132
Short name T299
Test name
Test status
Simulation time 2514239447 ps
CPU time 3.5 seconds
Started May 23 12:56:55 PM PDT 24
Finished May 23 12:57:00 PM PDT 24
Peak memory 202036 kb
Host smart-535a6114-97d9-4855-a320-fe186325ee92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513462132 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.513462132
Directory /workspace/44.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_smoke.2797045330
Short name T471
Test name
Test status
Simulation time 2159514780 ps
CPU time 1.19 seconds
Started May 23 12:56:58 PM PDT 24
Finished May 23 12:57:02 PM PDT 24
Peak memory 201916 kb
Host smart-03069a28-0551-4201-9b14-e1daf96588b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797045330 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.2797045330
Directory /workspace/44.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all.695926629
Short name T695
Test name
Test status
Simulation time 170102765936 ps
CPU time 443.2 seconds
Started May 23 12:56:57 PM PDT 24
Finished May 23 01:04:22 PM PDT 24
Peak memory 202256 kb
Host smart-77b272ab-c5f7-4aaa-bfa3-8982b13f32de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695926629 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_st
ress_all.695926629
Directory /workspace/44.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.3934747149
Short name T791
Test name
Test status
Simulation time 4787714545 ps
CPU time 2.14 seconds
Started May 23 12:56:55 PM PDT 24
Finished May 23 12:56:59 PM PDT 24
Peak memory 202000 kb
Host smart-47c92d5d-4ed2-438f-aa7f-8b020fa88773
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934747149 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ultra_low_pwr.3934747149
Directory /workspace/44.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_alert_test.2505979107
Short name T521
Test name
Test status
Simulation time 2018546383 ps
CPU time 3.13 seconds
Started May 23 12:56:55 PM PDT 24
Finished May 23 12:57:01 PM PDT 24
Peak memory 202016 kb
Host smart-04e0b813-a01e-44eb-a89b-4b22d17d548a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505979107 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_te
st.2505979107
Directory /workspace/45.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.1094641829
Short name T752
Test name
Test status
Simulation time 3557366332 ps
CPU time 9.28 seconds
Started May 23 12:56:59 PM PDT 24
Finished May 23 12:57:11 PM PDT 24
Peak memory 201996 kb
Host smart-1fb13c1e-4d4f-46a8-8993-70fced7b09aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094641829 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.1
094641829
Directory /workspace/45.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect.1120040412
Short name T653
Test name
Test status
Simulation time 145077469353 ps
CPU time 60.7 seconds
Started May 23 12:57:02 PM PDT 24
Finished May 23 12:58:05 PM PDT 24
Peak memory 202168 kb
Host smart-cb62c0e3-0d03-45ba-84e7-d8428d261582
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120040412 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_c
trl_combo_detect.1120040412
Directory /workspace/45.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.4268627800
Short name T110
Test name
Test status
Simulation time 2872857710 ps
CPU time 2.54 seconds
Started May 23 12:56:57 PM PDT 24
Finished May 23 12:57:01 PM PDT 24
Peak memory 202016 kb
Host smart-4f617e10-bc84-4afc-8b2f-cddc91abd22e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268627800 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_
ctrl_ec_pwr_on_rst.4268627800
Directory /workspace/45.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_edge_detect.4188716432
Short name T163
Test name
Test status
Simulation time 6204977402 ps
CPU time 8.17 seconds
Started May 23 12:57:00 PM PDT 24
Finished May 23 12:57:11 PM PDT 24
Peak memory 202096 kb
Host smart-d5f5a929-62aa-4704-8694-bb0a1b048998
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188716432 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ct
rl_edge_detect.4188716432
Directory /workspace/45.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.197735041
Short name T534
Test name
Test status
Simulation time 2635272876 ps
CPU time 1.87 seconds
Started May 23 12:56:55 PM PDT 24
Finished May 23 12:56:59 PM PDT 24
Peak memory 201996 kb
Host smart-478f05fc-382b-4d0e-9fa1-caa59d66a582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197735041 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.197735041
Directory /workspace/45.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.3796669852
Short name T421
Test name
Test status
Simulation time 2477359041 ps
CPU time 2.25 seconds
Started May 23 12:56:55 PM PDT 24
Finished May 23 12:56:59 PM PDT 24
Peak memory 202020 kb
Host smart-e3a4ad07-05da-43c6-805d-02806d1ebeee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796669852 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.3796669852
Directory /workspace/45.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.185437275
Short name T711
Test name
Test status
Simulation time 2022531050 ps
CPU time 5.68 seconds
Started May 23 12:56:56 PM PDT 24
Finished May 23 12:57:04 PM PDT 24
Peak memory 201876 kb
Host smart-ebd2d1d0-8c8e-4bc9-9afb-13e187e9dd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185437275 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.185437275
Directory /workspace/45.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.955973123
Short name T740
Test name
Test status
Simulation time 2549363038 ps
CPU time 1.72 seconds
Started May 23 12:56:55 PM PDT 24
Finished May 23 12:57:00 PM PDT 24
Peak memory 202112 kb
Host smart-b5b80f06-802f-4ab9-b4b6-1212ab696538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955973123 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.955973123
Directory /workspace/45.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_smoke.3380155268
Short name T607
Test name
Test status
Simulation time 2137891336 ps
CPU time 1.64 seconds
Started May 23 12:56:58 PM PDT 24
Finished May 23 12:57:02 PM PDT 24
Peak memory 201956 kb
Host smart-d6dc542d-d1b6-43c2-ab18-b9aff7ee9237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380155268 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.3380155268
Directory /workspace/45.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all.1898550775
Short name T596
Test name
Test status
Simulation time 6892159949 ps
CPU time 7.21 seconds
Started May 23 12:57:01 PM PDT 24
Finished May 23 12:57:10 PM PDT 24
Peak memory 202004 kb
Host smart-549aadf4-aacc-4012-bfef-f30b5bdc8aca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898550775 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_s
tress_all.1898550775
Directory /workspace/45.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.3463251607
Short name T763
Test name
Test status
Simulation time 111972272321 ps
CPU time 87.31 seconds
Started May 23 12:56:56 PM PDT 24
Finished May 23 12:58:25 PM PDT 24
Peak memory 218908 kb
Host smart-f3d9c815-fe38-4cd9-81f1-f650917bbf0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463251607 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all_with_rand_reset.3463251607
Directory /workspace/45.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.184697019
Short name T371
Test name
Test status
Simulation time 644407748225 ps
CPU time 66.52 seconds
Started May 23 12:56:56 PM PDT 24
Finished May 23 12:58:05 PM PDT 24
Peak memory 202108 kb
Host smart-ddffdbdb-afa1-4684-9dd5-7c615f649be9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184697019 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_c
trl_ultra_low_pwr.184697019
Directory /workspace/45.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_alert_test.169378999
Short name T682
Test name
Test status
Simulation time 2012578863 ps
CPU time 6.02 seconds
Started May 23 12:56:56 PM PDT 24
Finished May 23 12:57:04 PM PDT 24
Peak memory 201956 kb
Host smart-213abc49-c2f6-4922-92f1-c717c909963f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169378999 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_tes
t.169378999
Directory /workspace/46.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.2226135
Short name T675
Test name
Test status
Simulation time 3426348972 ps
CPU time 9.59 seconds
Started May 23 12:56:56 PM PDT 24
Finished May 23 12:57:08 PM PDT 24
Peak memory 202100 kb
Host smart-0ee409c2-19e8-41fa-ad94-27991e5d5c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226135 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.2226135
Directory /workspace/46.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect.771570957
Short name T787
Test name
Test status
Simulation time 62576587385 ps
CPU time 79.67 seconds
Started May 23 12:56:58 PM PDT 24
Finished May 23 12:58:21 PM PDT 24
Peak memory 202120 kb
Host smart-5225e6c7-410b-4684-892d-b64ac9ec830f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771570957 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ct
rl_combo_detect.771570957
Directory /workspace/46.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.3998907327
Short name T495
Test name
Test status
Simulation time 25846665832 ps
CPU time 18.82 seconds
Started May 23 12:56:58 PM PDT 24
Finished May 23 12:57:20 PM PDT 24
Peak memory 202348 kb
Host smart-e2c6ae45-5ccb-431a-a1aa-31e4ba94bde8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998907327 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect_w
ith_pre_cond.3998907327
Directory /workspace/46.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.1128707493
Short name T524
Test name
Test status
Simulation time 3507796749 ps
CPU time 9.42 seconds
Started May 23 12:57:00 PM PDT 24
Finished May 23 12:57:12 PM PDT 24
Peak memory 202080 kb
Host smart-b0de41a7-3c46-4114-8875-d65335e68339
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128707493 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_
ctrl_ec_pwr_on_rst.1128707493
Directory /workspace/46.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_edge_detect.3863431397
Short name T677
Test name
Test status
Simulation time 2884072214 ps
CPU time 2.62 seconds
Started May 23 12:56:56 PM PDT 24
Finished May 23 12:57:01 PM PDT 24
Peak memory 202016 kb
Host smart-6793c0a8-3a7e-4b2f-b521-fb18efa042db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863431397 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ct
rl_edge_detect.3863431397
Directory /workspace/46.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.380927163
Short name T474
Test name
Test status
Simulation time 2610140818 ps
CPU time 7.53 seconds
Started May 23 12:56:59 PM PDT 24
Finished May 23 12:57:09 PM PDT 24
Peak memory 202076 kb
Host smart-2ef4e417-5d7a-4ebc-bc6a-f13bd495a81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380927163 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.380927163
Directory /workspace/46.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.901859748
Short name T63
Test name
Test status
Simulation time 2487114090 ps
CPU time 2.43 seconds
Started May 23 12:57:01 PM PDT 24
Finished May 23 12:57:06 PM PDT 24
Peak memory 202000 kb
Host smart-72b79d33-2a91-478a-9b82-461c718ac641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901859748 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.901859748
Directory /workspace/46.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.1973137439
Short name T733
Test name
Test status
Simulation time 2245386109 ps
CPU time 3.63 seconds
Started May 23 12:56:57 PM PDT 24
Finished May 23 12:57:03 PM PDT 24
Peak memory 202048 kb
Host smart-194bc005-b551-4170-8876-391c502ee1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973137439 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.1973137439
Directory /workspace/46.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.3197581523
Short name T789
Test name
Test status
Simulation time 2510665936 ps
CPU time 7.09 seconds
Started May 23 12:56:58 PM PDT 24
Finished May 23 12:57:08 PM PDT 24
Peak memory 202112 kb
Host smart-eb84ebe1-2ca6-4eba-95c3-cc0dec9ce3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197581523 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.3197581523
Directory /workspace/46.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_smoke.1372804940
Short name T751
Test name
Test status
Simulation time 2155389219 ps
CPU time 1.28 seconds
Started May 23 12:56:59 PM PDT 24
Finished May 23 12:57:03 PM PDT 24
Peak memory 201992 kb
Host smart-49f4e298-5317-4b33-9d5f-d6d42ebc6113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372804940 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.1372804940
Directory /workspace/46.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all.164474232
Short name T212
Test name
Test status
Simulation time 14390095245 ps
CPU time 9.69 seconds
Started May 23 12:56:56 PM PDT 24
Finished May 23 12:57:08 PM PDT 24
Peak memory 202032 kb
Host smart-50a2676c-e4fe-4562-9dab-bb3bc6085ed5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164474232 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_st
ress_all.164474232
Directory /workspace/46.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.962936177
Short name T122
Test name
Test status
Simulation time 632395808892 ps
CPU time 138.55 seconds
Started May 23 12:56:58 PM PDT 24
Finished May 23 12:59:19 PM PDT 24
Peak memory 210652 kb
Host smart-d084ea55-66dd-4b08-8c25-041027ec12d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962936177 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all_with_rand_reset.962936177
Directory /workspace/46.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.3005598416
Short name T116
Test name
Test status
Simulation time 6682909817 ps
CPU time 2.03 seconds
Started May 23 12:56:58 PM PDT 24
Finished May 23 12:57:03 PM PDT 24
Peak memory 202032 kb
Host smart-a837a25e-3012-4863-86ee-926fa29b0abc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005598416 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_
ctrl_ultra_low_pwr.3005598416
Directory /workspace/46.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_alert_test.1226476225
Short name T439
Test name
Test status
Simulation time 2043312727 ps
CPU time 1.97 seconds
Started May 23 12:57:09 PM PDT 24
Finished May 23 12:57:14 PM PDT 24
Peak memory 201928 kb
Host smart-7d36a8b2-b836-4678-b6a3-ce3908f4642b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226476225 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_te
st.1226476225
Directory /workspace/47.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.1533819832
Short name T46
Test name
Test status
Simulation time 3619775907 ps
CPU time 2.72 seconds
Started May 23 12:56:58 PM PDT 24
Finished May 23 12:57:03 PM PDT 24
Peak memory 202076 kb
Host smart-d135c158-34fb-49af-bad0-a7268d39730a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533819832 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.1
533819832
Directory /workspace/47.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect.2856678985
Short name T638
Test name
Test status
Simulation time 38230654309 ps
CPU time 24.8 seconds
Started May 23 12:56:57 PM PDT 24
Finished May 23 12:57:24 PM PDT 24
Peak memory 202192 kb
Host smart-170b9346-d548-4b05-bd27-e01a3ec2ba4e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856678985 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_c
trl_combo_detect.2856678985
Directory /workspace/47.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2417101037
Short name T601
Test name
Test status
Simulation time 113031382118 ps
CPU time 79.62 seconds
Started May 23 12:57:09 PM PDT 24
Finished May 23 12:58:32 PM PDT 24
Peak memory 202412 kb
Host smart-f96688ff-b514-4c8e-8899-a13889a82849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417101037 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect_w
ith_pre_cond.2417101037
Directory /workspace/47.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.633972211
Short name T602
Test name
Test status
Simulation time 5041188353 ps
CPU time 1.64 seconds
Started May 23 12:56:56 PM PDT 24
Finished May 23 12:57:00 PM PDT 24
Peak memory 201960 kb
Host smart-40cafa72-7b0f-4f33-b3ed-26e4154015b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633972211 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_c
trl_ec_pwr_on_rst.633972211
Directory /workspace/47.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_edge_detect.1868559789
Short name T143
Test name
Test status
Simulation time 3720059197 ps
CPU time 5.34 seconds
Started May 23 12:57:08 PM PDT 24
Finished May 23 12:57:17 PM PDT 24
Peak memory 202108 kb
Host smart-81f86782-d4a0-4543-af3b-4fa22871dc80
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868559789 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ct
rl_edge_detect.1868559789
Directory /workspace/47.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.3337248008
Short name T668
Test name
Test status
Simulation time 2640550316 ps
CPU time 1.96 seconds
Started May 23 12:56:59 PM PDT 24
Finished May 23 12:57:04 PM PDT 24
Peak memory 202184 kb
Host smart-43fe8c3f-8a14-445c-a670-b3a72bd0d636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337248008 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.3337248008
Directory /workspace/47.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.1602524024
Short name T571
Test name
Test status
Simulation time 2449967712 ps
CPU time 4.41 seconds
Started May 23 12:56:58 PM PDT 24
Finished May 23 12:57:04 PM PDT 24
Peak memory 202112 kb
Host smart-fd122f5e-7824-464d-a6fe-3f1000ecdf27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602524024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.1602524024
Directory /workspace/47.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.510745479
Short name T200
Test name
Test status
Simulation time 2106339275 ps
CPU time 1.93 seconds
Started May 23 12:56:57 PM PDT 24
Finished May 23 12:57:01 PM PDT 24
Peak memory 201964 kb
Host smart-4a134a00-72cb-49e9-9848-a09b81a41f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510745479 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.510745479
Directory /workspace/47.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.1532130119
Short name T431
Test name
Test status
Simulation time 2511680395 ps
CPU time 7.15 seconds
Started May 23 12:56:59 PM PDT 24
Finished May 23 12:57:09 PM PDT 24
Peak memory 202200 kb
Host smart-fbecd453-9692-4071-a176-ca8f23a06e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532130119 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.1532130119
Directory /workspace/47.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_smoke.1349123732
Short name T434
Test name
Test status
Simulation time 2122104103 ps
CPU time 3.38 seconds
Started May 23 12:57:02 PM PDT 24
Finished May 23 12:57:07 PM PDT 24
Peak memory 201844 kb
Host smart-f1f9261d-ea12-430e-a299-764c1d0c0649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349123732 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.1349123732
Directory /workspace/47.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all.2517041025
Short name T624
Test name
Test status
Simulation time 11452789027 ps
CPU time 8.5 seconds
Started May 23 12:57:07 PM PDT 24
Finished May 23 12:57:17 PM PDT 24
Peak memory 202020 kb
Host smart-1729aa54-cf95-4709-bc6c-42ca1c6fe751
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517041025 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_s
tress_all.2517041025
Directory /workspace/47.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.2223173026
Short name T541
Test name
Test status
Simulation time 2721378770 ps
CPU time 5.9 seconds
Started May 23 12:56:58 PM PDT 24
Finished May 23 12:57:06 PM PDT 24
Peak memory 202004 kb
Host smart-6106f811-c0f1-44b6-bc11-b8accde2454d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223173026 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ultra_low_pwr.2223173026
Directory /workspace/47.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_alert_test.1035571841
Short name T464
Test name
Test status
Simulation time 2022064417 ps
CPU time 3.29 seconds
Started May 23 12:57:09 PM PDT 24
Finished May 23 12:57:16 PM PDT 24
Peak memory 201952 kb
Host smart-941f63fc-bc4b-4547-961f-ad53fb14c075
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035571841 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_te
st.1035571841
Directory /workspace/48.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.3630284873
Short name T470
Test name
Test status
Simulation time 3414984724 ps
CPU time 2.75 seconds
Started May 23 12:57:16 PM PDT 24
Finished May 23 12:57:19 PM PDT 24
Peak memory 202048 kb
Host smart-71d1d21a-d493-4c7a-931b-bee24bff7122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630284873 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.3
630284873
Directory /workspace/48.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect.992457600
Short name T250
Test name
Test status
Simulation time 127133349465 ps
CPU time 42.57 seconds
Started May 23 12:57:09 PM PDT 24
Finished May 23 12:57:56 PM PDT 24
Peak memory 202196 kb
Host smart-3799b264-c10b-4a6f-a695-fb758e7f682b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992457600 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ct
rl_combo_detect.992457600
Directory /workspace/48.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.2924179956
Short name T343
Test name
Test status
Simulation time 202145563676 ps
CPU time 514.85 seconds
Started May 23 12:57:16 PM PDT 24
Finished May 23 01:05:52 PM PDT 24
Peak memory 202172 kb
Host smart-3f551366-792d-4f4b-ac44-ad656b68168d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924179956 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect_w
ith_pre_cond.2924179956
Directory /workspace/48.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.36617260
Short name T441
Test name
Test status
Simulation time 2559805186 ps
CPU time 6.75 seconds
Started May 23 12:57:13 PM PDT 24
Finished May 23 12:57:21 PM PDT 24
Peak memory 201976 kb
Host smart-2baa981d-95a6-4aae-b400-6754495050f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36617260 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ct
rl_ec_pwr_on_rst.36617260
Directory /workspace/48.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_edge_detect.3085535128
Short name T630
Test name
Test status
Simulation time 5356488905 ps
CPU time 2.27 seconds
Started May 23 12:57:13 PM PDT 24
Finished May 23 12:57:17 PM PDT 24
Peak memory 201956 kb
Host smart-62531398-704c-4e5f-b00b-20774be76393
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085535128 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ct
rl_edge_detect.3085535128
Directory /workspace/48.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.306100040
Short name T450
Test name
Test status
Simulation time 2626378789 ps
CPU time 2.48 seconds
Started May 23 12:57:10 PM PDT 24
Finished May 23 12:57:16 PM PDT 24
Peak memory 202032 kb
Host smart-9fb06e9f-2b50-4053-b029-58697edd29c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306100040 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.306100040
Directory /workspace/48.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.2602028955
Short name T391
Test name
Test status
Simulation time 2492213793 ps
CPU time 2.09 seconds
Started May 23 12:57:13 PM PDT 24
Finished May 23 12:57:17 PM PDT 24
Peak memory 201956 kb
Host smart-f269587a-edd8-4934-a1aa-f2fc4aa86668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602028955 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.2602028955
Directory /workspace/48.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.312338621
Short name T734
Test name
Test status
Simulation time 2189933502 ps
CPU time 6.21 seconds
Started May 23 12:57:11 PM PDT 24
Finished May 23 12:57:20 PM PDT 24
Peak memory 202020 kb
Host smart-afb28a52-fad8-4f33-94a7-7e07504b08b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312338621 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.312338621
Directory /workspace/48.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.2217560670
Short name T663
Test name
Test status
Simulation time 2510902954 ps
CPU time 6.87 seconds
Started May 23 12:57:10 PM PDT 24
Finished May 23 12:57:20 PM PDT 24
Peak memory 202124 kb
Host smart-9f0c33e8-3274-4210-9c9b-d3592fc51362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217560670 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.2217560670
Directory /workspace/48.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_smoke.2427800650
Short name T411
Test name
Test status
Simulation time 2110537882 ps
CPU time 5.95 seconds
Started May 23 12:57:12 PM PDT 24
Finished May 23 12:57:20 PM PDT 24
Peak memory 201936 kb
Host smart-9de281b2-8eb2-4956-b00f-71cb433f5064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427800650 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.2427800650
Directory /workspace/48.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all.676154390
Short name T257
Test name
Test status
Simulation time 50595828571 ps
CPU time 124.99 seconds
Started May 23 12:57:11 PM PDT 24
Finished May 23 12:59:19 PM PDT 24
Peak memory 202388 kb
Host smart-1467cd73-e9b6-40cd-95d8-166608d87544
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676154390 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_st
ress_all.676154390
Directory /workspace/48.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_alert_test.4076873280
Short name T768
Test name
Test status
Simulation time 2068040127 ps
CPU time 1.27 seconds
Started May 23 12:57:16 PM PDT 24
Finished May 23 12:57:19 PM PDT 24
Peak memory 201916 kb
Host smart-96db616a-82d3-4f62-8757-cab81a72a6b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076873280 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_te
st.4076873280
Directory /workspace/49.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.4273525392
Short name T14
Test name
Test status
Simulation time 3215769647 ps
CPU time 8.96 seconds
Started May 23 12:57:11 PM PDT 24
Finished May 23 12:57:23 PM PDT 24
Peak memory 202156 kb
Host smart-46f3f38f-3fb9-4e1e-9065-f106dedae255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273525392 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.4
273525392
Directory /workspace/49.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect.802754846
Short name T361
Test name
Test status
Simulation time 82074460368 ps
CPU time 13.03 seconds
Started May 23 12:57:12 PM PDT 24
Finished May 23 12:57:27 PM PDT 24
Peak memory 202280 kb
Host smart-ea180fb4-85d0-4ad3-854d-722df49faeb8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802754846 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ct
rl_combo_detect.802754846
Directory /workspace/49.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.2994551242
Short name T254
Test name
Test status
Simulation time 27588974459 ps
CPU time 36.06 seconds
Started May 23 12:57:13 PM PDT 24
Finished May 23 12:57:51 PM PDT 24
Peak memory 202364 kb
Host smart-d0fcac5d-b8f8-4a0f-97aa-fcda37d34f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994551242 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect_w
ith_pre_cond.2994551242
Directory /workspace/49.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.486714727
Short name T709
Test name
Test status
Simulation time 644087158622 ps
CPU time 816.76 seconds
Started May 23 12:57:11 PM PDT 24
Finished May 23 01:10:51 PM PDT 24
Peak memory 202020 kb
Host smart-12a251fc-b65b-434a-bf13-05ee12f8239b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486714727 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_c
trl_ec_pwr_on_rst.486714727
Directory /workspace/49.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_edge_detect.4179366188
Short name T175
Test name
Test status
Simulation time 6210995553 ps
CPU time 4.27 seconds
Started May 23 12:57:08 PM PDT 24
Finished May 23 12:57:14 PM PDT 24
Peak memory 202016 kb
Host smart-bb58fb16-5e67-4322-88ce-19329342369e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179366188 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ct
rl_edge_detect.4179366188
Directory /workspace/49.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.1393678230
Short name T182
Test name
Test status
Simulation time 2653935876 ps
CPU time 1.52 seconds
Started May 23 12:57:18 PM PDT 24
Finished May 23 12:57:20 PM PDT 24
Peak memory 202104 kb
Host smart-9569ac7b-86e5-46a7-b4dc-5b74d371dc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393678230 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.1393678230
Directory /workspace/49.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.90801137
Short name T444
Test name
Test status
Simulation time 2457316355 ps
CPU time 6.72 seconds
Started May 23 12:57:10 PM PDT 24
Finished May 23 12:57:20 PM PDT 24
Peak memory 202100 kb
Host smart-26ec89c9-208a-44d4-945b-bfc8a3498062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90801137 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.90801137
Directory /workspace/49.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.18104125
Short name T106
Test name
Test status
Simulation time 2151732959 ps
CPU time 4 seconds
Started May 23 12:57:12 PM PDT 24
Finished May 23 12:57:18 PM PDT 24
Peak memory 202032 kb
Host smart-c17dfc9a-48be-4236-b20f-35333e9b2ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18104125 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.18104125
Directory /workspace/49.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.4271778465
Short name T739
Test name
Test status
Simulation time 2521536181 ps
CPU time 3.04 seconds
Started May 23 12:57:10 PM PDT 24
Finished May 23 12:57:16 PM PDT 24
Peak memory 202032 kb
Host smart-cb0c5a43-fd0c-44f7-802e-d6ca7fd8646d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271778465 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.4271778465
Directory /workspace/49.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_smoke.993740056
Short name T124
Test name
Test status
Simulation time 2122797744 ps
CPU time 1.94 seconds
Started May 23 12:57:10 PM PDT 24
Finished May 23 12:57:15 PM PDT 24
Peak memory 201960 kb
Host smart-8fbf597e-1f36-4d1b-a8cd-c3789b538495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993740056 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.993740056
Directory /workspace/49.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all.3454962230
Short name T207
Test name
Test status
Simulation time 7086622593 ps
CPU time 18.96 seconds
Started May 23 12:57:12 PM PDT 24
Finished May 23 12:57:33 PM PDT 24
Peak memory 202008 kb
Host smart-f694de2b-fa79-447d-aeb2-84fa95d4cc02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454962230 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_s
tress_all.3454962230
Directory /workspace/49.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.1967325035
Short name T99
Test name
Test status
Simulation time 59232948672 ps
CPU time 41.74 seconds
Started May 23 12:57:18 PM PDT 24
Finished May 23 12:58:00 PM PDT 24
Peak memory 202568 kb
Host smart-965ce467-5c91-49cb-a635-de4d7a6194fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967325035 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all_with_rand_reset.1967325035
Directory /workspace/49.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.2512298974
Short name T459
Test name
Test status
Simulation time 6950953228 ps
CPU time 5.94 seconds
Started May 23 12:57:18 PM PDT 24
Finished May 23 12:57:25 PM PDT 24
Peak memory 202100 kb
Host smart-4e0a1d86-340f-45f6-863b-281290cf4fb7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512298974 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ultra_low_pwr.2512298974
Directory /workspace/49.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_alert_test.3815921416
Short name T777
Test name
Test status
Simulation time 2016075080 ps
CPU time 3.06 seconds
Started May 23 12:54:30 PM PDT 24
Finished May 23 12:54:36 PM PDT 24
Peak memory 201932 kb
Host smart-e3789bba-9443-4485-b50a-02f5a5aa77a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815921416 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_tes
t.3815921416
Directory /workspace/5.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.772665148
Short name T731
Test name
Test status
Simulation time 3767296181 ps
CPU time 10.47 seconds
Started May 23 12:54:13 PM PDT 24
Finished May 23 12:54:25 PM PDT 24
Peak memory 202084 kb
Host smart-76d279f9-606b-4bd0-bfcb-26fd1eb0ca73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772665148 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.772665148
Directory /workspace/5.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect.765082662
Short name T259
Test name
Test status
Simulation time 135805048441 ps
CPU time 343.08 seconds
Started May 23 12:54:15 PM PDT 24
Finished May 23 01:00:00 PM PDT 24
Peak memory 202328 kb
Host smart-a7e4a715-453a-406a-b0fe-275650cea3b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765082662 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctr
l_combo_detect.765082662
Directory /workspace/5.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.1659996017
Short name T686
Test name
Test status
Simulation time 27853404218 ps
CPU time 18.89 seconds
Started May 23 12:54:12 PM PDT 24
Finished May 23 12:54:32 PM PDT 24
Peak memory 202384 kb
Host smart-77a0cb59-d760-4aae-ab81-1a6b33357b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659996017 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect_wi
th_pre_cond.1659996017
Directory /workspace/5.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.1300727027
Short name T236
Test name
Test status
Simulation time 3834588389 ps
CPU time 11.15 seconds
Started May 23 12:54:13 PM PDT 24
Finished May 23 12:54:26 PM PDT 24
Peak memory 202000 kb
Host smart-a8cbeb04-e310-4655-b4fd-617e651157ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300727027 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ec_pwr_on_rst.1300727027
Directory /workspace/5.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_edge_detect.1377425504
Short name T37
Test name
Test status
Simulation time 4384421795 ps
CPU time 2.76 seconds
Started May 23 12:54:12 PM PDT 24
Finished May 23 12:54:17 PM PDT 24
Peak memory 202036 kb
Host smart-ef6355b7-e88e-4ee9-9d3b-537772709ce1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377425504 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctr
l_edge_detect.1377425504
Directory /workspace/5.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.2764500731
Short name T376
Test name
Test status
Simulation time 2609748079 ps
CPU time 5.65 seconds
Started May 23 12:54:13 PM PDT 24
Finished May 23 12:54:21 PM PDT 24
Peak memory 202016 kb
Host smart-15c61de1-c60b-49bd-8231-eb6b702631cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764500731 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.2764500731
Directory /workspace/5.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.53644191
Short name T384
Test name
Test status
Simulation time 2489142650 ps
CPU time 2.27 seconds
Started May 23 12:54:11 PM PDT 24
Finished May 23 12:54:15 PM PDT 24
Peak memory 202020 kb
Host smart-f42e9ecb-890c-483f-b659-2143e28ff1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53644191 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.53644191
Directory /workspace/5.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.3387731876
Short name T774
Test name
Test status
Simulation time 2195558073 ps
CPU time 6.01 seconds
Started May 23 12:54:16 PM PDT 24
Finished May 23 12:54:23 PM PDT 24
Peak memory 202188 kb
Host smart-264a629b-d652-4944-b7b9-0622bd4b180b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387731876 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.3387731876
Directory /workspace/5.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_override_test.1872876258
Short name T631
Test name
Test status
Simulation time 2597907615 ps
CPU time 1.23 seconds
Started May 23 12:54:12 PM PDT 24
Finished May 23 12:54:15 PM PDT 24
Peak memory 202036 kb
Host smart-d99b6653-bd36-44b1-a9cd-30038623dcb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872876258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.1872876258
Directory /workspace/5.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_smoke.4074925790
Short name T104
Test name
Test status
Simulation time 2132933982 ps
CPU time 1.92 seconds
Started May 23 12:54:13 PM PDT 24
Finished May 23 12:54:17 PM PDT 24
Peak memory 201864 kb
Host smart-e95fa9f3-e68f-40cb-a419-c84485c0af6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074925790 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.4074925790
Directory /workspace/5.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all.3549484894
Short name T225
Test name
Test status
Simulation time 14378182777 ps
CPU time 40.6 seconds
Started May 23 12:54:25 PM PDT 24
Finished May 23 12:55:08 PM PDT 24
Peak memory 202020 kb
Host smart-a94011e4-584f-4167-9fe9-9a724cd0f6ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549484894 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_st
ress_all.3549484894
Directory /workspace/5.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.2591036807
Short name T8
Test name
Test status
Simulation time 4940864316 ps
CPU time 6.89 seconds
Started May 23 12:54:14 PM PDT 24
Finished May 23 12:54:23 PM PDT 24
Peak memory 202120 kb
Host smart-7ab14e90-adcc-44d5-976f-45a2b7e571d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591036807 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ultra_low_pwr.2591036807
Directory /workspace/5.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.3881669002
Short name T137
Test name
Test status
Simulation time 61940441712 ps
CPU time 175.67 seconds
Started May 23 12:57:18 PM PDT 24
Finished May 23 01:00:15 PM PDT 24
Peak memory 202280 kb
Host smart-892a037d-15f8-409b-80fa-ef279782451e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881669002 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.sysrst_ctrl_combo_detect_w
ith_pre_cond.3881669002
Directory /workspace/50.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.2664322348
Short name T369
Test name
Test status
Simulation time 61912988953 ps
CPU time 73.01 seconds
Started May 23 12:57:08 PM PDT 24
Finished May 23 12:58:22 PM PDT 24
Peak memory 202228 kb
Host smart-49824f10-adda-4e61-9944-8cf1a4b974e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664322348 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.sysrst_ctrl_combo_detect_w
ith_pre_cond.2664322348
Directory /workspace/51.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.2286576654
Short name T655
Test name
Test status
Simulation time 43651898947 ps
CPU time 66.66 seconds
Started May 23 12:57:12 PM PDT 24
Finished May 23 12:58:21 PM PDT 24
Peak memory 202224 kb
Host smart-3b5939ba-9d23-4e22-8c44-c6226b71d0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286576654 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.sysrst_ctrl_combo_detect_w
ith_pre_cond.2286576654
Directory /workspace/52.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.4042934022
Short name T728
Test name
Test status
Simulation time 23828168441 ps
CPU time 64.22 seconds
Started May 23 12:57:13 PM PDT 24
Finished May 23 12:58:19 PM PDT 24
Peak memory 202260 kb
Host smart-6d2bbf03-0e6d-4de8-afe6-2bb1b5bb19b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042934022 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.sysrst_ctrl_combo_detect_w
ith_pre_cond.4042934022
Directory /workspace/53.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.1162188185
Short name T360
Test name
Test status
Simulation time 64447958407 ps
CPU time 90.41 seconds
Started May 23 12:57:08 PM PDT 24
Finished May 23 12:58:42 PM PDT 24
Peak memory 202296 kb
Host smart-9f475e2f-be49-4bcf-8d9e-fa746e515644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162188185 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.sysrst_ctrl_combo_detect_w
ith_pre_cond.1162188185
Directory /workspace/54.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.1786307650
Short name T451
Test name
Test status
Simulation time 24828677849 ps
CPU time 67.53 seconds
Started May 23 12:57:14 PM PDT 24
Finished May 23 12:58:23 PM PDT 24
Peak memory 202236 kb
Host smart-52a4898e-0397-4a29-a86c-475f01595233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786307650 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.sysrst_ctrl_combo_detect_w
ith_pre_cond.1786307650
Directory /workspace/56.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.3744083306
Short name T784
Test name
Test status
Simulation time 36774568848 ps
CPU time 29.19 seconds
Started May 23 12:57:11 PM PDT 24
Finished May 23 12:57:43 PM PDT 24
Peak memory 202312 kb
Host smart-97df0b3f-75a5-4905-8b4b-87c107f8e437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744083306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.sysrst_ctrl_combo_detect_w
ith_pre_cond.3744083306
Directory /workspace/57.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.3509374435
Short name T34
Test name
Test status
Simulation time 95817510432 ps
CPU time 263.62 seconds
Started May 23 12:57:13 PM PDT 24
Finished May 23 01:01:38 PM PDT 24
Peak memory 202152 kb
Host smart-27bf8092-24fb-4f18-bb45-50e1d2608a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509374435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.sysrst_ctrl_combo_detect_w
ith_pre_cond.3509374435
Directory /workspace/58.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_alert_test.3268444366
Short name T723
Test name
Test status
Simulation time 2025525418 ps
CPU time 3.21 seconds
Started May 23 12:54:27 PM PDT 24
Finished May 23 12:54:33 PM PDT 24
Peak memory 202044 kb
Host smart-7dd5607d-3569-4460-a32a-92b76cab9bbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268444366 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_tes
t.3268444366
Directory /workspace/6.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.3305289763
Short name T140
Test name
Test status
Simulation time 3445457380 ps
CPU time 2.79 seconds
Started May 23 12:54:26 PM PDT 24
Finished May 23 12:54:32 PM PDT 24
Peak memory 202148 kb
Host smart-2eda1d17-4f41-4991-bdd5-794a3afa2ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305289763 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.3305289763
Directory /workspace/6.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect.2188870375
Short name T626
Test name
Test status
Simulation time 15464656971 ps
CPU time 41.41 seconds
Started May 23 12:54:27 PM PDT 24
Finished May 23 12:55:12 PM PDT 24
Peak memory 202188 kb
Host smart-54182b7d-f562-4aed-97d8-713e73457344
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188870375 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ct
rl_combo_detect.2188870375
Directory /workspace/6.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.299585509
Short name T357
Test name
Test status
Simulation time 44043502566 ps
CPU time 13.86 seconds
Started May 23 12:54:27 PM PDT 24
Finished May 23 12:54:44 PM PDT 24
Peak memory 202232 kb
Host smart-2c57beeb-fce1-4d23-863d-92e9b7c2267c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299585509 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect_wit
h_pre_cond.299585509
Directory /workspace/6.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.3805809960
Short name T383
Test name
Test status
Simulation time 4994968159 ps
CPU time 3.01 seconds
Started May 23 12:54:28 PM PDT 24
Finished May 23 12:54:34 PM PDT 24
Peak memory 202000 kb
Host smart-334a273e-5d1d-4e39-816d-97da9f78c18e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805809960 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ec_pwr_on_rst.3805809960
Directory /workspace/6.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_edge_detect.4136474922
Short name T239
Test name
Test status
Simulation time 2701979694 ps
CPU time 6.08 seconds
Started May 23 12:54:26 PM PDT 24
Finished May 23 12:54:36 PM PDT 24
Peak memory 201992 kb
Host smart-5d088c9a-716a-49bc-bc79-beff6d8ad61e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136474922 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctr
l_edge_detect.4136474922
Directory /workspace/6.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.508479574
Short name T409
Test name
Test status
Simulation time 2608059425 ps
CPU time 7.11 seconds
Started May 23 12:54:29 PM PDT 24
Finished May 23 12:54:40 PM PDT 24
Peak memory 202000 kb
Host smart-7d5923bd-f849-491a-b9fc-5b97d10ea56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508479574 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.508479574
Directory /workspace/6.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.3344536632
Short name T701
Test name
Test status
Simulation time 2462277367 ps
CPU time 2.21 seconds
Started May 23 12:54:27 PM PDT 24
Finished May 23 12:54:33 PM PDT 24
Peak memory 202036 kb
Host smart-eb411668-1f01-4547-b56c-745292844a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344536632 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.3344536632
Directory /workspace/6.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.1351317747
Short name T381
Test name
Test status
Simulation time 2199507536 ps
CPU time 1.13 seconds
Started May 23 12:54:28 PM PDT 24
Finished May 23 12:54:33 PM PDT 24
Peak memory 202088 kb
Host smart-b5532642-c7ac-4cb2-8e9f-544e684b15fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351317747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.1351317747
Directory /workspace/6.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.3963156271
Short name T690
Test name
Test status
Simulation time 2527970143 ps
CPU time 2.42 seconds
Started May 23 12:54:28 PM PDT 24
Finished May 23 12:54:34 PM PDT 24
Peak memory 202104 kb
Host smart-00d2bad0-b48f-4d23-9880-371490e3a01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963156271 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.3963156271
Directory /workspace/6.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_smoke.1556672429
Short name T707
Test name
Test status
Simulation time 2120128185 ps
CPU time 2.26 seconds
Started May 23 12:54:26 PM PDT 24
Finished May 23 12:54:32 PM PDT 24
Peak memory 201944 kb
Host smart-0ca8d66f-a1bc-47a4-bc8a-d7951f66af98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556672429 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.1556672429
Directory /workspace/6.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all.153948845
Short name T219
Test name
Test status
Simulation time 8583915432 ps
CPU time 7.04 seconds
Started May 23 12:54:24 PM PDT 24
Finished May 23 12:54:33 PM PDT 24
Peak memory 202128 kb
Host smart-1d723f59-3794-4f8b-8f8f-4f97071903b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153948845 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_str
ess_all.153948845
Directory /workspace/6.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.402267946
Short name T35
Test name
Test status
Simulation time 66529587722 ps
CPU time 23.87 seconds
Started May 23 12:54:28 PM PDT 24
Finished May 23 12:54:55 PM PDT 24
Peak memory 210752 kb
Host smart-40bbbf59-d995-4af7-96f2-d5ab6fc0d622
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402267946 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all_with_rand_reset.402267946
Directory /workspace/6.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.3185019691
Short name T758
Test name
Test status
Simulation time 688695473830 ps
CPU time 23.09 seconds
Started May 23 12:54:25 PM PDT 24
Finished May 23 12:54:50 PM PDT 24
Peak memory 202012 kb
Host smart-9f3b080d-70f9-43da-a2a3-c41719bc3c49
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185019691 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ultra_low_pwr.3185019691
Directory /workspace/6.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.4056233485
Short name T150
Test name
Test status
Simulation time 63838528591 ps
CPU time 91.93 seconds
Started May 23 12:57:09 PM PDT 24
Finished May 23 12:58:45 PM PDT 24
Peak memory 202368 kb
Host smart-f5ae715d-0ff8-4a86-a374-4c5345aa12f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056233485 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.sysrst_ctrl_combo_detect_w
ith_pre_cond.4056233485
Directory /workspace/60.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.2338642791
Short name T606
Test name
Test status
Simulation time 78349862235 ps
CPU time 189.42 seconds
Started May 23 12:57:08 PM PDT 24
Finished May 23 01:00:21 PM PDT 24
Peak memory 202384 kb
Host smart-49b4a897-3c1c-4f3e-b3a7-3174addc59df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338642791 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.sysrst_ctrl_combo_detect_w
ith_pre_cond.2338642791
Directory /workspace/61.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.152062459
Short name T17
Test name
Test status
Simulation time 26832248448 ps
CPU time 71.55 seconds
Started May 23 12:57:13 PM PDT 24
Finished May 23 12:58:26 PM PDT 24
Peak memory 202244 kb
Host smart-18660f71-9a39-40ab-b41c-5142ba280f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152062459 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.sysrst_ctrl_combo_detect_wi
th_pre_cond.152062459
Directory /workspace/62.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.72046915
Short name T340
Test name
Test status
Simulation time 119739547165 ps
CPU time 80.1 seconds
Started May 23 12:57:08 PM PDT 24
Finished May 23 12:58:32 PM PDT 24
Peak memory 202212 kb
Host smart-4ea0163a-8d1c-418a-934c-293807af9be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72046915 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.sysrst_ctrl_combo_detect_wit
h_pre_cond.72046915
Directory /workspace/63.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.805323745
Short name T356
Test name
Test status
Simulation time 56529994855 ps
CPU time 12.2 seconds
Started May 23 12:57:10 PM PDT 24
Finished May 23 12:57:26 PM PDT 24
Peak memory 202324 kb
Host smart-55431a8a-8a99-48ef-b530-2d76d76025a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805323745 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.sysrst_ctrl_combo_detect_wi
th_pre_cond.805323745
Directory /workspace/67.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.3287662541
Short name T352
Test name
Test status
Simulation time 53317420614 ps
CPU time 66.95 seconds
Started May 23 12:57:13 PM PDT 24
Finished May 23 12:58:22 PM PDT 24
Peak memory 202216 kb
Host smart-3245642c-2f0f-4d68-891a-dcb26d5d7098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287662541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_combo_detect_w
ith_pre_cond.3287662541
Directory /workspace/68.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.3670064020
Short name T753
Test name
Test status
Simulation time 26332372237 ps
CPU time 71.44 seconds
Started May 23 12:57:17 PM PDT 24
Finished May 23 12:58:30 PM PDT 24
Peak memory 202348 kb
Host smart-ecdd8db2-e093-4e4f-810b-bc725ac70ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670064020 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.sysrst_ctrl_combo_detect_w
ith_pre_cond.3670064020
Directory /workspace/69.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_alert_test.3483937586
Short name T155
Test name
Test status
Simulation time 2018836347 ps
CPU time 3.3 seconds
Started May 23 12:54:26 PM PDT 24
Finished May 23 12:54:33 PM PDT 24
Peak memory 201916 kb
Host smart-64d2a7be-2f15-40d3-a90f-d91db329b90f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483937586 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_tes
t.3483937586
Directory /workspace/7.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.1921153919
Short name T542
Test name
Test status
Simulation time 3597247867 ps
CPU time 2.49 seconds
Started May 23 12:54:26 PM PDT 24
Finished May 23 12:54:31 PM PDT 24
Peak memory 202084 kb
Host smart-a62c3f83-d9fe-44af-9a5e-daa1a3181452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921153919 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.1921153919
Directory /workspace/7.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect.4172440104
Short name T98
Test name
Test status
Simulation time 35879859578 ps
CPU time 8.82 seconds
Started May 23 12:54:26 PM PDT 24
Finished May 23 12:54:38 PM PDT 24
Peak memory 202188 kb
Host smart-d5e0b582-28cc-445b-b2ec-a05a26869e57
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172440104 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ct
rl_combo_detect.4172440104
Directory /workspace/7.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.4115846488
Short name T460
Test name
Test status
Simulation time 3963850228 ps
CPU time 1.18 seconds
Started May 23 12:54:28 PM PDT 24
Finished May 23 12:54:33 PM PDT 24
Peak memory 202012 kb
Host smart-67cc0373-fd83-4f29-a641-42c83e6a7942
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115846488 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_ec_pwr_on_rst.4115846488
Directory /workspace/7.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_edge_detect.2129928178
Short name T177
Test name
Test status
Simulation time 5024732215 ps
CPU time 3.16 seconds
Started May 23 12:54:26 PM PDT 24
Finished May 23 12:54:31 PM PDT 24
Peak memory 202096 kb
Host smart-52584ae3-5647-4fb2-a5dd-36fd0c6ac3e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129928178 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctr
l_edge_detect.2129928178
Directory /workspace/7.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.2834652008
Short name T579
Test name
Test status
Simulation time 2611583424 ps
CPU time 7.34 seconds
Started May 23 12:54:27 PM PDT 24
Finished May 23 12:54:38 PM PDT 24
Peak memory 202120 kb
Host smart-55abbdef-d835-40e3-afdf-371c64a17faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834652008 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.2834652008
Directory /workspace/7.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.258455486
Short name T563
Test name
Test status
Simulation time 2487438007 ps
CPU time 2.23 seconds
Started May 23 12:54:27 PM PDT 24
Finished May 23 12:54:32 PM PDT 24
Peak memory 201960 kb
Host smart-e9468f71-8aa8-4bcd-895c-c2f8b32dddc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258455486 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.258455486
Directory /workspace/7.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.295340757
Short name T580
Test name
Test status
Simulation time 2080063119 ps
CPU time 2.56 seconds
Started May 23 12:54:28 PM PDT 24
Finished May 23 12:54:35 PM PDT 24
Peak memory 201964 kb
Host smart-5bfad5c6-ac95-4173-8e24-20d8229f21df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295340757 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.295340757
Directory /workspace/7.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_override_test.1231716864
Short name T298
Test name
Test status
Simulation time 2511277125 ps
CPU time 7.17 seconds
Started May 23 12:54:27 PM PDT 24
Finished May 23 12:54:38 PM PDT 24
Peak memory 202104 kb
Host smart-c5268c79-7514-4f96-a011-b14946b78ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231716864 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.1231716864
Directory /workspace/7.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_smoke.1167894301
Short name T795
Test name
Test status
Simulation time 2109263215 ps
CPU time 6.02 seconds
Started May 23 12:54:26 PM PDT 24
Finished May 23 12:54:35 PM PDT 24
Peak memory 201864 kb
Host smart-67c3354f-23be-4a33-a74d-246139dc61bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167894301 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.1167894301
Directory /workspace/7.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all.2554366263
Short name T223
Test name
Test status
Simulation time 11423326923 ps
CPU time 8.33 seconds
Started May 23 12:54:29 PM PDT 24
Finished May 23 12:54:41 PM PDT 24
Peak memory 202000 kb
Host smart-4f69952f-a63e-479b-9e0d-f3d87bd26968
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554366263 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_st
ress_all.2554366263
Directory /workspace/7.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.3979985332
Short name T33
Test name
Test status
Simulation time 119324307045 ps
CPU time 61.6 seconds
Started May 23 12:57:13 PM PDT 24
Finished May 23 12:58:17 PM PDT 24
Peak memory 202160 kb
Host smart-8085117c-f412-4efe-9d6c-15e9ca032390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979985332 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.sysrst_ctrl_combo_detect_w
ith_pre_cond.3979985332
Directory /workspace/70.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.2692258802
Short name T253
Test name
Test status
Simulation time 68080315553 ps
CPU time 187.97 seconds
Started May 23 12:57:16 PM PDT 24
Finished May 23 01:00:25 PM PDT 24
Peak memory 202232 kb
Host smart-2f587ef8-8ae6-4e8a-9e52-81f922ba40cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692258802 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.sysrst_ctrl_combo_detect_w
ith_pre_cond.2692258802
Directory /workspace/71.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.1233987379
Short name T453
Test name
Test status
Simulation time 92310490082 ps
CPU time 230.56 seconds
Started May 23 12:57:08 PM PDT 24
Finished May 23 01:01:02 PM PDT 24
Peak memory 202260 kb
Host smart-fba99089-a9ea-4485-90d9-871bc5e19eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233987379 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.sysrst_ctrl_combo_detect_w
ith_pre_cond.1233987379
Directory /workspace/72.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.3785117210
Short name T766
Test name
Test status
Simulation time 38550460810 ps
CPU time 103.71 seconds
Started May 23 12:57:08 PM PDT 24
Finished May 23 12:58:56 PM PDT 24
Peak memory 202336 kb
Host smart-0d48fdb1-7ef8-49b7-b88c-4bac8c4db7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785117210 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.sysrst_ctrl_combo_detect_w
ith_pre_cond.3785117210
Directory /workspace/73.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.1472843406
Short name T508
Test name
Test status
Simulation time 119901151524 ps
CPU time 242.6 seconds
Started May 23 12:57:10 PM PDT 24
Finished May 23 01:01:16 PM PDT 24
Peak memory 202400 kb
Host smart-c403de51-0d6a-437d-b915-9caf92e55112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472843406 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.sysrst_ctrl_combo_detect_w
ith_pre_cond.1472843406
Directory /workspace/75.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.4055948481
Short name T346
Test name
Test status
Simulation time 90313906090 ps
CPU time 206.83 seconds
Started May 23 12:57:11 PM PDT 24
Finished May 23 01:00:40 PM PDT 24
Peak memory 202208 kb
Host smart-8bbbd645-036b-44ca-bce6-3a46d300e986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055948481 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.sysrst_ctrl_combo_detect_w
ith_pre_cond.4055948481
Directory /workspace/76.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.4147591458
Short name T249
Test name
Test status
Simulation time 34187150307 ps
CPU time 89.67 seconds
Started May 23 12:57:22 PM PDT 24
Finished May 23 12:58:53 PM PDT 24
Peak memory 202192 kb
Host smart-b3086c4b-fdc0-4e82-9659-d24e974f512d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147591458 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.sysrst_ctrl_combo_detect_w
ith_pre_cond.4147591458
Directory /workspace/77.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.1965208118
Short name T348
Test name
Test status
Simulation time 56885805272 ps
CPU time 13.46 seconds
Started May 23 12:57:21 PM PDT 24
Finished May 23 12:57:35 PM PDT 24
Peak memory 202324 kb
Host smart-e43257de-3aed-4789-b156-5820be6b0959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965208118 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.sysrst_ctrl_combo_detect_w
ith_pre_cond.1965208118
Directory /workspace/78.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.2090611433
Short name T228
Test name
Test status
Simulation time 26608043617 ps
CPU time 15.61 seconds
Started May 23 12:57:21 PM PDT 24
Finished May 23 12:57:38 PM PDT 24
Peak memory 202252 kb
Host smart-cd97b701-cb65-4129-8d59-54c652d4e19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090611433 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.sysrst_ctrl_combo_detect_w
ith_pre_cond.2090611433
Directory /workspace/79.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_alert_test.1727531172
Short name T794
Test name
Test status
Simulation time 2009793642 ps
CPU time 5.95 seconds
Started May 23 12:54:38 PM PDT 24
Finished May 23 12:54:45 PM PDT 24
Peak memory 201908 kb
Host smart-91fcd8ce-df83-4d53-9ae4-6f13db35b4e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727531172 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_tes
t.1727531172
Directory /workspace/8.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.1449206719
Short name T722
Test name
Test status
Simulation time 235905518087 ps
CPU time 157.03 seconds
Started May 23 12:54:40 PM PDT 24
Finished May 23 12:57:19 PM PDT 24
Peak memory 202152 kb
Host smart-1ad542d0-1234-4e99-95f6-fb12928e1fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449206719 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.1449206719
Directory /workspace/8.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect.2749391036
Short name T11
Test name
Test status
Simulation time 63883327811 ps
CPU time 42.66 seconds
Started May 23 12:54:44 PM PDT 24
Finished May 23 12:55:28 PM PDT 24
Peak memory 202236 kb
Host smart-679590dc-9789-4e66-a147-78c21701ec0f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749391036 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ct
rl_combo_detect.2749391036
Directory /workspace/8.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.500362104
Short name T26
Test name
Test status
Simulation time 28585101599 ps
CPU time 79 seconds
Started May 23 12:54:39 PM PDT 24
Finished May 23 12:56:00 PM PDT 24
Peak memory 202336 kb
Host smart-6f4769f9-6f32-4efc-a26a-b162c4b9e26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500362104 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect_wit
h_pre_cond.500362104
Directory /workspace/8.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.3872284817
Short name T720
Test name
Test status
Simulation time 4071072001 ps
CPU time 6.39 seconds
Started May 23 12:54:27 PM PDT 24
Finished May 23 12:54:37 PM PDT 24
Peak memory 202072 kb
Host smart-bdbaabb4-a985-4fb4-91ad-84fb7395cd28
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872284817 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_ec_pwr_on_rst.3872284817
Directory /workspace/8.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_edge_detect.1650070178
Short name T424
Test name
Test status
Simulation time 2840843985 ps
CPU time 5.68 seconds
Started May 23 12:54:39 PM PDT 24
Finished May 23 12:54:46 PM PDT 24
Peak memory 202116 kb
Host smart-b6708889-27c9-4ce4-bb48-4f2b5ab8fe9c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650070178 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctr
l_edge_detect.1650070178
Directory /workspace/8.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.2769727848
Short name T678
Test name
Test status
Simulation time 2634020517 ps
CPU time 2.17 seconds
Started May 23 12:54:26 PM PDT 24
Finished May 23 12:54:31 PM PDT 24
Peak memory 202032 kb
Host smart-06b1db48-b88f-4ad6-a652-69d59c2fa1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769727848 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.2769727848
Directory /workspace/8.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.2195379964
Short name T688
Test name
Test status
Simulation time 2482441627 ps
CPU time 2.31 seconds
Started May 23 12:54:27 PM PDT 24
Finished May 23 12:54:33 PM PDT 24
Peak memory 202120 kb
Host smart-493fed4f-be32-4a1d-bc46-883d13a33fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195379964 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.2195379964
Directory /workspace/8.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.2513932488
Short name T130
Test name
Test status
Simulation time 2051653810 ps
CPU time 5.59 seconds
Started May 23 12:54:28 PM PDT 24
Finished May 23 12:54:38 PM PDT 24
Peak memory 201872 kb
Host smart-f5a790ff-d6f1-4d61-be59-05fc11c546e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513932488 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.2513932488
Directory /workspace/8.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.3837441773
Short name T490
Test name
Test status
Simulation time 2527820899 ps
CPU time 3.05 seconds
Started May 23 12:54:26 PM PDT 24
Finished May 23 12:54:31 PM PDT 24
Peak memory 202052 kb
Host smart-89bdb9d9-d1f8-4c19-a4c0-6b657f9ef223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837441773 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.3837441773
Directory /workspace/8.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_smoke.1180013213
Short name T685
Test name
Test status
Simulation time 2136185993 ps
CPU time 1.88 seconds
Started May 23 12:54:26 PM PDT 24
Finished May 23 12:54:31 PM PDT 24
Peak memory 201940 kb
Host smart-2aef60e2-0bf4-45dd-8c09-6808b06787ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180013213 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.1180013213
Directory /workspace/8.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all.2709028836
Short name T167
Test name
Test status
Simulation time 10871637054 ps
CPU time 8.85 seconds
Started May 23 12:54:41 PM PDT 24
Finished May 23 12:54:51 PM PDT 24
Peak memory 202020 kb
Host smart-c761687a-51ef-4887-a122-4881ef1caacc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709028836 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_st
ress_all.2709028836
Directory /workspace/8.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.955722966
Short name T637
Test name
Test status
Simulation time 8834879673 ps
CPU time 24.87 seconds
Started May 23 12:54:43 PM PDT 24
Finished May 23 12:55:09 PM PDT 24
Peak memory 211924 kb
Host smart-31516df6-f306-41ab-9a01-a561a00298a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955722966 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all_with_rand_reset.955722966
Directory /workspace/8.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.2353185048
Short name T561
Test name
Test status
Simulation time 10496746904 ps
CPU time 2.82 seconds
Started May 23 12:54:40 PM PDT 24
Finished May 23 12:54:45 PM PDT 24
Peak memory 202168 kb
Host smart-7cc6b83b-025b-4761-8303-1e6c40ce078b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353185048 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_ultra_low_pwr.2353185048
Directory /workspace/8.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.784130626
Short name T92
Test name
Test status
Simulation time 37251772815 ps
CPU time 28.97 seconds
Started May 23 12:57:20 PM PDT 24
Finished May 23 12:57:50 PM PDT 24
Peak memory 202236 kb
Host smart-7ebca44f-c5f2-4056-a346-e2fa78da11db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784130626 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.sysrst_ctrl_combo_detect_wi
th_pre_cond.784130626
Directory /workspace/80.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.4139667063
Short name T507
Test name
Test status
Simulation time 21843330503 ps
CPU time 14.25 seconds
Started May 23 12:57:20 PM PDT 24
Finished May 23 12:57:35 PM PDT 24
Peak memory 202344 kb
Host smart-ab613d53-dd87-4a2c-a069-98cd898cdc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139667063 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.sysrst_ctrl_combo_detect_w
ith_pre_cond.4139667063
Directory /workspace/81.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.1194632249
Short name T652
Test name
Test status
Simulation time 98095305682 ps
CPU time 46.76 seconds
Started May 23 12:57:22 PM PDT 24
Finished May 23 12:58:11 PM PDT 24
Peak memory 202228 kb
Host smart-45b071e5-8180-4ad1-a595-16a9ed4a2f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194632249 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.sysrst_ctrl_combo_detect_w
ith_pre_cond.1194632249
Directory /workspace/82.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.3508815352
Short name T244
Test name
Test status
Simulation time 40112215221 ps
CPU time 27.35 seconds
Started May 23 12:57:21 PM PDT 24
Finished May 23 12:57:50 PM PDT 24
Peak memory 202256 kb
Host smart-6796cd68-af13-4785-a7d0-6f5e12aaf1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508815352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.sysrst_ctrl_combo_detect_w
ith_pre_cond.3508815352
Directory /workspace/84.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.1621758509
Short name T764
Test name
Test status
Simulation time 28331244418 ps
CPU time 71.79 seconds
Started May 23 12:57:22 PM PDT 24
Finished May 23 12:58:35 PM PDT 24
Peak memory 202272 kb
Host smart-00e9ba48-a79b-4e77-b772-f5e3d124dcf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621758509 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.sysrst_ctrl_combo_detect_w
ith_pre_cond.1621758509
Directory /workspace/85.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.1276884708
Short name T368
Test name
Test status
Simulation time 80251767099 ps
CPU time 46.87 seconds
Started May 23 12:57:21 PM PDT 24
Finished May 23 12:58:09 PM PDT 24
Peak memory 202292 kb
Host smart-4d42ad31-032b-4c88-8e19-a031c8c55947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276884708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.sysrst_ctrl_combo_detect_w
ith_pre_cond.1276884708
Directory /workspace/87.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.2896632691
Short name T516
Test name
Test status
Simulation time 31600115923 ps
CPU time 11.22 seconds
Started May 23 12:57:26 PM PDT 24
Finished May 23 12:57:39 PM PDT 24
Peak memory 202216 kb
Host smart-9d2d10df-48a7-4d60-a51e-68edfff149e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896632691 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.sysrst_ctrl_combo_detect_w
ith_pre_cond.2896632691
Directory /workspace/88.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.1541031972
Short name T702
Test name
Test status
Simulation time 43415948825 ps
CPU time 20.68 seconds
Started May 23 12:57:21 PM PDT 24
Finished May 23 12:57:43 PM PDT 24
Peak memory 202396 kb
Host smart-005c8554-b228-4c3f-9f7c-901c3b83aef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541031972 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.sysrst_ctrl_combo_detect_w
ith_pre_cond.1541031972
Directory /workspace/89.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_alert_test.1818177226
Short name T279
Test name
Test status
Simulation time 2034961851 ps
CPU time 1.93 seconds
Started May 23 12:54:39 PM PDT 24
Finished May 23 12:54:43 PM PDT 24
Peak memory 201936 kb
Host smart-e3bc7b0e-586d-4394-8590-556c2fb4f0db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818177226 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_tes
t.1818177226
Directory /workspace/9.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.3632320829
Short name T151
Test name
Test status
Simulation time 3372622262 ps
CPU time 8.68 seconds
Started May 23 12:54:42 PM PDT 24
Finished May 23 12:54:52 PM PDT 24
Peak memory 202164 kb
Host smart-48c35eb9-d092-40a9-a516-6eaa3d755328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632320829 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.3632320829
Directory /workspace/9.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect.1989633624
Short name T608
Test name
Test status
Simulation time 139775932341 ps
CPU time 368.29 seconds
Started May 23 12:54:41 PM PDT 24
Finished May 23 01:00:51 PM PDT 24
Peak memory 202188 kb
Host smart-61b5ebf2-ba25-40cd-b20f-69f13e08179b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989633624 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_combo_detect.1989633624
Directory /workspace/9.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.3811137395
Short name T484
Test name
Test status
Simulation time 1017993957590 ps
CPU time 196.05 seconds
Started May 23 12:54:39 PM PDT 24
Finished May 23 12:57:56 PM PDT 24
Peak memory 202096 kb
Host smart-60dbc334-fd74-42d8-b6bc-b1bf06fb4fb4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811137395 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_ec_pwr_on_rst.3811137395
Directory /workspace/9.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_edge_detect.3395250164
Short name T70
Test name
Test status
Simulation time 3243232117 ps
CPU time 6.45 seconds
Started May 23 12:54:41 PM PDT 24
Finished May 23 12:54:50 PM PDT 24
Peak memory 201992 kb
Host smart-fb28b05e-d350-400f-a588-d9bd341a786c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395250164 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctr
l_edge_detect.3395250164
Directory /workspace/9.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.2265156926
Short name T698
Test name
Test status
Simulation time 2828514543 ps
CPU time 1.11 seconds
Started May 23 12:54:40 PM PDT 24
Finished May 23 12:54:44 PM PDT 24
Peak memory 202008 kb
Host smart-b5b65d7a-c86e-4145-b47f-87a75f2580ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265156926 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.2265156926
Directory /workspace/9.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.1556890991
Short name T756
Test name
Test status
Simulation time 2462870731 ps
CPU time 4.73 seconds
Started May 23 12:54:42 PM PDT 24
Finished May 23 12:54:48 PM PDT 24
Peak memory 202088 kb
Host smart-e99103e0-e83a-4909-bbc3-b4bffc844a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556890991 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.1556890991
Directory /workspace/9.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.2013547678
Short name T704
Test name
Test status
Simulation time 2328887211 ps
CPU time 1.12 seconds
Started May 23 12:54:42 PM PDT 24
Finished May 23 12:54:45 PM PDT 24
Peak memory 201968 kb
Host smart-4efd9d37-e290-4ecf-9e85-8edcffb7cfad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013547678 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.2013547678
Directory /workspace/9.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.2642433081
Short name T127
Test name
Test status
Simulation time 2509367703 ps
CPU time 7.41 seconds
Started May 23 12:54:40 PM PDT 24
Finished May 23 12:54:49 PM PDT 24
Peak memory 202032 kb
Host smart-90e05da8-c188-46c4-9011-cf183babd3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642433081 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.2642433081
Directory /workspace/9.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_smoke.3715442882
Short name T590
Test name
Test status
Simulation time 2147880652 ps
CPU time 1.33 seconds
Started May 23 12:54:43 PM PDT 24
Finished May 23 12:54:45 PM PDT 24
Peak memory 202084 kb
Host smart-5a8682e6-ec36-4d70-a886-226afbac4ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715442882 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.3715442882
Directory /workspace/9.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all.1087529884
Short name T635
Test name
Test status
Simulation time 150921924694 ps
CPU time 196.44 seconds
Started May 23 12:54:40 PM PDT 24
Finished May 23 12:57:58 PM PDT 24
Peak memory 202248 kb
Host smart-c8b41225-b120-4f3a-a05c-13422b9cd1c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087529884 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_st
ress_all.1087529884
Directory /workspace/9.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.4281768300
Short name T215
Test name
Test status
Simulation time 56785694182 ps
CPU time 153.45 seconds
Started May 23 12:54:44 PM PDT 24
Finished May 23 12:57:18 PM PDT 24
Peak memory 210608 kb
Host smart-4f0285c3-2eef-4fdb-99be-ee3d26e14343
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281768300 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all_with_rand_reset.4281768300
Directory /workspace/9.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.2312614971
Short name T55
Test name
Test status
Simulation time 6224201806 ps
CPU time 4.32 seconds
Started May 23 12:54:41 PM PDT 24
Finished May 23 12:54:47 PM PDT 24
Peak memory 202028 kb
Host smart-a088d002-8050-4395-a092-01d312f81cf3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312614971 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_ultra_low_pwr.2312614971
Directory /workspace/9.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.3465190510
Short name T72
Test name
Test status
Simulation time 24078591551 ps
CPU time 63.43 seconds
Started May 23 12:57:22 PM PDT 24
Finished May 23 12:58:27 PM PDT 24
Peak memory 202280 kb
Host smart-50de629f-b662-403a-acee-a6262817c868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465190510 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.sysrst_ctrl_combo_detect_w
ith_pre_cond.3465190510
Directory /workspace/90.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.759474703
Short name T194
Test name
Test status
Simulation time 65249629623 ps
CPU time 141.58 seconds
Started May 23 12:57:22 PM PDT 24
Finished May 23 12:59:45 PM PDT 24
Peak memory 202264 kb
Host smart-e91392cc-3a94-4181-9a46-4f2dcd9d2e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759474703 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.sysrst_ctrl_combo_detect_wi
th_pre_cond.759474703
Directory /workspace/91.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.3738698473
Short name T91
Test name
Test status
Simulation time 27084122486 ps
CPU time 33.93 seconds
Started May 23 12:57:22 PM PDT 24
Finished May 23 12:57:57 PM PDT 24
Peak memory 202244 kb
Host smart-d70a48a1-8184-492c-ba91-522a60e7ed0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738698473 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.sysrst_ctrl_combo_detect_w
ith_pre_cond.3738698473
Directory /workspace/92.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.4028019526
Short name T519
Test name
Test status
Simulation time 74097181315 ps
CPU time 170.39 seconds
Started May 23 12:57:22 PM PDT 24
Finished May 23 01:00:14 PM PDT 24
Peak memory 202344 kb
Host smart-d9f486e5-54e7-49ac-af4b-4a1c6f2156a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028019526 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.sysrst_ctrl_combo_detect_w
ith_pre_cond.4028019526
Directory /workspace/93.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.639548286
Short name T93
Test name
Test status
Simulation time 25831992891 ps
CPU time 70.85 seconds
Started May 23 12:57:21 PM PDT 24
Finished May 23 12:58:33 PM PDT 24
Peak memory 202368 kb
Host smart-969a52b5-2545-49cb-9e04-a33748b3660e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639548286 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.sysrst_ctrl_combo_detect_wi
th_pre_cond.639548286
Directory /workspace/95.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.1544049404
Short name T413
Test name
Test status
Simulation time 26590259324 ps
CPU time 29.65 seconds
Started May 23 12:57:23 PM PDT 24
Finished May 23 12:57:54 PM PDT 24
Peak memory 202236 kb
Host smart-d6a6b7e5-c734-474a-8204-51a2beee9fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544049404 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.sysrst_ctrl_combo_detect_w
ith_pre_cond.1544049404
Directory /workspace/97.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.4256809262
Short name T75
Test name
Test status
Simulation time 70766635733 ps
CPU time 176.55 seconds
Started May 23 12:57:23 PM PDT 24
Finished May 23 01:00:22 PM PDT 24
Peak memory 202288 kb
Host smart-017e1fc1-49c4-406b-8fb0-30cc5e497c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256809262 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.sysrst_ctrl_combo_detect_w
ith_pre_cond.4256809262
Directory /workspace/99.sysrst_ctrl_combo_detect_with_pre_cond/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%