Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1826

1

T4

15

T6

24

T7

3

auto[1]

596

1

T4

6

T7

5

T9

1

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1925

1

T4

16

T6

24

T7

8

auto[1]

497

1

T4

5

T9

13

T10

9

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1761

1

T4

6

T6

18

T7

5

auto[1]

661

1

T4

15

T6

6

T7

3

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1994

1

T4

15

T6

24

T9

12

auto[1]

428

1

T4

6

T7

8

T9

1

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2238

1

T4

21

T6

24

T7

8

auto[1]

184

1

T45

7

T47

5

T34

5

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2220

1

T4

21

T6

18

T7

8

auto[1]

202

1

T6

6

T45

7

T47

5

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2258

1

T4

21

T6

24

T7

8

auto[1]

164

1

T86

10

T84

6

T252

6

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2215

1

T4

21

T6

24

T7

8

auto[1]

207

1

T11

2

T45

5

T46

10

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2237

1

T4

21

T6

24

T7

8

auto[1]

185

1

T11

5

T45

5

T46

1

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1850

1

T4

21

T6

24

T7

8

auto[1]

572

1

T9

8

T10

9

T45

7

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	868	1			T4	21		T7	8		T9	13
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	31	1			T243	8		T361	1		T362	2
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	70	1			T11	2		T46	1		T363	2
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	7	1			T364	7		-	-		-	-
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	55	1			T46	10		T252	7		T353	4
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	34	1			T255	2		T243	4		T342	9
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	16	1			T11	1		T45	5		T142	4
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	8	1			T365	1		T215	7		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	41	1			T86	9		T252	6		T272	3
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	9	1			T364	1		T366	7		T367	1
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	22	1			T243	3		T353	3		T352	1
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	11	1			T104	2		T368	7		T342	2
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	19	1			T261	7		T272	1		T369	4
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	1	1			T243	1		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	3	1			T86	1		T353	2		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[1]	1	1			T366	1		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	48	1			T6	6		T252	6		T272	6
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	33	1			T45	7		T47	5		T34	5
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	18	1			T86	2		T364	6		T370	2
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	4	1			T215	4		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	15	1			T104	3		T365	2		T370	2
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	18	1			T371	7		T342	6		T365	1
auto[1]	auto[0]	auto[1]	auto[1]	auto[1]	6	1			T342	3		T215	3		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	34	1			T261	4		T255	11		T366	5
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	2	1			T371	2		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	1	1			T261	1		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

96

1

T46

6

T126

13

T65

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

110

1

T45

7

T126

11

T65

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

53

1

T33

5

T204

8

T44

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

67

1

T101

5

T220

10

T261

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

73

1

T4

6

T7

5

T126

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

40

1

T252

6

T105

7

T165

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

24

1

T126

2

T204

2

T44

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

182

1

T4

10

T6

6

T34

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

74

1

T45

5

T39

7

T372

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

75

1

T47

5

T35

3

T371

11

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

25

1

T113

2

T263

4

T221

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

38

1

T7

3

T101

1

T181

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

29

1

T10

2

T113

1

T267

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

31

1

T35

3

T113

3

T267

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

11

1

T96

2

T263

1

T101

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

73

1

T35

11

T86

9

T344

11

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

86

1

T204

9

T101

1

T139

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

77

1

T9

7

T10

9

T346

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

6

1

T272

1

T345

3

T264

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

36

1

T275

3

T44

4

T139

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

5

1

T266

5

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

10

1

T93

1

T346

3

T252

6

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

4

1

T9

1

T139

1

T220

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

56

1

T4

5

T9

5

T35

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

17

1

T11

3

T33

1

T142

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

28

1

T344

8

T243

4

T347

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

15

1

T46

5

T348

2

T118

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

9

1

T343

2

T139

3

T118

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

9

1

T345

1

T363

1

T268

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

7

1

T348

2

T373

2

T374

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

9

1

T267

2

T242

1

T347

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded