Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1089

1

T3

9

T69

10

T22

8

auto[1]

1120

1

T3

11

T69

10

T22

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

523

1

T3

5

T69

5

T22

5

from_0to1

513

1

T3

4

T69

5

T22

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1099

1

T3

10

T69

8

T22

9

auto[1]

1110

1

T3

10

T69

12

T22

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1128

1

T3

13

T69

10

T22

12

auto[1]

1081

1

T3

7

T69

10

T22

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T3

2

T382

1

T116

1

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T22

2

T71

1

T227

1

auto[0]

from_1to0

auto[1]

auto[0]

73

1

T3

1

T69

1

T71

1

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T3

2

T22

1

T71

1

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T3

2

T22

1

T111

1

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T22

1

T116

1

T312

2

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T69

1

T71

1

T227

1

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T69

2

T71

1

T382

1

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T69

1

T382

2

T227

1

auto[1]

from_1to0

auto[0]

auto[1]

64

1

T69

2

T76

1

T382

1

auto[1]

from_1to0

auto[1]

auto[0]

59

1

T22

2

T71

1

T111

1

auto[1]

from_1to0

auto[1]

auto[1]

75

1

T69

1

T111

2

T116

2

auto[1]

from_0to1

auto[0]

auto[0]

62

1

T22

2

T71

1

T76

2

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T382

1

T111

1

T383

1

auto[1]

from_0to1

auto[1]

auto[0]

73

1

T3

1

T69

1

T22

1

auto[1]

from_0to1

auto[1]

auto[1]

61

1

T3

1

T69

1

T76

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1054

1

T3

10

T69

8

T22

9

auto[1]

1155

1

T3

10

T69

12

T22

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

533

1

T3

5

T69

6

T22

5

from_0to1

545

1

T3

5

T69

5

T22

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1097

1

T3

7

T69

10

T22

9

auto[1]

1112

1

T3

13

T69

10

T22

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1110

1

T3

9

T69

8

T22

12

auto[1]

1099

1

T3

11

T69

12

T22

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

80

1

T3

1

T69

1

T71

2

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T22

1

T111

1

T312

2

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T69

2

T71

1

T382

1

auto[0]

from_1to0

auto[1]

auto[1]

56

1

T3

1

T76

1

T227

1

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T22

1

T76

2

T111

1

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T227

3

T383

3

T68

1

auto[0]

from_0to1

auto[1]

auto[0]

69

1

T3

2

T22

1

T71

1

auto[0]

from_0to1

auto[1]

auto[1]

76

1

T3

1

T69

1

T71

1

auto[1]

from_1to0

auto[0]

auto[0]

66

1

T76

1

T382

1

T116

1

auto[1]

from_1to0

auto[0]

auto[1]

69

1

T3

2

T69

1

T76

1

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T3

1

T22

3

T227

1

auto[1]

from_1to0

auto[1]

auto[1]

72

1

T69

2

T22

1

T71

1

auto[1]

from_0to1

auto[0]

auto[0]

81

1

T3

1

T69

1

T227

1

auto[1]

from_0to1

auto[0]

auto[1]

59

1

T69

1

T22

1

T71

1

auto[1]

from_0to1

auto[1]

auto[0]

67

1

T69

1

T22

1

T76

1

auto[1]

from_0to1

auto[1]

auto[1]

70

1

T3

1

T69

1

T22

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1121

1

T3

14

T69

11

T22

9

auto[1]

1088

1

T3

6

T69

9

T22

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

549

1

T3

3

T69

6

T22

7

from_0to1

544

1

T3

4

T69

6

T22

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1084

1

T3

10

T69

12

T22

9

auto[1]

1125

1

T3

10

T69

8

T22

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1087

1

T3

9

T69

9

T22

8

auto[1]

1122

1

T3

11

T69

11

T22

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

72

1

T382

1

T111

1

T116

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T69

3

T71

1

T76

1

auto[0]

from_1to0

auto[1]

auto[0]

58

1

T22

1

T382

1

T111

2

auto[0]

from_1to0

auto[1]

auto[1]

70

1

T3

2

T76

1

T116

1

auto[0]

from_0to1

auto[0]

auto[0]

78

1

T3

1

T22

2

T76

1

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T69

2

T382

1

T65

1

auto[0]

from_0to1

auto[1]

auto[0]

48

1

T71

1

T111

1

T227

1

auto[0]

from_0to1

auto[1]

auto[1]

87

1

T22

3

T71

1

T76

2

auto[1]

from_1to0

auto[0]

auto[0]

74

1

T3

1

T69

1

T22

1

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T22

2

T71

1

T382

2

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T22

1

T76

2

T382

1

auto[1]

from_1to0

auto[1]

auto[1]

85

1

T69

2

T22

2

T71

2

auto[1]

from_0to1

auto[0]

auto[0]

69

1

T69

2

T382

2

T116

3

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T69

1

T71

1

T76

1

auto[1]

from_0to1

auto[1]

auto[0]

63

1

T3

1

T71

2

T116

1

auto[1]

from_0to1

auto[1]

auto[1]

71

1

T3

2

T69

1

T22

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1091

1

T3

8

T69

6

T22

9

auto[1]

1118

1

T3

12

T69

14

T22

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

542

1

T3

5

T69

6

T22

4

from_0to1

536

1

T3

5

T69

6

T22

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1071

1

T3

15

T69

8

T22

10

auto[1]

1138

1

T3

5

T69

12

T22

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1094

1

T3

8

T69

12

T22

9

auto[1]

1115

1

T3

12

T69

8

T22

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

50

1

T382

1

T116

2

T65

4

auto[0]

from_1to0

auto[0]

auto[1]

65

1

T3

2

T69

1

T22

1

auto[0]

from_1to0

auto[1]

auto[0]

76

1

T22

1

T71

1

T111

2

auto[0]

from_1to0

auto[1]

auto[1]

75

1

T3

1

T227

1

T312

1

auto[0]

from_0to1

auto[0]

auto[0]

53

1

T69

1

T71

1

T382

1

auto[0]

from_0to1

auto[0]

auto[1]

65

1

T69

1

T71

1

T382

1

auto[0]

from_0to1

auto[1]

auto[0]

76

1

T69

1

T22

2

T71

1

auto[0]

from_0to1

auto[1]

auto[1]

70

1

T116

1

T227

1

T312

1

auto[1]

from_1to0

auto[0]

auto[0]

74

1

T3

1

T69

3

T76

1

auto[1]

from_1to0

auto[0]

auto[1]

65

1

T3

1

T22

1

T76

1

auto[1]

from_1to0

auto[1]

auto[0]

80

1

T69

1

T71

2

T76

1

auto[1]

from_1to0

auto[1]

auto[1]

57

1

T69

1

T22

1

T382

1

auto[1]

from_0to1

auto[0]

auto[0]

72

1

T3

1

T69

1

T22

1

auto[1]

from_0to1

auto[0]

auto[1]

59

1

T3

1

T71

1

T76

1

auto[1]

from_0to1

auto[1]

auto[0]

63

1

T3

1

T69

2

T382

1

auto[1]

from_0to1

auto[1]

auto[1]

78

1

T3

2

T22

1

T382

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1138

1

T3

10

T69

10

T22

7

auto[1]

1071

1

T3

10

T69

10

T22

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

532

1

T3

4

T69

5

T22

5

from_0to1

528

1

T3

5

T69

4

T22

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1120

1

T3

10

T69

10

T22

7

auto[1]

1089

1

T3

10

T69

10

T22

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1098

1

T3

13

T69

9

T22

8

auto[1]

1111

1

T3

7

T69

11

T22

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

68

1

T3

1

T76

1

T111

2

auto[0]

from_1to0

auto[0]

auto[1]

76

1

T22

1

T382

1

T111

1

auto[0]

from_1to0

auto[1]

auto[0]

62

1

T69

2

T382

1

T227

1

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T22

1

T382

1

T383

1

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T69

2

T22

1

T71

2

auto[0]

from_0to1

auto[0]

auto[1]

76

1

T3

1

T69

1

T116

2

auto[0]

from_0to1

auto[1]

auto[0]

63

1

T71

1

T382

2

T227

1

auto[0]

from_0to1

auto[1]

auto[1]

71

1

T3

1

T22

2

T382

1

auto[1]

from_1to0

auto[0]

auto[0]

73

1

T3

3

T69

1

T71

1

auto[1]

from_1to0

auto[0]

auto[1]

67

1

T69

1

T71

1

T76

2

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T69

1

T22

1

T382

1

auto[1]

from_1to0

auto[1]

auto[1]

59

1

T22

2

T71

1

T111

1

auto[1]

from_0to1

auto[0]

auto[0]

68

1

T3

1

T22

1

T382

1

auto[1]

from_0to1

auto[0]

auto[1]

57

1

T111

3

T227

1

T312

1

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T22

2

T76

2

T116

1

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T3

2

T69

1

T382

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1100

1

T3

7

T69

10

T22

9

auto[1]

1109

1

T3

13

T69

10

T22

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

512

1

T3

3

T69

5

T22

4

from_0to1

518

1

T3

3

T69

6

T22

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1099

1

T3

9

T69

13

T22

9

auto[1]

1110

1

T3

11

T69

7

T22

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1116

1

T3

9

T69

11

T22

9

auto[1]

1093

1

T3

11

T69

9

T22

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

69

1

T3

1

T69

2

T76

1

auto[0]

from_1to0

auto[0]

auto[1]

55

1

T69

1

T22

1

T65

4

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T69

1

T22

1

T71

3

auto[0]

from_1to0

auto[1]

auto[1]

63

1

T3

1

T71

1

T116

1

auto[0]

from_0to1

auto[0]

auto[0]

40

1

T76

2

T116

1

T227

1

auto[0]

from_0to1

auto[0]

auto[1]

74

1

T22

1

T71

1

T382

1

auto[0]

from_0to1

auto[1]

auto[0]

60

1

T3

1

T69

1

T111

1

auto[0]

from_0to1

auto[1]

auto[1]

68

1

T69

1

T22

1

T71

1

auto[1]

from_1to0

auto[0]

auto[0]

82

1

T3

1

T69

1

T22

1

auto[1]

from_1to0

auto[0]

auto[1]

49

1

T71

1

T76

1

T382

1

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T22

1

T382

1

T116

3

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T76

2

T382

1

T227

3

auto[1]

from_0to1

auto[0]

auto[0]

73

1

T69

2

T22

1

T382

1

auto[1]

from_0to1

auto[0]

auto[1]

75

1

T69

2

T71

2

T76

1

auto[1]

from_0to1

auto[1]

auto[0]

73

1

T3

1

T22

1

T71

2

auto[1]

from_0to1

auto[1]

auto[1]

55

1

T3

1

T76

1

T382

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1133

1

T3

10

T69

12

T22

11

auto[1]

1076

1

T3

10

T69

8

T22

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

517

1

T3

4

T69

4

T22

5

from_0to1

521

1

T3

4

T69

5

T22

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1121

1

T3

11

T69

12

T22

9

auto[1]

1088

1

T3

9

T69

8

T22

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1059

1

T3

10

T69

10

T22

8

auto[1]

1150

1

T3

10

T69

10

T22

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T3

2

T69

2

T71

1

auto[0]

from_1to0

auto[0]

auto[1]

73

1

T22

1

T76

1

T382

1

auto[0]

from_1to0

auto[1]

auto[0]

47

1

T69

1

T22

2

T76

1

auto[0]

from_1to0

auto[1]

auto[1]

74

1

T71

1

T76

1

T382

2

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T3

1

T69

2

T71

1

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T22

1

T76

2

T382

1

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T71

2

T76

1

T382

2

auto[0]

from_0to1

auto[1]

auto[1]

70

1

T69

1

T22

1

T71

1

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T3

1

T22

1

T111

1

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T76

1

T116

1

T383

2

auto[1]

from_1to0

auto[1]

auto[0]

74

1

T3

1

T22

1

T71

3

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T69

1

T382

1

T111

3

auto[1]

from_0to1

auto[0]

auto[0]

68

1

T69

1

T71

1

T111

1

auto[1]

from_0to1

auto[0]

auto[1]

71

1

T22

2

T71

1

T116

2

auto[1]

from_0to1

auto[1]

auto[0]

55

1

T3

1

T69

1

T65

2

auto[1]

from_0to1

auto[1]

auto[1]

57

1

T3

2

T22

1

T382

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1057

1

T3

8

T69

10

T22

6

auto[1]

1152

1

T3

12

T69

10

T22

14

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

528

1

T3

5

T69

4

T22

4

from_0to1

539

1

T3

6

T69

5

T22

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1131

1

T3

6

T69

10

T22

6

auto[1]

1078

1

T3

14

T69

10

T22

14

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1121

1

T3

11

T69

4

T22

11

auto[1]

1088

1

T3

9

T69

16

T22

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

71

1

T76

1

T382

2

T116

1

auto[0]

from_1to0

auto[0]

auto[1]

61

1

T22

1

T76

1

T111

1

auto[0]

from_1to0

auto[1]

auto[0]

55

1

T3

3

T22

1

T71

1

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T69

2

T382

1

T111

1

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T71

1

T76

1

T111

1

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T3

1

T69

3

T111

1

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T3

2

T71

1

T111

1

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T22

2

T71

1

T76

1

auto[1]

from_1to0

auto[0]

auto[0]

78

1

T69

1

T71

1

T76

1

auto[1]

from_1to0

auto[0]

auto[1]

75

1

T3

1

T69

1

T71

1

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T22

2

T111

3

T116

1

auto[1]

from_1to0

auto[1]

auto[1]

58

1

T3

1

T71

1

T116

1

auto[1]

from_0to1

auto[0]

auto[0]

92

1

T22

2

T76

1

T382

1

auto[1]

from_0to1

auto[0]

auto[1]

63

1

T3

2

T382

1

T111

2

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T69

1

T76

2

T111

1

auto[1]

from_0to1

auto[1]

auto[1]

71

1

T3

1

T69

1

T22

1