Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	160659	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

121235

1

T1

23

T5

5

T2

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	143327	1			T1	29		T5	2		T2	7
values[0x0]	69005	1			T1	8		T5	8		T2	1
values[0x1]	69562	1			T1	13		T5	10		T2	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	130237	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

151657

1

T1

26

T5

6

T2

7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1741	1			T1	1		T3	1		T6	5
valid_sources[0x01]	1065	1			T5	2		T23	1		T4	32
valid_sources[0x02]	930	1			T6	2		T8	1		T9	3
valid_sources[0x03]	1174	1			T3	2		T6	4		T57	1
valid_sources[0x04]	958	1			T6	1		T26	2		T24	3
valid_sources[0x05]	853	1			T12	1		T28	1		T6	20
valid_sources[0x06]	1155	1			T3	1		T32	14		T6	10
valid_sources[0x07]	787	1			T12	1		T3	2		T6	2
valid_sources[0x08]	889	1			T1	1		T3	1		T26	1
valid_sources[0x09]	818	1			T1	1		T3	1		T32	8
valid_sources[0x0a]	823	1			T1	1		T3	1		T4	70
valid_sources[0x0b]	826	1			T5	1		T6	1		T33	1
valid_sources[0x0c]	834	1			T3	3		T32	26		T6	1
valid_sources[0x0d]	782	1			T1	1		T6	4		T55	42
valid_sources[0x0e]	1553	1			T6	9		T26	2		T45	5
valid_sources[0x0f]	1009	1			T3	3		T6	10		T7	20
valid_sources[0x10]	1006	1			T3	1		T6	12		T57	5
valid_sources[0x11]	846	1			T6	4		T7	1		T57	1
valid_sources[0x12]	1001	1			T3	2		T6	2		T7	4
valid_sources[0x13]	958	1			T3	5		T4	28		T6	14
valid_sources[0x14]	1049	1			T6	6		T7	7		T57	1
valid_sources[0x15]	979	1			T3	4		T6	11		T9	2
valid_sources[0x16]	888	1			T3	1		T6	4		T9	2
valid_sources[0x17]	978	1			T12	1		T23	3		T4	41
valid_sources[0x18]	1875	1			T1	1		T3	2		T6	1
valid_sources[0x19]	950	1			T1	1		T3	2		T6	8
valid_sources[0x1a]	1014	1			T3	2		T23	3		T6	2
valid_sources[0x1b]	1421	1			T7	6		T10	1		T45	3
valid_sources[0x1c]	816	1			T5	1		T6	8		T57	2
valid_sources[0x1d]	1638	1			T3	1		T6	11		T9	4
valid_sources[0x1e]	1703	1			T3	1		T6	1		T7	7
valid_sources[0x1f]	1504	1			T3	3		T6	1		T26	1
valid_sources[0x20]	1029	1			T3	1		T23	1		T6	2
valid_sources[0x21]	908	1			T1	1		T3	1		T6	3
valid_sources[0x22]	864	1			T3	1		T6	3		T9	2
valid_sources[0x23]	1060	1			T3	1		T6	2		T9	1
valid_sources[0x24]	969	1			T14	13		T3	1		T6	1
valid_sources[0x25]	1606	1			T3	4		T25	1		T24	1
valid_sources[0x26]	866	1			T3	1		T6	8		T57	1
valid_sources[0x27]	943	1			T12	1		T6	10		T9	3
valid_sources[0x28]	958	1			T3	3		T4	30		T9	1
valid_sources[0x29]	936	1			T3	1		T6	1		T25	10
valid_sources[0x2a]	1038	1			T1	1		T3	1		T6	2
valid_sources[0x2b]	752	1			T3	1		T23	2		T48	2
valid_sources[0x2c]	766	1			T1	1		T5	1		T12	1
valid_sources[0x2d]	1059	1			T12	1		T6	3		T9	1
valid_sources[0x2e]	1088	1			T3	4		T6	2		T7	11
valid_sources[0x2f]	716	1			T2	2		T3	2		T6	4
valid_sources[0x30]	1623	1			T3	2		T6	7		T25	1
valid_sources[0x31]	1176	1			T3	2		T6	8		T9	2
valid_sources[0x32]	960	1			T3	3		T4	22		T6	15
valid_sources[0x33]	807	1			T6	6		T9	2		T10	5
valid_sources[0x34]	1529	1			T3	3		T28	1		T6	2
valid_sources[0x35]	872	1			T6	10		T7	13		T24	1
valid_sources[0x36]	900	1			T6	6		T26	1		T7	1
valid_sources[0x37]	1328	1			T3	1		T6	5		T24	1
valid_sources[0x38]	971	1			T3	1		T6	4		T57	2
valid_sources[0x39]	1205	1			T1	3		T6	5		T45	3
valid_sources[0x3a]	794	1			T6	6		T24	1		T48	1
valid_sources[0x3b]	938	1			T3	2		T6	9		T9	1
valid_sources[0x3c]	903	1			T1	1		T5	2		T3	1
valid_sources[0x3d]	1030	1			T3	2		T32	13		T7	13
valid_sources[0x3e]	1606	1			T3	3		T16	3		T25	9
valid_sources[0x3f]	904	1			T3	1		T6	11		T7	5
valid_sources[0x40]	795	1			T13	1		T3	2		T6	4
valid_sources[0x41]	2178	1			T28	1		T6	7		T9	1
valid_sources[0x42]	860	1			T1	1		T3	2		T6	3
valid_sources[0x43]	1022	1			T6	10		T26	1		T8	1
valid_sources[0x44]	1036	1			T3	1		T25	5		T45	8
valid_sources[0x45]	858	1			T6	1		T8	2		T9	4
valid_sources[0x46]	840	1			T2	3		T6	8		T55	2
valid_sources[0x47]	1078	1			T23	1		T6	1		T7	1
valid_sources[0x48]	1186	1			T3	2		T6	1		T25	3
valid_sources[0x49]	1260	1			T3	3		T6	2		T48	1
valid_sources[0x4a]	983	1			T1	1		T16	3		T6	4
valid_sources[0x4b]	1856	1			T3	1		T4	46		T6	9
valid_sources[0x4c]	1331	1			T3	3		T7	4		T10	2
valid_sources[0x4d]	858	1			T23	4		T26	1		T7	1
valid_sources[0x4e]	1100	1			T3	2		T6	9		T26	1
valid_sources[0x4f]	867	1			T1	1		T3	2		T6	3
valid_sources[0x50]	868	1			T3	2		T23	3		T6	1
valid_sources[0x51]	983	1			T26	2		T7	3		T48	1
valid_sources[0x52]	1006	1			T6	4		T9	1		T45	2
valid_sources[0x53]	1061	1			T6	5		T7	14		T8	1
valid_sources[0x54]	788	1			T3	1		T6	4		T57	3
valid_sources[0x55]	834	1			T12	1		T26	1		T9	5
valid_sources[0x56]	948	1			T3	1		T6	7		T26	1
valid_sources[0x57]	1429	1			T1	1		T3	3		T9	2
valid_sources[0x58]	971	1			T1	2		T3	1		T6	3
valid_sources[0x59]	1069	1			T5	1		T3	1		T6	2
valid_sources[0x5a]	1143	1			T3	1		T4	42		T6	12
valid_sources[0x5b]	1000	1			T23	1		T4	48		T6	6
valid_sources[0x5c]	960	1			T1	1		T3	1		T6	5
valid_sources[0x5d]	1104	1			T3	1		T4	71		T6	7
valid_sources[0x5e]	2658	1			T3	3		T23	1		T6	6
valid_sources[0x5f]	1787	1			T3	1		T9	5		T10	3
valid_sources[0x60]	1037	1			T3	2		T6	12		T25	1
valid_sources[0x61]	957	1			T6	6		T9	1		T45	6
valid_sources[0x62]	1575	1			T3	1		T17	1		T6	5
valid_sources[0x63]	952	1			T1	1		T5	1		T3	1
valid_sources[0x64]	1918	1			T23	2		T6	13		T9	4
valid_sources[0x65]	844	1			T6	2		T24	5		T9	1
valid_sources[0x66]	785	1			T3	1		T9	1		T10	11
valid_sources[0x67]	1017	1			T3	1		T6	8		T26	3
valid_sources[0x68]	1181	1			T6	6		T9	5		T10	2
valid_sources[0x69]	1212	1			T3	1		T6	4		T57	1
valid_sources[0x6a]	2387	1			T3	1		T6	1		T7	5
valid_sources[0x6b]	901	1			T3	3		T6	8		T9	2
valid_sources[0x6c]	826	1			T12	1		T3	1		T6	3
valid_sources[0x6d]	904	1			T3	4		T6	1		T45	2
valid_sources[0x6e]	960	1			T3	4		T6	5		T26	1
valid_sources[0x6f]	1250	1			T3	1		T23	1		T6	4
valid_sources[0x70]	814	1			T2	1		T3	1		T6	2
valid_sources[0x71]	919	1			T3	2		T6	5		T7	2
valid_sources[0x72]	805	1			T3	2		T6	1		T25	6
valid_sources[0x73]	1749	1			T3	3		T15	1		T6	1
valid_sources[0x74]	887	1			T3	6		T6	3		T9	2
valid_sources[0x75]	1165	1			T6	6		T7	4		T9	2
valid_sources[0x76]	1105	1			T6	8		T7	3		T9	1
valid_sources[0x77]	1824	1			T5	1		T3	1		T23	2
valid_sources[0x78]	768	1			T1	1		T12	2		T7	1
valid_sources[0x79]	1055	1			T1	1		T3	1		T6	2
valid_sources[0x7a]	693	1			T6	3		T9	4		T10	3
valid_sources[0x7b]	942	1			T1	1		T3	1		T23	1
valid_sources[0x7c]	865	1			T1	1		T3	1		T26	2
valid_sources[0x7d]	1044	1			T3	1		T9	2		T10	3
valid_sources[0x7e]	1220	1			T6	3		T48	1		T9	1
valid_sources[0x7f]	1152	1			T3	5		T23	1		T6	7
valid_sources[0x80]	2248	1			T3	1		T6	3		T9	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

64044

1

T1

17

T5

1

T2

4

values[0x0]

all_enables

biggest_size

33469

1

T1

2

T5

2

T2

1

values[0x1]

all_enables

biggest_size

23722

1

T1

4

T5

2

T2

1