Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T14
1	Covered	T1,T5,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T14
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T3,T28,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T2	VC_COV_UNR
1	Covered	T3,T28,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T3,T28,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T28,T25
1	0	Covered	T1,T14,T3
1	1	Covered	T3,T28,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T28,T25
0	1	Covered	T109,T110
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T28,T25
0	1	Covered	T3,T28,T25
1	0	Covered	T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T28,T25
1	-	Covered	T3,T28,T25

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T28,T25
DetectSt	168	Covered	T3,T28,T25
IdleSt	163	Covered	T1,T5,T2
StableSt	191	Covered	T3,T28,T25

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T28,T25
DebounceSt->IdleSt	163	Covered	T49,T128,T129
DetectSt->IdleSt	186	Covered	T109,T110
DetectSt->StableSt	191	Covered	T3,T28,T25
IdleSt->DebounceSt	148	Covered	T3,T28,T25
StableSt->IdleSt	206	Covered	T3,T28,T25

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T28,T25
0	1	Covered	T3,T28,T25
0	0	Excluded	T1,T5,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T28,T25
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T28,T25
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T28,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T49,T128,T129
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T28,T25
DetectSt	-	-	-	-	1	-	-	Covered	T109,T110
DetectSt	-	-	-	-	0	1	-	Covered	T3,T28,T25
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T28,T25
StableSt	-	-	-	-	-	-	0	Covered	T3,T28,T25
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5823894	274	0	0
CntIncr_A	5823894	218724	0	0
CntNoWrap_A	5823894	5160397	0	0
DetectStDropOut_A	5823894	2	0	0
DetectedOut_A	5823894	799	0	0
DetectedPulseOut_A	5823894	123	0	0
DisabledIdleSt_A	5823894	4935585	0	0
DisabledNoDetection_A	5823894	4937890	0	0
EnterDebounceSt_A	5823894	151	0	0
EnterDetectSt_A	5823894	125	0	0
EnterStableSt_A	5823894	123	0	0
PulseIsPulse_A	5823894	123	0	0
StayInStableSt	5823894	676	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5823894	6981	0	0
gen_low_level_sva.LowLevelEvent_A	5823894	5163025	0	0
gen_not_sticky_sva.StableStDropOut_A	5823894	122	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	274	0	0
T3	4462	4	0	0
T4	28273	0	0	0
T6	20803	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T23	491	0	0	0
T25	3703	2	0	0
T28	18583	2	0	0
T32	2718	0	0	0
T48	0	4	0	0
T49	0	3	0	0
T50	0	6	0	0
T51	0	4	0	0
T53	0	4	0	0
T54	0	4	0	0
T95	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	218724	0	0
T3	4462	169	0	0
T4	28273	0	0	0
T6	20803	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T23	491	0	0	0
T25	3703	14	0	0
T28	18583	10	0	0
T32	2718	0	0	0
T48	0	125	0	0
T49	0	44	0	0
T50	0	150	0	0
T51	0	93	0	0
T53	0	149	0	0
T54	0	95	0	0
T95	0	113	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5160397	0	0
T1	2226	623	0	0
T2	534	133	0	0
T3	4462	968	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	2	0	0
T109	17891	1	0	0
T110	0	1	0	0
T117	746	0	0	0
T118	13507	0	0	0
T119	12864	0	0	0
T120	13337	0	0	0
T121	4953	0	0	0
T122	493	0	0	0
T123	493	0	0	0
T124	7860	0	0	0
T125	13607	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	799	0	0
T3	4462	18	0	0
T4	28273	0	0	0
T6	20803	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T23	491	0	0	0
T25	3703	6	0	0
T28	18583	3	0	0
T32	2718	0	0	0
T48	0	9	0	0
T49	0	4	0	0
T50	0	20	0	0
T51	0	16	0	0
T53	0	14	0	0
T54	0	14	0	0
T95	0	22	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	123	0	0
T3	4462	2	0	0
T4	28273	0	0	0
T6	20803	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T23	491	0	0	0
T25	3703	1	0	0
T28	18583	1	0	0
T32	2718	0	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	3	0	0
T51	0	2	0	0
T53	0	2	0	0
T54	0	2	0	0
T95	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	4935585	0	0
T1	2226	623	0	0
T2	534	133	0	0
T3	4462	705	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	4937890	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	713	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	151	0	0
T3	4462	2	0	0
T4	28273	0	0	0
T6	20803	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T23	491	0	0	0
T25	3703	1	0	0
T28	18583	1	0	0
T32	2718	0	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	3	0	0
T51	0	2	0	0
T53	0	2	0	0
T54	0	2	0	0
T95	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	125	0	0
T3	4462	2	0	0
T4	28273	0	0	0
T6	20803	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T23	491	0	0	0
T25	3703	1	0	0
T28	18583	1	0	0
T32	2718	0	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	3	0	0
T51	0	2	0	0
T53	0	2	0	0
T54	0	2	0	0
T95	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	123	0	0
T3	4462	2	0	0
T4	28273	0	0	0
T6	20803	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T23	491	0	0	0
T25	3703	1	0	0
T28	18583	1	0	0
T32	2718	0	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	3	0	0
T51	0	2	0	0
T53	0	2	0	0
T54	0	2	0	0
T95	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	123	0	0
T3	4462	2	0	0
T4	28273	0	0	0
T6	20803	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T23	491	0	0	0
T25	3703	1	0	0
T28	18583	1	0	0
T32	2718	0	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	3	0	0
T51	0	2	0	0
T53	0	2	0	0
T54	0	2	0	0
T95	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	676	0	0
T3	4462	16	0	0
T4	28273	0	0	0
T6	20803	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T23	491	0	0	0
T25	3703	5	0	0
T28	18583	2	0	0
T32	2718	0	0	0
T48	0	7	0	0
T49	0	3	0	0
T50	0	17	0	0
T51	0	14	0	0
T53	0	12	0	0
T54	0	12	0	0
T95	0	20	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	6981	0	0
T3	4462	16	0	0
T4	28273	12	0	0
T6	20803	34	0	0
T14	1128	5	0	0
T15	423	3	0	0
T16	984	0	0	0
T17	422	0	0	0
T23	491	9	0	0
T25	0	14	0	0
T28	18583	3	0	0
T32	2718	4	0	0
T55	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5163025	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	122	0	0
T3	4462	2	0	0
T4	28273	0	0	0
T6	20803	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T23	491	0	0	0
T25	3703	1	0	0
T28	18583	1	0	0
T32	2718	0	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	3	0	0
T51	0	2	0	0
T53	0	2	0	0
T54	0	2	0	0
T95	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T14
1	Covered	T1,T5,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T14
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T8,T21,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T2	VC_COV_UNR
1	Covered	T8,T21,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T8,T21,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T21,T22
1	0	Covered	T1,T14,T3
1	1	Covered	T8,T21,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T21,T22
0	1	Covered	T87,T93,T91
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T21,T22
0	1	Unreachable
1	0	Covered	T8,T21,T22

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T21,T22
DetectSt	168	Covered	T8,T21,T22
IdleSt	163	Covered	T1,T5,T2
StableSt	191	Covered	T8,T21,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T21,T22
DebounceSt->IdleSt	163	Covered	T87,T129,T130
DetectSt->IdleSt	186	Covered	T87,T93,T91
DetectSt->StableSt	191	Covered	T8,T21,T22
IdleSt->DebounceSt	148	Covered	T8,T21,T22
StableSt->IdleSt	206	Covered	T8,T21,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T21,T22
0	1	Covered	T8,T21,T22
0	0	Excluded	T1,T5,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T21,T22
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T21,T22
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T83,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T21,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T87,T129,T130
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T21,T22
DetectSt	-	-	-	-	1	-	-	Covered	T87,T93,T91
DetectSt	-	-	-	-	0	1	-	Covered	T8,T21,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T21,T22
StableSt	-	-	-	-	-	-	0	Covered	T8,T21,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5823894	165	0	0
CntIncr_A	5823894	193729	0	0
CntNoWrap_A	5823894	5160506	0	0
DetectStDropOut_A	5823894	17	0	0
DetectedOut_A	5823894	9462	0	0
DetectedPulseOut_A	5823894	49	0	0
DisabledIdleSt_A	5823894	4434425	0	0
DisabledNoDetection_A	5823894	4436778	0	0
EnterDebounceSt_A	5823894	99	0	0
EnterDetectSt_A	5823894	66	0	0
EnterStableSt_A	5823894	49	0	0
PulseIsPulse_A	5823894	49	0	0
StayInStableSt	5823894	9413	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5823894	6981	0	0
gen_low_level_sva.LowLevelEvent_A	5823894	5163025	0	0
gen_sticky_sva.StableStDropOut_A	5823894	62724	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	165	0	0
T8	2288	2	0	0
T9	20544	0	0	0
T10	29861	0	0	0
T11	12359	0	0	0
T21	0	4	0	0
T22	0	2	0	0
T29	7627	0	0	0
T36	0	2	0	0
T45	32312	0	0	0
T60	630	0	0	0
T61	0	2	0	0
T69	503	0	0	0
T76	0	2	0	0
T77	0	2	0	0
T78	0	2	0	0
T79	0	2	0	0
T80	0	4	0	0
T81	1088	0	0	0
T82	991	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	193729	0	0
T8	2288	98	0	0
T9	20544	0	0	0
T10	29861	0	0	0
T11	12359	0	0	0
T21	0	162	0	0
T22	0	61	0	0
T29	7627	0	0	0
T36	0	74	0	0
T45	32312	0	0	0
T60	630	0	0	0
T61	0	66	0	0
T69	503	0	0	0
T76	0	68	0	0
T77	0	14	0	0
T78	0	61	0	0
T79	0	50	0	0
T80	0	196	0	0
T81	1088	0	0	0
T82	991	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5160506	0	0
T1	2226	623	0	0
T2	534	133	0	0
T3	4462	972	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	17	0	0
T85	657	0	0	0
T87	992	1	0	0
T91	0	1	0	0
T93	0	2	0	0
T102	7258	0	0	0
T131	0	2	0	0
T132	0	1	0	0
T133	0	1	0	0
T134	0	2	0	0
T135	0	3	0	0
T136	0	3	0	0
T137	0	1	0	0
T138	676	0	0	0
T139	23038	0	0	0
T140	502	0	0	0
T141	491	0	0	0
T142	11934	0	0	0
T143	437	0	0	0
T144	721	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	9462	0	0
T8	2288	802	0	0
T9	20544	0	0	0
T10	29861	0	0	0
T11	12359	0	0	0
T21	0	824	0	0
T22	0	308	0	0
T29	7627	0	0	0
T36	0	298	0	0
T45	32312	0	0	0
T60	630	0	0	0
T61	0	87	0	0
T69	503	0	0	0
T76	0	354	0	0
T77	0	26	0	0
T78	0	234	0	0
T79	0	243	0	0
T80	0	545	0	0
T81	1088	0	0	0
T82	991	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	49	0	0
T8	2288	1	0	0
T9	20544	0	0	0
T10	29861	0	0	0
T11	12359	0	0	0
T21	0	2	0	0
T22	0	1	0	0
T29	7627	0	0	0
T36	0	1	0	0
T45	32312	0	0	0
T60	630	0	0	0
T61	0	1	0	0
T69	503	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	2	0	0
T81	1088	0	0	0
T82	991	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	4434425	0	0
T1	2226	623	0	0
T2	534	133	0	0
T3	4462	972	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	4436778	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	99	0	0
T8	2288	1	0	0
T9	20544	0	0	0
T10	29861	0	0	0
T11	12359	0	0	0
T21	0	2	0	0
T22	0	1	0	0
T29	7627	0	0	0
T36	0	1	0	0
T45	32312	0	0	0
T60	630	0	0	0
T61	0	1	0	0
T69	503	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	2	0	0
T81	1088	0	0	0
T82	991	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	66	0	0
T8	2288	1	0	0
T9	20544	0	0	0
T10	29861	0	0	0
T11	12359	0	0	0
T21	0	2	0	0
T22	0	1	0	0
T29	7627	0	0	0
T36	0	1	0	0
T45	32312	0	0	0
T60	630	0	0	0
T61	0	1	0	0
T69	503	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	2	0	0
T81	1088	0	0	0
T82	991	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	49	0	0
T8	2288	1	0	0
T9	20544	0	0	0
T10	29861	0	0	0
T11	12359	0	0	0
T21	0	2	0	0
T22	0	1	0	0
T29	7627	0	0	0
T36	0	1	0	0
T45	32312	0	0	0
T60	630	0	0	0
T61	0	1	0	0
T69	503	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	2	0	0
T81	1088	0	0	0
T82	991	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	49	0	0
T8	2288	1	0	0
T9	20544	0	0	0
T10	29861	0	0	0
T11	12359	0	0	0
T21	0	2	0	0
T22	0	1	0	0
T29	7627	0	0	0
T36	0	1	0	0
T45	32312	0	0	0
T60	630	0	0	0
T61	0	1	0	0
T69	503	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	2	0	0
T81	1088	0	0	0
T82	991	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	9413	0	0
T8	2288	801	0	0
T9	20544	0	0	0
T10	29861	0	0	0
T11	12359	0	0	0
T21	0	822	0	0
T22	0	307	0	0
T29	7627	0	0	0
T36	0	297	0	0
T45	32312	0	0	0
T60	630	0	0	0
T61	0	86	0	0
T69	503	0	0	0
T76	0	353	0	0
T77	0	25	0	0
T78	0	233	0	0
T79	0	242	0	0
T80	0	543	0	0
T81	1088	0	0	0
T82	991	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	6981	0	0
T3	4462	16	0	0
T4	28273	12	0	0
T6	20803	34	0	0
T14	1128	5	0	0
T15	423	3	0	0
T16	984	0	0	0
T17	422	0	0	0
T23	491	9	0	0
T25	0	14	0	0
T28	18583	3	0	0
T32	2718	4	0	0
T55	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5163025	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	62724	0	0
T8	2288	130	0	0
T9	20544	0	0	0
T10	29861	0	0	0
T11	12359	0	0	0
T21	0	237	0	0
T22	0	101	0	0
T29	7627	0	0	0
T36	0	534	0	0
T45	32312	0	0	0
T60	630	0	0	0
T61	0	155	0	0
T69	503	0	0	0
T76	0	270	0	0
T77	0	234	0	0
T78	0	172	0	0
T79	0	370	0	0
T80	0	93	0	0
T81	1088	0	0	0
T82	991	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T1,T2,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T2,T14
1	1	Covered	T1,T2,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T8,T21,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T2	VC_COV_UNR
1	Covered	T8,T21,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T8,T61,T76

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T21,T22
1	0	Covered	T1,T2,T14
1	1	Covered	T8,T21,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T61,T76
0	1	Covered	T8,T61,T80
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T61,T76
0	1	Unreachable
1	0	Covered	T8,T61,T76

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T21,T22
DetectSt	168	Covered	T8,T61,T76
IdleSt	163	Covered	T1,T5,T2
StableSt	191	Covered	T8,T61,T76

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T61,T76
DebounceSt->IdleSt	163	Covered	T21,T22,T36
DetectSt->IdleSt	186	Covered	T8,T61,T80
DetectSt->StableSt	191	Covered	T8,T61,T76
IdleSt->DebounceSt	148	Covered	T8,T21,T22
StableSt->IdleSt	206	Covered	T8,T61,T76

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T21,T22
0	1	Covered	T8,T21,T22
0	0	Excluded	T1,T5,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T61,T76
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T21,T22
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T83,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T61,T76
DebounceSt	-	0	1	0	-	-	-	Covered	T21,T22,T36
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T21,T22
DetectSt	-	-	-	-	1	-	-	Covered	T8,T61,T80
DetectSt	-	-	-	-	0	1	-	Covered	T8,T61,T76
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T61,T76
StableSt	-	-	-	-	-	-	0	Covered	T8,T61,T76
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5823894	165	0	0
CntIncr_A	5823894	81284	0	0
CntNoWrap_A	5823894	5160506	0	0
DetectStDropOut_A	5823894	12	0	0
DetectedOut_A	5823894	48953	0	0
DetectedPulseOut_A	5823894	42	0	0
DisabledIdleSt_A	5823894	4434425	0	0
DisabledNoDetection_A	5823894	4436778	0	0
EnterDebounceSt_A	5823894	111	0	0
EnterDetectSt_A	5823894	54	0	0
EnterStableSt_A	5823894	42	0	0
PulseIsPulse_A	5823894	42	0	0
StayInStableSt	5823894	48911	0	0
gen_high_level_sva.HighLevelEvent_A	5823894	5163025	0	0
gen_sticky_sva.StableStDropOut_A	5823894	588726	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	165	0	0
T8	2288	6	0	0
T9	20544	0	0	0
T10	29861	0	0	0
T11	12359	0	0	0
T21	0	9	0	0
T22	0	4	0	0
T29	7627	0	0	0
T36	0	5	0	0
T45	32312	0	0	0
T60	630	0	0	0
T61	0	4	0	0
T69	503	0	0	0
T76	0	2	0	0
T77	0	2	0	0
T78	0	2	0	0
T79	0	2	0	0
T80	0	7	0	0
T81	1088	0	0	0
T82	991	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	81284	0	0
T8	2288	198	0	0
T9	20544	0	0	0
T10	29861	0	0	0
T11	12359	0	0	0
T21	0	468	0	0
T22	0	64	0	0
T29	7627	0	0	0
T36	0	365	0	0
T45	32312	0	0	0
T60	630	0	0	0
T61	0	196	0	0
T69	503	0	0	0
T76	0	61	0	0
T77	0	31	0	0
T78	0	92	0	0
T79	0	97	0	0
T80	0	84	0	0
T81	1088	0	0	0
T82	991	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5160506	0	0
T1	2226	623	0	0
T2	534	133	0	0
T3	4462	972	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	12	0	0
T8	2288	2	0	0
T9	20544	0	0	0
T10	29861	0	0	0
T11	12359	0	0	0
T29	7627	0	0	0
T45	32312	0	0	0
T60	630	0	0	0
T61	0	1	0	0
T69	503	0	0	0
T80	0	2	0	0
T81	1088	0	0	0
T82	991	0	0	0
T130	0	3	0	0
T131	0	2	0	0
T134	0	1	0	0
T145	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	48953	0	0
T8	2288	135	0	0
T9	20544	0	0	0
T10	29861	0	0	0
T11	12359	0	0	0
T29	7627	0	0	0
T45	32312	0	0	0
T60	630	0	0	0
T61	0	1	0	0
T69	503	0	0	0
T76	0	542	0	0
T77	0	88	0	0
T78	0	320	0	0
T79	0	673	0	0
T80	0	1	0	0
T81	1088	0	0	0
T82	991	0	0	0
T87	0	52	0	0
T88	0	214	0	0
T93	0	392	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	42	0	0
T8	2288	1	0	0
T9	20544	0	0	0
T10	29861	0	0	0
T11	12359	0	0	0
T29	7627	0	0	0
T45	32312	0	0	0
T60	630	0	0	0
T61	0	1	0	0
T69	503	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	1088	0	0	0
T82	991	0	0	0
T87	0	2	0	0
T88	0	1	0	0
T93	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	4434425	0	0
T1	2226	623	0	0
T2	534	133	0	0
T3	4462	972	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	4436778	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	111	0	0
T8	2288	3	0	0
T9	20544	0	0	0
T10	29861	0	0	0
T11	12359	0	0	0
T21	0	9	0	0
T22	0	4	0	0
T29	7627	0	0	0
T36	0	5	0	0
T45	32312	0	0	0
T60	630	0	0	0
T61	0	2	0	0
T69	503	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	4	0	0
T81	1088	0	0	0
T82	991	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	54	0	0
T8	2288	3	0	0
T9	20544	0	0	0
T10	29861	0	0	0
T11	12359	0	0	0
T29	7627	0	0	0
T45	32312	0	0	0
T60	630	0	0	0
T61	0	2	0	0
T69	503	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	3	0	0
T81	1088	0	0	0
T82	991	0	0	0
T87	0	2	0	0
T88	0	1	0	0
T93	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	42	0	0
T8	2288	1	0	0
T9	20544	0	0	0
T10	29861	0	0	0
T11	12359	0	0	0
T29	7627	0	0	0
T45	32312	0	0	0
T60	630	0	0	0
T61	0	1	0	0
T69	503	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	1088	0	0	0
T82	991	0	0	0
T87	0	2	0	0
T88	0	1	0	0
T93	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	42	0	0
T8	2288	1	0	0
T9	20544	0	0	0
T10	29861	0	0	0
T11	12359	0	0	0
T29	7627	0	0	0
T45	32312	0	0	0
T60	630	0	0	0
T61	0	1	0	0
T69	503	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	1088	0	0	0
T82	991	0	0	0
T87	0	2	0	0
T88	0	1	0	0
T93	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	48911	0	0
T8	2288	134	0	0
T9	20544	0	0	0
T10	29861	0	0	0
T11	12359	0	0	0
T29	7627	0	0	0
T45	32312	0	0	0
T60	630	0	0	0
T69	503	0	0	0
T76	0	541	0	0
T77	0	87	0	0
T78	0	319	0	0
T79	0	672	0	0
T81	1088	0	0	0
T82	991	0	0	0
T87	0	50	0	0
T88	0	213	0	0
T93	0	390	0	0
T146	0	41	0	0
T147	0	93	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5163025	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	588726	0	0
T8	2288	419	0	0
T9	20544	0	0	0
T10	29861	0	0	0
T11	12359	0	0	0
T29	7627	0	0	0
T45	32312	0	0	0
T60	630	0	0	0
T61	0	61	0	0
T69	503	0	0	0
T76	0	83	0	0
T77	0	159	0	0
T78	0	45	0	0
T79	0	111	0	0
T80	0	192	0	0
T81	1088	0	0	0
T82	991	0	0	0
T87	0	153	0	0
T88	0	40	0	0
T93	0	230	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T1,T2,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T8,T21,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T2	VC_COV_UNR
1	Covered	T8,T21,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T21,T22,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T21,T22
1	0	Covered	T1,T2,T14
1	1	Covered	T8,T21,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T36
0	1	Covered	T87,T88,T89
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T36
0	1	Unreachable
1	0	Covered	T21,T22,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T21,T22
DetectSt	168	Covered	T21,T22,T36
IdleSt	163	Covered	T1,T5,T2
StableSt	191	Covered	T21,T22,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T21,T22,T36
DebounceSt->IdleSt	163	Covered	T8,T79,T93
DetectSt->IdleSt	186	Covered	T87,T88,T89
DetectSt->StableSt	191	Covered	T21,T22,T36
IdleSt->DebounceSt	148	Covered	T8,T21,T22
StableSt->IdleSt	206	Covered	T21,T22,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T21,T22
0	1	Covered	T8,T21,T22
0	0	Excluded	T1,T5,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T36
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T21,T22
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T83,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T21,T22,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T79,T93
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T21,T22
DetectSt	-	-	-	-	1	-	-	Covered	T87,T88,T89
DetectSt	-	-	-	-	0	1	-	Covered	T21,T22,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T21,T22,T36
StableSt	-	-	-	-	-	-	0	Covered	T21,T22,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5823894	166	0	0
CntIncr_A	5823894	69858	0	0
CntNoWrap_A	5823894	5160505	0	0
DetectStDropOut_A	5823894	16	0	0
DetectedOut_A	5823894	337107	0	0
DetectedPulseOut_A	5823894	41	0	0
DisabledIdleSt_A	5823894	4434425	0	0
DisabledNoDetection_A	5823894	4436778	0	0
EnterDebounceSt_A	5823894	109	0	0
EnterDetectSt_A	5823894	57	0	0
EnterStableSt_A	5823894	41	0	0
PulseIsPulse_A	5823894	41	0	0
StayInStableSt	5823894	337066	0	0
gen_high_event_sva.HighLevelEvent_A	5823894	5163025	0	0
gen_high_level_sva.HighLevelEvent_A	5823894	5163025	0	0
gen_sticky_sva.StableStDropOut_A	5823894	124977	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	166	0	0
T8	2288	5	0	0
T9	20544	0	0	0
T10	29861	0	0	0
T11	12359	0	0	0
T21	0	4	0	0
T22	0	2	0	0
T29	7627	0	0	0
T36	0	2	0	0
T45	32312	0	0	0
T60	630	0	0	0
T61	0	2	0	0
T69	503	0	0	0
T76	0	2	0	0
T77	0	2	0	0
T78	0	2	0	0
T79	0	4	0	0
T80	0	4	0	0
T81	1088	0	0	0
T82	991	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	69858	0	0
T8	2288	175	0	0
T9	20544	0	0	0
T10	29861	0	0	0
T11	12359	0	0	0
T21	0	132	0	0
T22	0	69	0	0
T29	7627	0	0	0
T36	0	82	0	0
T45	32312	0	0	0
T60	630	0	0	0
T61	0	76	0	0
T69	503	0	0	0
T76	0	19	0	0
T77	0	90	0	0
T78	0	15	0	0
T79	0	256	0	0
T80	0	52	0	0
T81	1088	0	0	0
T82	991	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5160505	0	0
T1	2226	623	0	0
T2	534	133	0	0
T3	4462	972	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	16	0	0
T85	657	0	0	0
T87	992	2	0	0
T88	0	2	0	0
T89	0	1	0	0
T102	7258	0	0	0
T137	0	3	0	0
T138	676	0	0	0
T139	23038	0	0	0
T140	502	0	0	0
T141	491	0	0	0
T142	11934	0	0	0
T143	437	0	0	0
T144	721	0	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	2	0	0
T152	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	337107	0	0
T21	2140	847	0	0
T22	2297	249	0	0
T27	773	0	0	0
T33	17456	0	0	0
T34	17799	0	0	0
T36	258522	460	0	0
T46	22587	0	0	0
T47	32569	0	0	0
T50	687	0	0	0
T61	0	214	0	0
T76	0	130	0	0
T77	0	173	0	0
T78	0	71	0	0
T80	0	115	0	0
T87	0	39	0	0
T93	0	97	0	0
T127	406	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	41	0	0
T21	2140	2	0	0
T22	2297	1	0	0
T27	773	0	0	0
T33	17456	0	0	0
T34	17799	0	0	0
T36	258522	1	0	0
T46	22587	0	0	0
T47	32569	0	0	0
T50	687	0	0	0
T61	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T80	0	2	0	0
T87	0	1	0	0
T93	0	1	0	0
T127	406	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	4434425	0	0
T1	2226	623	0	0
T2	534	133	0	0
T3	4462	972	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	4436778	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	109	0	0
T8	2288	5	0	0
T9	20544	0	0	0
T10	29861	0	0	0
T11	12359	0	0	0
T21	0	2	0	0
T22	0	1	0	0
T29	7627	0	0	0
T36	0	1	0	0
T45	32312	0	0	0
T60	630	0	0	0
T61	0	1	0	0
T69	503	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	4	0	0
T80	0	2	0	0
T81	1088	0	0	0
T82	991	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	57	0	0
T21	2140	2	0	0
T22	2297	1	0	0
T27	773	0	0	0
T33	17456	0	0	0
T34	17799	0	0	0
T36	258522	1	0	0
T46	22587	0	0	0
T47	32569	0	0	0
T50	687	0	0	0
T61	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T80	0	2	0	0
T87	0	3	0	0
T93	0	1	0	0
T127	406	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	41	0	0
T21	2140	2	0	0
T22	2297	1	0	0
T27	773	0	0	0
T33	17456	0	0	0
T34	17799	0	0	0
T36	258522	1	0	0
T46	22587	0	0	0
T47	32569	0	0	0
T50	687	0	0	0
T61	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T80	0	2	0	0
T87	0	1	0	0
T93	0	1	0	0
T127	406	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	41	0	0
T21	2140	2	0	0
T22	2297	1	0	0
T27	773	0	0	0
T33	17456	0	0	0
T34	17799	0	0	0
T36	258522	1	0	0
T46	22587	0	0	0
T47	32569	0	0	0
T50	687	0	0	0
T61	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T80	0	2	0	0
T87	0	1	0	0
T93	0	1	0	0
T127	406	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	337066	0	0
T21	2140	845	0	0
T22	2297	248	0	0
T27	773	0	0	0
T33	17456	0	0	0
T34	17799	0	0	0
T36	258522	459	0	0
T46	22587	0	0	0
T47	32569	0	0	0
T50	687	0	0	0
T61	0	213	0	0
T76	0	129	0	0
T77	0	172	0	0
T78	0	70	0	0
T80	0	113	0	0
T87	0	38	0	0
T93	0	96	0	0
T127	406	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5163025	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5163025	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	124977	0	0
T21	2140	267	0	0
T22	2297	156	0	0
T27	773	0	0	0
T33	17456	0	0	0
T34	17799	0	0	0
T36	258522	375	0	0
T46	22587	0	0	0
T47	32569	0	0	0
T50	687	0	0	0
T61	0	36	0	0
T76	0	557	0	0
T77	0	32	0	0
T78	0	387	0	0
T80	0	694	0	0
T87	0	55	0	0
T93	0	319	0	0
T127	406	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T1,T5,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T5,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T1,T35,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T2	VC_COV_UNR
1	Covered	T1,T35,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T1,T35,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T36
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T35,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T35,T37
0	1	Covered	T91
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T35,T37
0	1	Covered	T35,T43,T39
1	0	Covered	T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T35,T37
1	-	Covered	T35,T43,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T35,T37
DetectSt	168	Covered	T1,T35,T37
IdleSt	163	Covered	T1,T5,T2
StableSt	191	Covered	T1,T35,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T35,T37
DebounceSt->IdleSt	163	Covered	T83,T153,T154
DetectSt->IdleSt	186	Covered	T91
DetectSt->StableSt	191	Covered	T1,T35,T37
IdleSt->DebounceSt	148	Covered	T1,T35,T37
StableSt->IdleSt	206	Covered	T1,T35,T155

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T35,T37
0	1	Covered	T1,T35,T37
0	0	Excluded	T1,T5,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T35,T37
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T35,T37
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T35,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T153,T154
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T35,T37
DetectSt	-	-	-	-	1	-	-	Covered	T91
DetectSt	-	-	-	-	0	1	-	Covered	T1,T35,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T43,T39
StableSt	-	-	-	-	-	-	0	Covered	T1,T35,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5823894	75	0	0
CntIncr_A	5823894	2129	0	0
CntNoWrap_A	5823894	5160596	0	0
DetectStDropOut_A	5823894	1	0	0
DetectedOut_A	5823894	3455	0	0
DetectedPulseOut_A	5823894	35	0	0
DisabledIdleSt_A	5823894	4776448	0	0
DisabledNoDetection_A	5823894	4778753	0	0
EnterDebounceSt_A	5823894	39	0	0
EnterDetectSt_A	5823894	36	0	0
EnterStableSt_A	5823894	35	0	0
PulseIsPulse_A	5823894	35	0	0
StayInStableSt	5823894	3400	0	0
gen_high_level_sva.HighLevelEvent_A	5823894	5163025	0	0
gen_not_sticky_sva.StableStDropOut_A	5823894	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	75	0	0
T1	2226	2	0	0
T2	534	0	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T35	0	2	0	0
T37	0	2	0	0
T39	0	2	0	0
T43	0	4	0	0
T93	0	4	0	0
T129	0	2	0	0
T155	0	2	0	0
T156	0	2	0	0
T157	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	2129	0	0
T1	2226	30	0	0
T2	534	0	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T35	0	95	0	0
T37	0	78	0	0
T39	0	62	0	0
T43	0	144	0	0
T93	0	110	0	0
T129	0	72	0	0
T155	0	90	0	0
T156	0	54	0	0
T157	0	146	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5160596	0	0
T1	2226	621	0	0
T2	534	133	0	0
T3	4462	972	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	1	0	0
T91	22562	1	0	0
T158	2385	0	0	0
T159	794	0	0	0
T160	5271	0	0	0
T161	493	0	0	0
T162	496	0	0	0
T163	491	0	0	0
T164	503	0	0	0
T165	30266	0	0	0
T166	506	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	3455	0	0
T1	2226	174	0	0
T2	534	0	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T35	0	42	0	0
T37	0	42	0	0
T39	0	41	0	0
T43	0	228	0	0
T93	0	231	0	0
T129	0	63	0	0
T155	0	39	0	0
T156	0	200	0	0
T157	0	84	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	35	0	0
T1	2226	1	0	0
T2	534	0	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T35	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T43	0	2	0	0
T93	0	2	0	0
T129	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	4776448	0	0
T1	2226	293	0	0
T2	534	3	0	0
T3	4462	972	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	4778753	0	0
T1	2226	295	0	0
T2	534	3	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	39	0	0
T1	2226	1	0	0
T2	534	0	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T35	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T43	0	2	0	0
T93	0	2	0	0
T129	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	36	0	0
T1	2226	1	0	0
T2	534	0	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T35	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T43	0	2	0	0
T93	0	2	0	0
T129	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	35	0	0
T1	2226	1	0	0
T2	534	0	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T35	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T43	0	2	0	0
T93	0	2	0	0
T129	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	35	0	0
T1	2226	1	0	0
T2	534	0	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T35	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T43	0	2	0	0
T93	0	2	0	0
T129	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	3400	0	0
T1	2226	172	0	0
T2	534	0	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T35	0	41	0	0
T37	0	40	0	0
T39	0	40	0	0
T43	0	225	0	0
T93	0	227	0	0
T129	0	62	0	0
T155	0	37	0	0
T156	0	198	0	0
T157	0	81	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5163025	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	14	0	0
T35	40117	1	0	0
T37	894	0	0	0
T39	0	1	0	0
T40	940	0	0	0
T43	0	1	0	0
T63	492	0	0	0
T111	502	0	0	0
T112	1657	0	0	0
T113	25808	0	0	0
T114	402	0	0	0
T115	408	0	0	0
T116	501	0	0	0
T129	0	1	0	0
T157	0	1	0	0
T159	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T1,T5,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T1,T2,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T2	VC_COV_UNR
1	Covered	T1,T2,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T1,T2,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T36
1	0	Covered	T1,T3,T15
1	1	Covered	T1,T2,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T35
0	1	Covered	T44,T85,T91
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T35
0	1	Covered	T1,T38,T155
1	0	Covered	T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T35
1	-	Covered	T1,T38,T155

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T35
DetectSt	168	Covered	T1,T2,T35
IdleSt	163	Covered	T1,T5,T2
StableSt	191	Covered	T1,T2,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T35
DebounceSt->IdleSt	163	Covered	T35,T171,T156
DetectSt->IdleSt	186	Covered	T44,T85,T91
DetectSt->StableSt	191	Covered	T1,T2,T35
IdleSt->DebounceSt	148	Covered	T1,T2,T35
StableSt->IdleSt	206	Covered	T1,T38,T155

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T35
0	1	Covered	T1,T2,T35
0	0	Excluded	T1,T5,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T35
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T35
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T35,T171,T156
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T35
DetectSt	-	-	-	-	1	-	-	Covered	T44,T85,T91
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T38,T155
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5823894	130	0	0
CntIncr_A	5823894	61620	0	0
CntNoWrap_A	5823894	5160541	0	0
DetectStDropOut_A	5823894	3	0	0
DetectedOut_A	5823894	4088	0	0
DetectedPulseOut_A	5823894	58	0	0
DisabledIdleSt_A	5823894	4773587	0	0
DisabledNoDetection_A	5823894	4775892	0	0
EnterDebounceSt_A	5823894	70	0	0
EnterDetectSt_A	5823894	61	0	0
EnterStableSt_A	5823894	58	0	0
PulseIsPulse_A	5823894	58	0	0
StayInStableSt	5823894	4001	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5823894	2683	0	0
gen_low_level_sva.LowLevelEvent_A	5823894	5163025	0	0
gen_not_sticky_sva.StableStDropOut_A	5823894	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	130	0	0
T1	2226	2	0	0
T2	534	2	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T35	0	3	0	0
T38	0	4	0	0
T39	0	6	0	0
T44	0	4	0	0
T78	0	2	0	0
T85	0	6	0	0
T93	0	2	0	0
T155	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	61620	0	0
T1	2226	30	0	0
T2	534	41	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T35	0	190	0	0
T38	0	40	0	0
T39	0	173	0	0
T44	0	52	0	0
T78	0	43	0	0
T85	0	51	0	0
T93	0	12	0	0
T155	0	90	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5160541	0	0
T1	2226	621	0	0
T2	534	131	0	0
T3	4462	972	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	3	0	0
T44	19577	1	0	0
T78	11923	0	0	0
T85	0	1	0	0
T91	0	1	0	0
T99	6089	0	0	0
T172	487	0	0	0
T173	522	0	0	0
T174	522	0	0	0
T175	501	0	0	0
T176	446	0	0	0
T177	490	0	0	0
T178	505	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	4088	0	0
T1	2226	90	0	0
T2	534	84	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T35	0	139	0	0
T38	0	117	0	0
T39	0	307	0	0
T44	0	66	0	0
T78	0	39	0	0
T85	0	81	0	0
T93	0	56	0	0
T155	0	142	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	58	0	0
T1	2226	1	0	0
T2	534	1	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T35	0	1	0	0
T38	0	2	0	0
T39	0	3	0	0
T44	0	1	0	0
T78	0	1	0	0
T85	0	2	0	0
T93	0	1	0	0
T155	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	4773587	0	0
T1	2226	293	0	0
T2	534	3	0	0
T3	4462	972	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	4775892	0	0
T1	2226	295	0	0
T2	534	3	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	70	0	0
T1	2226	1	0	0
T2	534	1	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T35	0	2	0	0
T38	0	2	0	0
T39	0	3	0	0
T44	0	2	0	0
T78	0	1	0	0
T85	0	3	0	0
T93	0	1	0	0
T155	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	61	0	0
T1	2226	1	0	0
T2	534	1	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T35	0	1	0	0
T38	0	2	0	0
T39	0	3	0	0
T44	0	2	0	0
T78	0	1	0	0
T85	0	3	0	0
T93	0	1	0	0
T155	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	58	0	0
T1	2226	1	0	0
T2	534	1	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T35	0	1	0	0
T38	0	2	0	0
T39	0	3	0	0
T44	0	1	0	0
T78	0	1	0	0
T85	0	2	0	0
T93	0	1	0	0
T155	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	58	0	0
T1	2226	1	0	0
T2	534	1	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T35	0	1	0	0
T38	0	2	0	0
T39	0	3	0	0
T44	0	1	0	0
T78	0	1	0	0
T85	0	2	0	0
T93	0	1	0	0
T155	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	4001	0	0
T1	2226	89	0	0
T2	534	82	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T35	0	137	0	0
T38	0	114	0	0
T39	0	302	0	0
T44	0	65	0	0
T78	0	37	0	0
T85	0	78	0	0
T93	0	54	0	0
T155	0	141	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	2683	0	0
T1	2226	1	0	0
T2	534	1	0	0
T3	4462	10	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	3	0	0
T16	984	0	0	0
T17	422	2	0	0
T23	0	5	0	0
T24	0	6	0	0
T25	0	3	0	0
T26	0	6	0	0
T55	0	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5163025	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	28	0	0
T1	2226	1	0	0
T2	534	0	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T44	0	1	0	0
T85	0	1	0	0
T91	0	2	0	0
T107	0	2	0	0
T155	0	1	0	0
T179	0	1	0	0
T180	0	1	0	0