Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T1,T5,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T5,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T27,T40,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T2	VC_COV_UNR
1	Covered	T27,T40,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T27,T40,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T40,T41
1	0	Covered	T1,T5,T2
1	1	Covered	T27,T40,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T40,T44
0	1	Covered	T92
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T27,T40,T44
0	1	Covered	T27,T181,T93
1	0	Covered	T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T27,T40,T44
1	-	Covered	T27,T181,T93

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T27,T40,T44
DetectSt	168	Covered	T27,T40,T44
IdleSt	163	Covered	T1,T5,T2
StableSt	191	Covered	T27,T40,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T27,T40,T44
DebounceSt->IdleSt	163	Covered	T83,T137
DetectSt->IdleSt	186	Covered	T92
DetectSt->StableSt	191	Covered	T27,T40,T44
IdleSt->DebounceSt	148	Covered	T27,T40,T44
StableSt->IdleSt	206	Covered	T27,T44,T181

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T27,T40,T44
0	1	Covered	T27,T40,T44
0	0	Excluded	T1,T5,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T40,T44
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T27,T40,T44
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T27,T40,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T137
DebounceSt	-	0	0	-	-	-	-	Covered	T27,T40,T44
DetectSt	-	-	-	-	1	-	-	Covered	T92
DetectSt	-	-	-	-	0	1	-	Covered	T27,T40,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T27,T181,T93
StableSt	-	-	-	-	-	-	0	Covered	T27,T40,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5823894	66	0	0
CntIncr_A	5823894	1947	0	0
CntNoWrap_A	5823894	5160605	0	0
DetectStDropOut_A	5823894	1	0	0
DetectedOut_A	5823894	2808	0	0
DetectedPulseOut_A	5823894	31	0	0
DisabledIdleSt_A	5823894	5144136	0	0
DisabledNoDetection_A	5823894	5146440	0	0
EnterDebounceSt_A	5823894	34	0	0
EnterDetectSt_A	5823894	32	0	0
EnterStableSt_A	5823894	31	0	0
PulseIsPulse_A	5823894	31	0	0
StayInStableSt	5823894	2760	0	0
gen_high_level_sva.HighLevelEvent_A	5823894	5163025	0	0
gen_not_sticky_sva.StableStDropOut_A	5823894	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	66	0	0
T27	773	2	0	0
T34	17799	0	0	0
T36	258522	0	0	0
T40	0	2	0	0
T44	0	2	0	0
T46	22587	0	0	0
T47	32569	0	0	0
T50	687	0	0	0
T61	2399	0	0	0
T70	548	0	0	0
T71	503	0	0	0
T93	0	6	0	0
T165	0	2	0	0
T181	0	2	0	0
T182	0	2	0	0
T183	0	2	0	0
T184	0	2	0	0
T185	0	2	0	0
T186	446	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	1947	0	0
T27	773	60	0	0
T34	17799	0	0	0
T36	258522	0	0	0
T40	0	96	0	0
T44	0	26	0	0
T46	22587	0	0	0
T47	32569	0	0	0
T50	687	0	0	0
T61	2399	0	0	0
T70	548	0	0	0
T71	503	0	0	0
T93	0	135	0	0
T165	0	43	0	0
T181	0	57	0	0
T182	0	28	0	0
T183	0	70	0	0
T184	0	96	0	0
T185	0	70	0	0
T186	446	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5160605	0	0
T1	2226	623	0	0
T2	534	133	0	0
T3	4462	972	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	1	0	0
T92	1010	1	0	0
T168	1098	0	0	0
T187	404	0	0	0
T188	741	0	0	0
T189	570	0	0	0
T190	1249	0	0	0
T191	14697	0	0	0
T192	25070	0	0	0
T193	424	0	0	0
T194	490	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	2808	0	0
T27	773	140	0	0
T34	17799	0	0	0
T36	258522	0	0	0
T40	0	43	0	0
T44	0	66	0	0
T46	22587	0	0	0
T47	32569	0	0	0
T50	687	0	0	0
T61	2399	0	0	0
T70	548	0	0	0
T71	503	0	0	0
T93	0	231	0	0
T165	0	41	0	0
T181	0	53	0	0
T182	0	88	0	0
T183	0	66	0	0
T184	0	136	0	0
T185	0	44	0	0
T186	446	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	31	0	0
T27	773	1	0	0
T34	17799	0	0	0
T36	258522	0	0	0
T40	0	1	0	0
T44	0	1	0	0
T46	22587	0	0	0
T47	32569	0	0	0
T50	687	0	0	0
T61	2399	0	0	0
T70	548	0	0	0
T71	503	0	0	0
T93	0	3	0	0
T165	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0
T186	446	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5144136	0	0
T1	2226	623	0	0
T2	534	133	0	0
T3	4462	972	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5146440	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	34	0	0
T27	773	1	0	0
T34	17799	0	0	0
T36	258522	0	0	0
T40	0	1	0	0
T44	0	1	0	0
T46	22587	0	0	0
T47	32569	0	0	0
T50	687	0	0	0
T61	2399	0	0	0
T70	548	0	0	0
T71	503	0	0	0
T93	0	3	0	0
T165	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0
T186	446	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	32	0	0
T27	773	1	0	0
T34	17799	0	0	0
T36	258522	0	0	0
T40	0	1	0	0
T44	0	1	0	0
T46	22587	0	0	0
T47	32569	0	0	0
T50	687	0	0	0
T61	2399	0	0	0
T70	548	0	0	0
T71	503	0	0	0
T93	0	3	0	0
T165	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0
T186	446	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	31	0	0
T27	773	1	0	0
T34	17799	0	0	0
T36	258522	0	0	0
T40	0	1	0	0
T44	0	1	0	0
T46	22587	0	0	0
T47	32569	0	0	0
T50	687	0	0	0
T61	2399	0	0	0
T70	548	0	0	0
T71	503	0	0	0
T93	0	3	0	0
T165	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0
T186	446	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	31	0	0
T27	773	1	0	0
T34	17799	0	0	0
T36	258522	0	0	0
T40	0	1	0	0
T44	0	1	0	0
T46	22587	0	0	0
T47	32569	0	0	0
T50	687	0	0	0
T61	2399	0	0	0
T70	548	0	0	0
T71	503	0	0	0
T93	0	3	0	0
T165	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0
T186	446	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	2760	0	0
T27	773	139	0	0
T34	17799	0	0	0
T36	258522	0	0	0
T40	0	41	0	0
T44	0	64	0	0
T46	22587	0	0	0
T47	32569	0	0	0
T50	687	0	0	0
T61	2399	0	0	0
T70	548	0	0	0
T71	503	0	0	0
T93	0	226	0	0
T165	0	39	0	0
T181	0	52	0	0
T182	0	86	0	0
T183	0	64	0	0
T184	0	135	0	0
T185	0	42	0	0
T186	446	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5163025	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	13	0	0
T27	773	1	0	0
T34	17799	0	0	0
T36	258522	0	0	0
T46	22587	0	0	0
T47	32569	0	0	0
T50	687	0	0	0
T61	2399	0	0	0
T70	548	0	0	0
T71	503	0	0	0
T93	0	1	0	0
T124	0	1	0	0
T169	0	1	0	0
T181	0	1	0	0
T184	0	1	0	0
T186	446	0	0	0
T195	0	1	0	0
T196	0	1	0	0
T197	0	1	0	0
T198	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T1,T5,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T27,T38,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T2	VC_COV_UNR
1	Covered	T27,T38,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T27,T38,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T38,T39
1	0	Covered	T1,T2,T13
1	1	Covered	T27,T38,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T38,T39
0	1	Covered	T38
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T27,T38,T39
0	1	Covered	T38,T39,T181
1	0	Covered	T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T27,T38,T39
1	-	Covered	T38,T39,T181

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T27,T38,T39
DetectSt	168	Covered	T27,T38,T39
IdleSt	163	Covered	T1,T5,T2
StableSt	191	Covered	T27,T38,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T27,T38,T39
DebounceSt->IdleSt	163	Covered	T27,T93,T157
DetectSt->IdleSt	186	Covered	T38
DetectSt->StableSt	191	Covered	T27,T38,T39
IdleSt->DebounceSt	148	Covered	T27,T38,T39
StableSt->IdleSt	206	Covered	T38,T39,T101

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T27,T38,T39
0	1	Covered	T27,T38,T39
0	0	Excluded	T1,T5,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T38,T39
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T27,T38,T39
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T27,T38,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T27,T93,T157
DebounceSt	-	0	0	-	-	-	-	Covered	T27,T38,T39
DetectSt	-	-	-	-	1	-	-	Covered	T38
DetectSt	-	-	-	-	0	1	-	Covered	T27,T38,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T38,T39,T181
StableSt	-	-	-	-	-	-	0	Covered	T27,T38,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5823894	121	0	0
CntIncr_A	5823894	60857	0	0
CntNoWrap_A	5823894	5160550	0	0
DetectStDropOut_A	5823894	1	0	0
DetectedOut_A	5823894	5195	0	0
DetectedPulseOut_A	5823894	56	0	0
DisabledIdleSt_A	5823894	5023865	0	0
DisabledNoDetection_A	5823894	5026166	0	0
EnterDebounceSt_A	5823894	65	0	0
EnterDetectSt_A	5823894	57	0	0
EnterStableSt_A	5823894	56	0	0
PulseIsPulse_A	5823894	56	0	0
StayInStableSt	5823894	5111	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5823894	3047	0	0
gen_low_level_sva.LowLevelEvent_A	5823894	5163025	0	0
gen_not_sticky_sva.StableStDropOut_A	5823894	27	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	121	0	0
T27	773	3	0	0
T34	17799	0	0	0
T36	258522	0	0	0
T38	0	6	0	0
T39	0	6	0	0
T46	22587	0	0	0
T47	32569	0	0	0
T50	687	0	0	0
T61	2399	0	0	0
T70	548	0	0	0
T71	503	0	0	0
T90	0	2	0	0
T93	0	1	0	0
T101	0	2	0	0
T171	0	2	0	0
T181	0	4	0	0
T186	446	0	0	0
T199	0	2	0	0
T200	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	60857	0	0
T27	773	120	0	0
T34	17799	0	0	0
T36	258522	0	0	0
T38	0	60	0	0
T39	0	186	0	0
T46	22587	0	0	0
T47	32569	0	0	0
T50	687	0	0	0
T61	2399	0	0	0
T70	548	0	0	0
T71	503	0	0	0
T90	0	47	0	0
T93	0	53	0	0
T101	0	20	0	0
T171	0	65	0	0
T181	0	114	0	0
T186	446	0	0	0
T199	0	15	0	0
T200	0	47	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5160550	0	0
T1	2226	623	0	0
T2	534	133	0	0
T3	4462	972	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	1	0	0
T38	3732	1	0	0
T44	19577	0	0	0
T77	9677	0	0	0
T95	42380	0	0	0
T155	4885	0	0	0
T172	487	0	0	0
T201	734	0	0	0
T202	2772	0	0	0
T203	539	0	0	0
T204	31668	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5195	0	0
T27	773	42	0	0
T34	17799	0	0	0
T36	258522	0	0	0
T38	0	57	0	0
T39	0	116	0	0
T46	22587	0	0	0
T47	32569	0	0	0
T50	687	0	0	0
T61	2399	0	0	0
T70	548	0	0	0
T71	503	0	0	0
T90	0	180	0	0
T101	0	77	0	0
T171	0	171	0	0
T181	0	85	0	0
T182	0	41	0	0
T186	446	0	0	0
T199	0	59	0	0
T200	0	122	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	56	0	0
T27	773	1	0	0
T34	17799	0	0	0
T36	258522	0	0	0
T38	0	2	0	0
T39	0	3	0	0
T46	22587	0	0	0
T47	32569	0	0	0
T50	687	0	0	0
T61	2399	0	0	0
T70	548	0	0	0
T71	503	0	0	0
T90	0	1	0	0
T101	0	1	0	0
T171	0	1	0	0
T181	0	2	0	0
T182	0	1	0	0
T186	446	0	0	0
T199	0	1	0	0
T200	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5023865	0	0
T1	2226	623	0	0
T2	534	133	0	0
T3	4462	972	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5026166	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	65	0	0
T27	773	2	0	0
T34	17799	0	0	0
T36	258522	0	0	0
T38	0	3	0	0
T39	0	3	0	0
T46	22587	0	0	0
T47	32569	0	0	0
T50	687	0	0	0
T61	2399	0	0	0
T70	548	0	0	0
T71	503	0	0	0
T90	0	1	0	0
T93	0	1	0	0
T101	0	1	0	0
T171	0	1	0	0
T181	0	2	0	0
T186	446	0	0	0
T199	0	1	0	0
T200	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	57	0	0
T27	773	1	0	0
T34	17799	0	0	0
T36	258522	0	0	0
T38	0	3	0	0
T39	0	3	0	0
T46	22587	0	0	0
T47	32569	0	0	0
T50	687	0	0	0
T61	2399	0	0	0
T70	548	0	0	0
T71	503	0	0	0
T90	0	1	0	0
T101	0	1	0	0
T171	0	1	0	0
T181	0	2	0	0
T182	0	1	0	0
T186	446	0	0	0
T199	0	1	0	0
T200	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	56	0	0
T27	773	1	0	0
T34	17799	0	0	0
T36	258522	0	0	0
T38	0	2	0	0
T39	0	3	0	0
T46	22587	0	0	0
T47	32569	0	0	0
T50	687	0	0	0
T61	2399	0	0	0
T70	548	0	0	0
T71	503	0	0	0
T90	0	1	0	0
T101	0	1	0	0
T171	0	1	0	0
T181	0	2	0	0
T182	0	1	0	0
T186	446	0	0	0
T199	0	1	0	0
T200	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	56	0	0
T27	773	1	0	0
T34	17799	0	0	0
T36	258522	0	0	0
T38	0	2	0	0
T39	0	3	0	0
T46	22587	0	0	0
T47	32569	0	0	0
T50	687	0	0	0
T61	2399	0	0	0
T70	548	0	0	0
T71	503	0	0	0
T90	0	1	0	0
T101	0	1	0	0
T171	0	1	0	0
T181	0	2	0	0
T182	0	1	0	0
T186	446	0	0	0
T199	0	1	0	0
T200	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5111	0	0
T27	773	40	0	0
T34	17799	0	0	0
T36	258522	0	0	0
T38	0	54	0	0
T39	0	112	0	0
T46	22587	0	0	0
T47	32569	0	0	0
T50	687	0	0	0
T61	2399	0	0	0
T70	548	0	0	0
T71	503	0	0	0
T90	0	178	0	0
T101	0	75	0	0
T171	0	170	0	0
T181	0	82	0	0
T182	0	40	0	0
T186	446	0	0	0
T199	0	58	0	0
T200	0	120	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	3047	0	0
T1	2226	4	0	0
T2	534	1	0	0
T3	4462	13	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	2	0	0
T14	1128	0	0	0
T15	423	2	0	0
T16	984	4	0	0
T17	422	1	0	0
T23	0	4	0	0
T25	0	8	0	0
T32	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5163025	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	27	0	0
T38	3732	1	0	0
T39	0	2	0	0
T44	19577	0	0	0
T77	9677	0	0	0
T91	0	1	0	0
T95	42380	0	0	0
T107	0	1	0	0
T155	4885	0	0	0
T171	0	1	0	0
T172	487	0	0	0
T181	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0
T199	0	1	0	0
T201	734	0	0	0
T202	2772	0	0	0
T203	539	0	0	0
T204	31668	0	0	0
T205	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T1,T2,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T2,T14
1	1	Covered	T1,T2,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T1,T38,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T2	VC_COV_UNR
1	Covered	T1,T38,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T1,T38,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T38,T43
1	0	Covered	T2,T14,T3
1	1	Covered	T1,T38,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T38,T43
0	1	Covered	T206
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T38,T43
0	1	Covered	T1,T38,T43
1	0	Covered	T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T38,T43
1	-	Covered	T1,T38,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T38,T43
DetectSt	168	Covered	T1,T38,T43
IdleSt	163	Covered	T1,T5,T2
StableSt	191	Covered	T1,T38,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T38,T43
DebounceSt->IdleSt	163	Covered	T157,T207,T124
DetectSt->IdleSt	186	Covered	T206
DetectSt->StableSt	191	Covered	T1,T38,T43
IdleSt->DebounceSt	148	Covered	T1,T38,T43
StableSt->IdleSt	206	Covered	T1,T38,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T38,T43
0	1	Covered	T1,T38,T43
0	0	Excluded	T1,T5,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T38,T43
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T38,T43
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T38,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T157
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T38,T43
DetectSt	-	-	-	-	1	-	-	Covered	T206
DetectSt	-	-	-	-	0	1	-	Covered	T1,T38,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T38,T43
StableSt	-	-	-	-	-	-	0	Covered	T1,T38,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5823894	110	0	0
CntIncr_A	5823894	60081	0	0
CntNoWrap_A	5823894	5160561	0	0
DetectStDropOut_A	5823894	1	0	0
DetectedOut_A	5823894	7901	0	0
DetectedPulseOut_A	5823894	53	0	0
DisabledIdleSt_A	5823894	5031870	0	0
DisabledNoDetection_A	5823894	5034180	0	0
EnterDebounceSt_A	5823894	58	0	0
EnterDetectSt_A	5823894	54	0	0
EnterStableSt_A	5823894	53	0	0
PulseIsPulse_A	5823894	53	0	0
StayInStableSt	5823894	7825	0	0
gen_high_level_sva.HighLevelEvent_A	5823894	5163025	0	0
gen_not_sticky_sva.StableStDropOut_A	5823894	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	110	0	0
T1	2226	4	0	0
T2	534	0	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T38	0	4	0	0
T43	0	2	0	0
T90	0	2	0	0
T93	0	10	0	0
T101	0	2	0	0
T171	0	2	0	0
T182	0	2	0	0
T208	0	2	0	0
T209	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	60081	0	0
T1	2226	60	0	0
T2	534	0	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T38	0	40	0	0
T43	0	72	0	0
T90	0	47	0	0
T93	0	216	0	0
T101	0	20	0	0
T171	0	65	0	0
T182	0	28	0	0
T208	0	46	0	0
T209	0	41	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5160561	0	0
T1	2226	619	0	0
T2	534	133	0	0
T3	4462	972	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	1	0	0
T110	11544	0	0	0
T206	627	1	0	0
T210	608	0	0	0
T211	5766	0	0	0
T212	24215	0	0	0
T213	497	0	0	0
T214	490	0	0	0
T215	19300	0	0	0
T216	422	0	0	0
T217	65590	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	7901	0	0
T1	2226	161	0	0
T2	534	0	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T38	0	126	0	0
T43	0	43	0	0
T90	0	90	0	0
T93	0	438	0	0
T101	0	39	0	0
T171	0	235	0	0
T182	0	87	0	0
T208	0	42	0	0
T209	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	53	0	0
T1	2226	2	0	0
T2	534	0	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T38	0	2	0	0
T43	0	1	0	0
T90	0	1	0	0
T93	0	5	0	0
T101	0	1	0	0
T171	0	1	0	0
T182	0	1	0	0
T208	0	1	0	0
T209	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5031870	0	0
T1	2226	293	0	0
T2	534	133	0	0
T3	4462	972	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5034180	0	0
T1	2226	295	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	58	0	0
T1	2226	2	0	0
T2	534	0	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T38	0	2	0	0
T43	0	1	0	0
T90	0	1	0	0
T93	0	5	0	0
T101	0	1	0	0
T171	0	1	0	0
T182	0	1	0	0
T208	0	1	0	0
T209	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	54	0	0
T1	2226	2	0	0
T2	534	0	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T38	0	2	0	0
T43	0	1	0	0
T90	0	1	0	0
T93	0	5	0	0
T101	0	1	0	0
T171	0	1	0	0
T182	0	1	0	0
T208	0	1	0	0
T209	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	53	0	0
T1	2226	2	0	0
T2	534	0	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T38	0	2	0	0
T43	0	1	0	0
T90	0	1	0	0
T93	0	5	0	0
T101	0	1	0	0
T171	0	1	0	0
T182	0	1	0	0
T208	0	1	0	0
T209	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	53	0	0
T1	2226	2	0	0
T2	534	0	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T38	0	2	0	0
T43	0	1	0	0
T90	0	1	0	0
T93	0	5	0	0
T101	0	1	0	0
T171	0	1	0	0
T182	0	1	0	0
T208	0	1	0	0
T209	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	7825	0	0
T1	2226	159	0	0
T2	534	0	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T38	0	123	0	0
T43	0	42	0	0
T90	0	88	0	0
T93	0	432	0	0
T101	0	37	0	0
T171	0	233	0	0
T182	0	86	0	0
T208	0	40	0	0
T209	0	41	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5163025	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	29	0	0
T1	2226	2	0	0
T2	534	0	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T38	0	1	0	0
T43	0	1	0	0
T93	0	4	0	0
T167	0	1	0	0
T179	0	1	0	0
T182	0	1	0	0
T184	0	2	0	0
T205	0	1	0	0
T218	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T14
1	Covered	T1,T5,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T14
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T1,T2,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T2	VC_COV_UNR
1	Covered	T1,T2,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T1,T2,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T27
1	0	Covered	T1,T14,T3
1	1	Covered	T1,T2,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T40
0	1	Covered	T85,T154
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T40
0	1	Covered	T1,T38,T93
1	0	Covered	T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T40
1	-	Covered	T1,T38,T93

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T40
DetectSt	168	Covered	T1,T2,T40
IdleSt	163	Covered	T1,T5,T2
StableSt	191	Covered	T1,T2,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T40
DebounceSt->IdleSt	163	Covered	T83
DetectSt->IdleSt	186	Covered	T85,T154
DetectSt->StableSt	191	Covered	T1,T2,T40
IdleSt->DebounceSt	148	Covered	T1,T2,T40
StableSt->IdleSt	206	Covered	T1,T38,T93

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T40
0	1	Covered	T1,T2,T40
0	0	Excluded	T1,T5,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T40
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T40
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T40
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T40
DetectSt	-	-	-	-	1	-	-	Covered	T85,T154
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T38,T93
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5823894	83	0	0
CntIncr_A	5823894	2158	0	0
CntNoWrap_A	5823894	5160588	0	0
DetectStDropOut_A	5823894	2	0	0
DetectedOut_A	5823894	3338	0	0
DetectedPulseOut_A	5823894	39	0	0
DisabledIdleSt_A	5823894	5143676	0	0
DisabledNoDetection_A	5823894	5145981	0	0
EnterDebounceSt_A	5823894	42	0	0
EnterDetectSt_A	5823894	41	0	0
EnterStableSt_A	5823894	39	0	0
PulseIsPulse_A	5823894	39	0	0
StayInStableSt	5823894	3275	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5823894	6542	0	0
gen_low_level_sva.LowLevelEvent_A	5823894	5163025	0	0
gen_not_sticky_sva.StableStDropOut_A	5823894	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	83	0	0
T1	2226	4	0	0
T2	534	2	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T38	0	2	0	0
T40	0	2	0	0
T43	0	2	0	0
T85	0	4	0	0
T93	0	8	0	0
T182	0	2	0	0
T199	0	4	0	0
T200	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	2158	0	0
T1	2226	60	0	0
T2	534	41	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T38	0	20	0	0
T40	0	96	0	0
T43	0	72	0	0
T85	0	34	0	0
T93	0	163	0	0
T182	0	28	0	0
T199	0	30	0	0
T200	0	94	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5160588	0	0
T1	2226	619	0	0
T2	534	131	0	0
T3	4462	972	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	2	0	0
T85	657	1	0	0
T102	7258	0	0	0
T141	491	0	0	0
T142	11934	0	0	0
T143	437	0	0	0
T144	721	0	0	0
T154	0	1	0	0
T219	402	0	0	0
T220	27728	0	0	0
T221	20344	0	0	0
T222	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	3338	0	0
T1	2226	42	0	0
T2	534	42	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T38	0	58	0	0
T40	0	181	0	0
T43	0	430	0	0
T85	0	71	0	0
T93	0	297	0	0
T182	0	42	0	0
T199	0	43	0	0
T200	0	83	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	39	0	0
T1	2226	2	0	0
T2	534	1	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T85	0	1	0	0
T93	0	4	0	0
T182	0	1	0	0
T199	0	2	0	0
T200	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5143676	0	0
T1	2226	293	0	0
T2	534	3	0	0
T3	4462	972	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5145981	0	0
T1	2226	295	0	0
T2	534	3	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	42	0	0
T1	2226	2	0	0
T2	534	1	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T85	0	2	0	0
T93	0	4	0	0
T182	0	1	0	0
T199	0	2	0	0
T200	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	41	0	0
T1	2226	2	0	0
T2	534	1	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T85	0	2	0	0
T93	0	4	0	0
T182	0	1	0	0
T199	0	2	0	0
T200	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	39	0	0
T1	2226	2	0	0
T2	534	1	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T85	0	1	0	0
T93	0	4	0	0
T182	0	1	0	0
T199	0	2	0	0
T200	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	39	0	0
T1	2226	2	0	0
T2	534	1	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T85	0	1	0	0
T93	0	4	0	0
T182	0	1	0	0
T199	0	2	0	0
T200	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	3275	0	0
T1	2226	39	0	0
T2	534	40	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T38	0	57	0	0
T40	0	179	0	0
T43	0	428	0	0
T85	0	69	0	0
T93	0	290	0	0
T182	0	40	0	0
T199	0	40	0	0
T200	0	80	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	6542	0	0
T1	2226	2	0	0
T2	534	1	0	0
T3	4462	11	0	0
T4	0	11	0	0
T5	402	0	0	0
T6	0	34	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	5	0	0
T15	423	1	0	0
T16	984	0	0	0
T17	422	2	0	0
T23	0	8	0	0
T32	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5163025	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	14	0	0
T1	2226	1	0	0
T2	534	0	0	0
T3	4462	0	0	0
T5	402	0	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T38	0	1	0	0
T93	0	1	0	0
T167	0	1	0	0
T170	0	1	0	0
T184	0	2	0	0
T196	0	1	0	0
T199	0	1	0	0
T200	0	1	0	0
T223	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T1,T3,T15

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T3,T15
1	1	Covered	T1,T3,T15

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T27,T35,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T2	VC_COV_UNR
1	Covered	T27,T35,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T27,T35,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T27,T35
1	0	Covered	T1,T3,T15
1	1	Covered	T27,T35,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T35,T42
0	1	Covered	T168,T154
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T27,T35,T42
0	1	Covered	T35,T44,T78
1	0	Covered	T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T27,T35,T42
1	-	Covered	T35,T44,T78

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T27,T35,T42
DetectSt	168	Covered	T27,T35,T42
IdleSt	163	Covered	T1,T5,T2
StableSt	191	Covered	T27,T35,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T27,T35,T42
DebounceSt->IdleSt	163	Covered	T183,T157,T83
DetectSt->IdleSt	186	Covered	T168,T154
DetectSt->StableSt	191	Covered	T27,T35,T42
IdleSt->DebounceSt	148	Covered	T27,T35,T42
StableSt->IdleSt	206	Covered	T35,T44,T78

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T27,T35,T42
0	1	Covered	T27,T35,T42
0	0	Excluded	T1,T5,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T35,T42
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T27,T35,T42
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T27,T35,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T183,T157,T170
DebounceSt	-	0	0	-	-	-	-	Covered	T27,T35,T42
DetectSt	-	-	-	-	1	-	-	Covered	T168,T154
DetectSt	-	-	-	-	0	1	-	Covered	T27,T35,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T44,T78
StableSt	-	-	-	-	-	-	0	Covered	T27,T35,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5823894	136	0	0
CntIncr_A	5823894	59201	0	0
CntNoWrap_A	5823894	5160535	0	0
DetectStDropOut_A	5823894	2	0	0
DetectedOut_A	5823894	7074	0	0
DetectedPulseOut_A	5823894	63	0	0
DisabledIdleSt_A	5823894	5027215	0	0
DisabledNoDetection_A	5823894	5029514	0	0
EnterDebounceSt_A	5823894	72	0	0
EnterDetectSt_A	5823894	65	0	0
EnterStableSt_A	5823894	63	0	0
PulseIsPulse_A	5823894	63	0	0
StayInStableSt	5823894	6985	0	0
gen_high_level_sva.HighLevelEvent_A	5823894	5163025	0	0
gen_not_sticky_sva.StableStDropOut_A	5823894	36	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	136	0	0
T27	773	2	0	0
T34	17799	0	0	0
T35	0	4	0	0
T36	258522	0	0	0
T39	0	4	0	0
T42	0	2	0	0
T44	0	6	0	0
T46	22587	0	0	0
T47	32569	0	0	0
T50	687	0	0	0
T61	2399	0	0	0
T70	548	0	0	0
T71	503	0	0	0
T78	0	2	0	0
T93	0	10	0	0
T101	0	2	0	0
T181	0	4	0	0
T186	446	0	0	0
T199	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	59201	0	0
T27	773	60	0	0
T34	17799	0	0	0
T35	0	190	0	0
T36	258522	0	0	0
T39	0	124	0	0
T42	0	43	0	0
T44	0	78	0	0
T46	22587	0	0	0
T47	32569	0	0	0
T50	687	0	0	0
T61	2399	0	0	0
T70	548	0	0	0
T71	503	0	0	0
T78	0	43	0	0
T93	0	171	0	0
T101	0	20	0	0
T181	0	114	0	0
T186	446	0	0	0
T199	0	15	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5160535	0	0
T1	2226	623	0	0
T2	534	133	0	0
T3	4462	972	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	2	0	0
T154	0	1	0	0
T168	1098	1	0	0
T188	741	0	0	0
T189	570	0	0	0
T190	1249	0	0	0
T191	14697	0	0	0
T192	25070	0	0	0
T193	424	0	0	0
T194	490	0	0	0
T224	782	0	0	0
T225	1166	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	7074	0	0
T27	773	304	0	0
T34	17799	0	0	0
T35	0	147	0	0
T36	258522	0	0	0
T39	0	271	0	0
T42	0	68	0	0
T44	0	74	0	0
T46	22587	0	0	0
T47	32569	0	0	0
T50	687	0	0	0
T61	2399	0	0	0
T70	548	0	0	0
T71	503	0	0	0
T78	0	3	0	0
T93	0	163	0	0
T101	0	18	0	0
T181	0	197	0	0
T186	446	0	0	0
T199	0	79	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	63	0	0
T27	773	1	0	0
T34	17799	0	0	0
T35	0	2	0	0
T36	258522	0	0	0
T39	0	2	0	0
T42	0	1	0	0
T44	0	3	0	0
T46	22587	0	0	0
T47	32569	0	0	0
T50	687	0	0	0
T61	2399	0	0	0
T70	548	0	0	0
T71	503	0	0	0
T78	0	1	0	0
T93	0	5	0	0
T101	0	1	0	0
T181	0	2	0	0
T186	446	0	0	0
T199	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5027215	0	0
T1	2226	623	0	0
T2	534	3	0	0
T3	4462	972	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5029514	0	0
T1	2226	626	0	0
T2	534	3	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	72	0	0
T27	773	1	0	0
T34	17799	0	0	0
T35	0	2	0	0
T36	258522	0	0	0
T39	0	2	0	0
T42	0	1	0	0
T44	0	3	0	0
T46	22587	0	0	0
T47	32569	0	0	0
T50	687	0	0	0
T61	2399	0	0	0
T70	548	0	0	0
T71	503	0	0	0
T78	0	1	0	0
T93	0	5	0	0
T101	0	1	0	0
T181	0	2	0	0
T186	446	0	0	0
T199	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	65	0	0
T27	773	1	0	0
T34	17799	0	0	0
T35	0	2	0	0
T36	258522	0	0	0
T39	0	2	0	0
T42	0	1	0	0
T44	0	3	0	0
T46	22587	0	0	0
T47	32569	0	0	0
T50	687	0	0	0
T61	2399	0	0	0
T70	548	0	0	0
T71	503	0	0	0
T78	0	1	0	0
T93	0	5	0	0
T101	0	1	0	0
T181	0	2	0	0
T186	446	0	0	0
T199	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	63	0	0
T27	773	1	0	0
T34	17799	0	0	0
T35	0	2	0	0
T36	258522	0	0	0
T39	0	2	0	0
T42	0	1	0	0
T44	0	3	0	0
T46	22587	0	0	0
T47	32569	0	0	0
T50	687	0	0	0
T61	2399	0	0	0
T70	548	0	0	0
T71	503	0	0	0
T78	0	1	0	0
T93	0	5	0	0
T101	0	1	0	0
T181	0	2	0	0
T186	446	0	0	0
T199	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	63	0	0
T27	773	1	0	0
T34	17799	0	0	0
T35	0	2	0	0
T36	258522	0	0	0
T39	0	2	0	0
T42	0	1	0	0
T44	0	3	0	0
T46	22587	0	0	0
T47	32569	0	0	0
T50	687	0	0	0
T61	2399	0	0	0
T70	548	0	0	0
T71	503	0	0	0
T78	0	1	0	0
T93	0	5	0	0
T101	0	1	0	0
T181	0	2	0	0
T186	446	0	0	0
T199	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	6985	0	0
T27	773	302	0	0
T34	17799	0	0	0
T35	0	144	0	0
T36	258522	0	0	0
T39	0	268	0	0
T42	0	66	0	0
T44	0	70	0	0
T46	22587	0	0	0
T47	32569	0	0	0
T50	687	0	0	0
T61	2399	0	0	0
T70	548	0	0	0
T71	503	0	0	0
T78	0	2	0	0
T93	0	156	0	0
T101	0	17	0	0
T181	0	194	0	0
T186	446	0	0	0
T199	0	78	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5163025	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	36	0	0
T35	40117	1	0	0
T37	894	0	0	0
T39	0	1	0	0
T40	940	0	0	0
T44	0	2	0	0
T63	492	0	0	0
T78	0	1	0	0
T93	0	3	0	0
T101	0	1	0	0
T111	502	0	0	0
T112	1657	0	0	0
T113	25808	0	0	0
T114	402	0	0	0
T115	408	0	0	0
T116	501	0	0	0
T179	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T199	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T15
1	Covered	T1,T5,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T37,T41,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T2	VC_COV_UNR
1	Covered	T37,T41,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T37,T41,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T27,T37
1	0	Covered	T1,T3,T15
1	1	Covered	T37,T41,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T37,T41,T38
0	1	Covered	T226
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T37,T41,T38
0	1	Covered	T38,T43,T39
1	0	Covered	T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T37,T41,T38
1	-	Covered	T38,T43,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T37,T41,T38
DetectSt	168	Covered	T37,T41,T38
IdleSt	163	Covered	T1,T5,T2
StableSt	191	Covered	T37,T41,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T37,T41,T38
DebounceSt->IdleSt	163	Covered	T93,T83
DetectSt->IdleSt	186	Covered	T226
DetectSt->StableSt	191	Covered	T37,T41,T38
IdleSt->DebounceSt	148	Covered	T37,T41,T38
StableSt->IdleSt	206	Covered	T38,T155,T78

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T37,T41,T38
0	1	Covered	T37,T41,T38
0	0	Excluded	T1,T5,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T37,T41,T38
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T37,T41,T38
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T37,T41,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T93
DebounceSt	-	0	0	-	-	-	-	Covered	T37,T41,T38
DetectSt	-	-	-	-	1	-	-	Covered	T226
DetectSt	-	-	-	-	0	1	-	Covered	T37,T41,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T38,T43,T39
StableSt	-	-	-	-	-	-	0	Covered	T37,T41,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5823894	94	0	0
CntIncr_A	5823894	2591	0	0
CntNoWrap_A	5823894	5160577	0	0
DetectStDropOut_A	5823894	1	0	0
DetectedOut_A	5823894	3810	0	0
DetectedPulseOut_A	5823894	45	0	0
DisabledIdleSt_A	5823894	5136564	0	0
DisabledNoDetection_A	5823894	5138858	0	0
EnterDebounceSt_A	5823894	48	0	0
EnterDetectSt_A	5823894	46	0	0
EnterStableSt_A	5823894	45	0	0
PulseIsPulse_A	5823894	45	0	0
StayInStableSt	5823894	3737	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5823894	6349	0	0
gen_low_level_sva.LowLevelEvent_A	5823894	5163025	0	0
gen_not_sticky_sva.StableStDropOut_A	5823894	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	94	0	0
T37	894	2	0	0
T38	0	2	0	0
T39	0	4	0	0
T40	940	0	0	0
T41	0	2	0	0
T43	0	4	0	0
T63	492	0	0	0
T78	0	2	0	0
T93	0	5	0	0
T113	25808	0	0	0
T114	402	0	0	0
T115	408	0	0	0
T116	501	0	0	0
T155	0	2	0	0
T181	0	2	0	0
T183	0	2	0	0
T227	518	0	0	0
T228	402	0	0	0
T229	697	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	2591	0	0
T37	894	78	0	0
T38	0	20	0	0
T39	0	111	0	0
T40	940	0	0	0
T41	0	61	0	0
T43	0	144	0	0
T63	492	0	0	0
T78	0	43	0	0
T93	0	106	0	0
T113	25808	0	0	0
T114	402	0	0	0
T115	408	0	0	0
T116	501	0	0	0
T155	0	90	0	0
T181	0	57	0	0
T183	0	70	0	0
T227	518	0	0	0
T228	402	0	0	0
T229	697	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5160577	0	0
T1	2226	623	0	0
T2	534	133	0	0
T3	4462	972	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	1	0	0
T226	8392	1	0	0
T230	2251	0	0	0
T231	4767	0	0	0
T232	4360	0	0	0
T233	28620	0	0	0
T234	217172	0	0	0
T235	493	0	0	0
T236	761	0	0	0
T237	421	0	0	0
T238	712	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	3810	0	0
T37	894	135	0	0
T38	0	59	0	0
T39	0	76	0	0
T40	940	0	0	0
T41	0	39	0	0
T43	0	242	0	0
T63	492	0	0	0
T78	0	40	0	0
T93	0	85	0	0
T113	25808	0	0	0
T114	402	0	0	0
T115	408	0	0	0
T116	501	0	0	0
T155	0	39	0	0
T181	0	39	0	0
T183	0	306	0	0
T227	518	0	0	0
T228	402	0	0	0
T229	697	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	45	0	0
T37	894	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	940	0	0	0
T41	0	1	0	0
T43	0	2	0	0
T63	492	0	0	0
T78	0	1	0	0
T93	0	2	0	0
T113	25808	0	0	0
T114	402	0	0	0
T115	408	0	0	0
T116	501	0	0	0
T155	0	1	0	0
T181	0	1	0	0
T183	0	1	0	0
T227	518	0	0	0
T228	402	0	0	0
T229	697	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5136564	0	0
T1	2226	623	0	0
T2	534	3	0	0
T3	4462	972	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5138858	0	0
T1	2226	626	0	0
T2	534	3	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	48	0	0
T37	894	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	940	0	0	0
T41	0	1	0	0
T43	0	2	0	0
T63	492	0	0	0
T78	0	1	0	0
T93	0	3	0	0
T113	25808	0	0	0
T114	402	0	0	0
T115	408	0	0	0
T116	501	0	0	0
T155	0	1	0	0
T181	0	1	0	0
T183	0	1	0	0
T227	518	0	0	0
T228	402	0	0	0
T229	697	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	46	0	0
T37	894	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	940	0	0	0
T41	0	1	0	0
T43	0	2	0	0
T63	492	0	0	0
T78	0	1	0	0
T93	0	2	0	0
T113	25808	0	0	0
T114	402	0	0	0
T115	408	0	0	0
T116	501	0	0	0
T155	0	1	0	0
T181	0	1	0	0
T183	0	1	0	0
T227	518	0	0	0
T228	402	0	0	0
T229	697	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	45	0	0
T37	894	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	940	0	0	0
T41	0	1	0	0
T43	0	2	0	0
T63	492	0	0	0
T78	0	1	0	0
T93	0	2	0	0
T113	25808	0	0	0
T114	402	0	0	0
T115	408	0	0	0
T116	501	0	0	0
T155	0	1	0	0
T181	0	1	0	0
T183	0	1	0	0
T227	518	0	0	0
T228	402	0	0	0
T229	697	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	45	0	0
T37	894	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	940	0	0	0
T41	0	1	0	0
T43	0	2	0	0
T63	492	0	0	0
T78	0	1	0	0
T93	0	2	0	0
T113	25808	0	0	0
T114	402	0	0	0
T115	408	0	0	0
T116	501	0	0	0
T155	0	1	0	0
T181	0	1	0	0
T183	0	1	0	0
T227	518	0	0	0
T228	402	0	0	0
T229	697	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	3737	0	0
T37	894	133	0	0
T38	0	58	0	0
T39	0	73	0	0
T40	940	0	0	0
T41	0	37	0	0
T43	0	239	0	0
T63	492	0	0	0
T78	0	38	0	0
T93	0	82	0	0
T113	25808	0	0	0
T114	402	0	0	0
T115	408	0	0	0
T116	501	0	0	0
T155	0	37	0	0
T181	0	38	0	0
T183	0	304	0	0
T227	518	0	0	0
T228	402	0	0	0
T229	697	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	6349	0	0
T1	2226	1	0	0
T2	534	0	0	0
T3	4462	7	0	0
T4	0	12	0	0
T5	402	0	0	0
T6	0	33	0	0
T12	402	0	0	0
T13	683	0	0	0
T14	1128	0	0	0
T15	423	3	0	0
T16	984	0	0	0
T17	422	2	0	0
T23	0	9	0	0
T25	0	5	0	0
T26	0	5	0	0
T55	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5163025	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	16	0	0
T38	3732	1	0	0
T39	0	1	0	0
T43	0	1	0	0
T44	19577	0	0	0
T77	9677	0	0	0
T91	0	1	0	0
T93	0	1	0	0
T95	42380	0	0	0
T124	0	1	0	0
T145	0	1	0	0
T155	4885	0	0	0
T172	487	0	0	0
T181	0	1	0	0
T195	0	1	0	0
T201	734	0	0	0
T202	2772	0	0	0
T203	539	0	0	0
T204	31668	0	0	0
T218	0	1	0	0