Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T29,T11
1	Covered	T1,T5,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T6,T29,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T6,T29,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T6,T29,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T29,T11
1	0	Covered	T6,T29,T11
1	1	Covered	T6,T29,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T29,T11
0	1	Covered	T11,T34,T74
1	0	Covered	T11,T34,T84

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T29,T45
0	1	Covered	T6,T29,T45
1	0	Covered	T252,T253,T254

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T29,T45
1	-	Covered	T6,T29,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T29,T11
DetectSt	168	Covered	T6,T29,T11
IdleSt	163	Covered	T1,T5,T2
StableSt	191	Covered	T6,T29,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T29,T11
DebounceSt->IdleSt	163	Covered	T94,T83,T231
DetectSt->IdleSt	186	Covered	T11,T34,T74
DetectSt->StableSt	191	Covered	T6,T29,T45
IdleSt->DebounceSt	148	Covered	T6,T29,T11
StableSt->IdleSt	206	Covered	T6,T29,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T29,T11
0	1	Covered	T6,T29,T11
0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T29,T11
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T6,T29,T11
IdleSt	0	-	-	-	-	-	-	Covered	T6,T29,T11
DebounceSt	-	1	-	-	-	-	-	Covered	T83,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T29,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T94,T83,T231
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T29,T11
DetectSt	-	-	-	-	1	-	-	Covered	T11,T34,T74
DetectSt	-	-	-	-	0	1	-	Covered	T6,T29,T45
DetectSt	-	-	-	-	0	0	-	Covered	T6,T29,T11
StableSt	-	-	-	-	-	-	1	Covered	T6,T29,T45
StableSt	-	-	-	-	-	-	0	Covered	T6,T29,T45
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5823894	3240	0	0
CntIncr_A	5823894	123606	0	0
CntNoWrap_A	5823894	5157431	0	0
DetectStDropOut_A	5823894	481	0	0
DetectedOut_A	5823894	88571	0	0
DetectedPulseOut_A	5823894	948	0	0
DisabledIdleSt_A	5823894	4629909	0	0
DisabledNoDetection_A	5823894	4632060	0	0
EnterDebounceSt_A	5823894	1631	0	0
EnterDetectSt_A	5823894	1610	0	0
EnterStableSt_A	5823894	948	0	0
PulseIsPulse_A	5823894	948	0	0
StayInStableSt	5823894	87514	0	0
gen_high_event_sva.HighLevelEvent_A	5823894	5163025	0	0
gen_high_level_sva.HighLevelEvent_A	5823894	5163025	0	0
gen_not_sticky_sva.StableStDropOut_A	5823894	824	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	3240	0	0
T6	20803	54	0	0
T7	21857	0	0	0
T8	2288	0	0	0
T11	0	14	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T29	0	24	0	0
T34	0	22	0	0
T45	0	20	0	0
T46	0	42	0	0
T47	0	14	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T73	0	40	0	0
T74	0	60	0	0
T75	0	42	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	123606	0	0
T6	20803	1485	0	0
T7	21857	0	0	0
T8	2288	0	0	0
T11	0	528	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T29	0	756	0	0
T34	0	661	0	0
T45	0	380	0	0
T46	0	3234	0	0
T47	0	1848	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T73	0	700	0	0
T74	0	1440	0	0
T75	0	966	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5157431	0	0
T1	2226	623	0	0
T2	534	133	0	0
T3	4462	972	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	481	0	0
T11	12359	2	0	0
T21	2140	0	0	0
T22	2297	0	0	0
T34	0	6	0	0
T45	32312	0	0	0
T49	646	0	0	0
T69	503	0	0	0
T74	0	30	0	0
T82	991	0	0	0
T84	0	10	0	0
T97	0	26	0	0
T98	0	13	0	0
T102	0	19	0	0
T103	0	16	0	0
T104	0	18	0	0
T255	0	18	0	0
T256	762	0	0	0
T257	580	0	0	0
T258	842	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	88571	0	0
T6	20803	2777	0	0
T7	21857	0	0	0
T8	2288	0	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T29	0	146	0	0
T45	0	1790	0	0
T46	0	5491	0	0
T47	0	5568	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T73	0	1478	0	0
T75	0	672	0	0
T86	0	386	0	0
T94	0	522	0	0
T239	0	30	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	948	0	0
T6	20803	27	0	0
T7	21857	0	0	0
T8	2288	0	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T29	0	12	0	0
T45	0	10	0	0
T46	0	21	0	0
T47	0	7	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T73	0	20	0	0
T75	0	21	0	0
T86	0	5	0	0
T94	0	4	0	0
T239	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	4629909	0	0
T1	2226	623	0	0
T2	534	133	0	0
T3	4462	972	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	4632060	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	1631	0	0
T6	20803	27	0	0
T7	21857	0	0	0
T8	2288	0	0	0
T11	0	7	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T29	0	12	0	0
T34	0	11	0	0
T45	0	10	0	0
T46	0	21	0	0
T47	0	7	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T73	0	20	0	0
T74	0	30	0	0
T75	0	21	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	1610	0	0
T6	20803	27	0	0
T7	21857	0	0	0
T8	2288	0	0	0
T11	0	7	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T29	0	12	0	0
T34	0	11	0	0
T45	0	10	0	0
T46	0	21	0	0
T47	0	7	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T73	0	20	0	0
T74	0	30	0	0
T75	0	21	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	948	0	0
T6	20803	27	0	0
T7	21857	0	0	0
T8	2288	0	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T29	0	12	0	0
T45	0	10	0	0
T46	0	21	0	0
T47	0	7	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T73	0	20	0	0
T75	0	21	0	0
T86	0	5	0	0
T94	0	4	0	0
T239	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	948	0	0
T6	20803	27	0	0
T7	21857	0	0	0
T8	2288	0	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T29	0	12	0	0
T45	0	10	0	0
T46	0	21	0	0
T47	0	7	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T73	0	20	0	0
T75	0	21	0	0
T86	0	5	0	0
T94	0	4	0	0
T239	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	87514	0	0
T6	20803	2744	0	0
T7	21857	0	0	0
T8	2288	0	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T29	0	134	0	0
T45	0	1773	0	0
T46	0	5470	0	0
T47	0	5556	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T73	0	1458	0	0
T75	0	651	0	0
T86	0	380	0	0
T94	0	518	0	0
T239	0	26	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5163025	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5163025	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	824	0	0
T6	20803	21	0	0
T7	21857	0	0	0
T8	2288	0	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T29	0	12	0	0
T45	0	3	0	0
T46	0	21	0	0
T47	0	2	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T73	0	20	0	0
T75	0	21	0	0
T86	0	4	0	0
T94	0	4	0	0
T239	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T4,T6
1	Covered	T1,T5,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T3,T4,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T2	VC_COV_UNR
1	Covered	T3,T4,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T3,T4,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T3,T32
1	1	Covered	T3,T4,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T6
0	1	Covered	T35,T96,T99
1	0	Covered	T83,T58

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T6
0	1	Covered	T3,T4,T6
1	0	Covered	T73,T83,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T4,T6
1	-	Covered	T3,T4,T6

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T4,T6
DetectSt	168	Covered	T3,T4,T6
IdleSt	163	Covered	T1,T5,T2
StableSt	191	Covered	T3,T4,T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T4,T6
DebounceSt->IdleSt	163	Covered	T33,T126,T35
DetectSt->IdleSt	186	Covered	T35,T96,T99
DetectSt->StableSt	191	Covered	T3,T4,T6
IdleSt->DebounceSt	148	Covered	T3,T4,T6
StableSt->IdleSt	206	Covered	T3,T4,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T4,T6
0	1	Covered	T3,T4,T6
0	0	Excluded	T1,T5,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T6
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T4,T6
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T83,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T4,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T33,T126,T35
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T4,T6
DetectSt	-	-	-	-	1	-	-	Covered	T35,T96,T99
DetectSt	-	-	-	-	0	1	-	Covered	T3,T4,T6
DetectSt	-	-	-	-	0	0	-	Covered	T3,T4,T6
StableSt	-	-	-	-	-	-	1	Covered	T3,T4,T6
StableSt	-	-	-	-	-	-	0	Covered	T3,T4,T6
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5823894	867	0	0
CntIncr_A	5823894	47653	0	0
CntNoWrap_A	5823894	5159804	0	0
DetectStDropOut_A	5823894	56	0	0
DetectedOut_A	5823894	14189	0	0
DetectedPulseOut_A	5823894	336	0	0
DisabledIdleSt_A	5823894	4786413	0	0
DisabledNoDetection_A	5823894	4788058	0	0
EnterDebounceSt_A	5823894	472	0	0
EnterDetectSt_A	5823894	396	0	0
EnterStableSt_A	5823894	336	0	0
PulseIsPulse_A	5823894	336	0	0
StayInStableSt	5823894	13816	0	0
gen_high_level_sva.HighLevelEvent_A	5823894	5163025	0	0
gen_not_sticky_sva.StableStDropOut_A	5823894	296	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	867	0	0
T3	4462	2	0	0
T4	28273	12	0	0
T6	20803	12	0	0
T9	0	2	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T23	491	0	0	0
T25	3703	0	0	0
T28	18583	0	0	0
T32	2718	0	0	0
T33	0	11	0	0
T45	0	14	0	0
T46	0	10	0	0
T47	0	10	0	0
T61	0	2	0	0
T73	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	47653	0	0
T3	4462	25	0	0
T4	28273	990	0	0
T6	20803	354	0	0
T9	0	78	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T23	491	0	0	0
T25	3703	0	0	0
T28	18583	0	0	0
T32	2718	0	0	0
T33	0	728	0	0
T45	0	483	0	0
T46	0	870	0	0
T47	0	1320	0	0
T61	0	25	0	0
T73	0	195	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5159804	0	0
T1	2226	623	0	0
T2	534	133	0	0
T3	4462	970	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	56	0	0
T35	40117	1	0	0
T37	894	0	0	0
T39	0	7	0	0
T40	940	0	0	0
T63	492	0	0	0
T96	0	5	0	0
T99	0	4	0	0
T100	0	11	0	0
T101	0	2	0	0
T105	0	12	0	0
T106	0	1	0	0
T107	0	5	0	0
T108	0	1	0	0
T111	502	0	0	0
T112	1657	0	0	0
T113	25808	0	0	0
T114	402	0	0	0
T115	408	0	0	0
T116	501	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	14189	0	0
T3	4462	4	0	0
T4	28273	216	0	0
T6	20803	400	0	0
T9	0	58	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T23	491	0	0	0
T25	3703	0	0	0
T28	18583	0	0	0
T32	2718	0	0	0
T33	0	333	0	0
T45	0	332	0	0
T46	0	439	0	0
T47	0	458	0	0
T61	0	3	0	0
T73	0	150	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	336	0	0
T3	4462	1	0	0
T4	28273	6	0	0
T6	20803	6	0	0
T9	0	1	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T23	491	0	0	0
T25	3703	0	0	0
T28	18583	0	0	0
T32	2718	0	0	0
T33	0	5	0	0
T45	0	7	0	0
T46	0	5	0	0
T47	0	5	0	0
T61	0	1	0	0
T73	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	4786413	0	0
T1	2226	623	0	0
T2	534	133	0	0
T3	4462	899	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	4788058	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	907	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	472	0	0
T3	4462	1	0	0
T4	28273	6	0	0
T6	20803	6	0	0
T9	0	1	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T23	491	0	0	0
T25	3703	0	0	0
T28	18583	0	0	0
T32	2718	0	0	0
T33	0	6	0	0
T45	0	7	0	0
T46	0	5	0	0
T47	0	5	0	0
T61	0	1	0	0
T73	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	396	0	0
T3	4462	1	0	0
T4	28273	6	0	0
T6	20803	6	0	0
T9	0	1	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T23	491	0	0	0
T25	3703	0	0	0
T28	18583	0	0	0
T32	2718	0	0	0
T33	0	5	0	0
T45	0	7	0	0
T46	0	5	0	0
T47	0	5	0	0
T61	0	1	0	0
T73	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	336	0	0
T3	4462	1	0	0
T4	28273	6	0	0
T6	20803	6	0	0
T9	0	1	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T23	491	0	0	0
T25	3703	0	0	0
T28	18583	0	0	0
T32	2718	0	0	0
T33	0	5	0	0
T45	0	7	0	0
T46	0	5	0	0
T47	0	5	0	0
T61	0	1	0	0
T73	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	336	0	0
T3	4462	1	0	0
T4	28273	6	0	0
T6	20803	6	0	0
T9	0	1	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T23	491	0	0	0
T25	3703	0	0	0
T28	18583	0	0	0
T32	2718	0	0	0
T33	0	5	0	0
T45	0	7	0	0
T46	0	5	0	0
T47	0	5	0	0
T61	0	1	0	0
T73	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	13816	0	0
T3	4462	3	0	0
T4	28273	210	0	0
T6	20803	394	0	0
T9	0	57	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T23	491	0	0	0
T25	3703	0	0	0
T28	18583	0	0	0
T32	2718	0	0	0
T33	0	328	0	0
T45	0	325	0	0
T46	0	434	0	0
T47	0	448	0	0
T61	0	2	0	0
T73	0	147	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5163025	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	296	0	0
T3	4462	1	0	0
T4	28273	6	0	0
T6	20803	6	0	0
T9	0	1	0	0
T15	423	0	0	0
T16	984	0	0	0
T17	422	0	0	0
T23	491	0	0	0
T25	3703	0	0	0
T28	18583	0	0	0
T32	2718	0	0	0
T33	0	5	0	0
T45	0	7	0	0
T46	0	5	0	0
T61	0	1	0	0
T73	0	2	0	0
T126	0	6	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T29,T11
1	Covered	T1,T5,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T6,T29,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T6,T29,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T6,T29,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T29,T11
1	0	Covered	T6,T29,T11
1	1	Covered	T6,T29,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T29,T11
0	1	Covered	T6,T47,T34
1	0	Covered	T6,T47,T34

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T11,T45
0	1	Covered	T29,T11,T45
1	0	Covered	T86,T259,T260

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T29,T11,T45
1	-	Covered	T29,T11,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T29,T11
DetectSt	168	Covered	T6,T29,T11
IdleSt	163	Covered	T1,T5,T2
StableSt	191	Covered	T29,T11,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T29,T11
DebounceSt->IdleSt	163	Covered	T94,T83,T231
DetectSt->IdleSt	186	Covered	T6,T47,T34
DetectSt->StableSt	191	Covered	T29,T11,T45
IdleSt->DebounceSt	148	Covered	T6,T29,T11
StableSt->IdleSt	206	Covered	T29,T11,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T29,T11
0	1	Covered	T6,T29,T11
0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T29,T11
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T6,T29,T11
IdleSt	0	-	-	-	-	-	-	Covered	T6,T29,T11
DebounceSt	-	1	-	-	-	-	-	Covered	T83,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T29,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T94,T83,T231
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T29,T11
DetectSt	-	-	-	-	1	-	-	Covered	T6,T47,T34
DetectSt	-	-	-	-	0	1	-	Covered	T29,T11,T45
DetectSt	-	-	-	-	0	0	-	Covered	T6,T29,T11
StableSt	-	-	-	-	-	-	1	Covered	T29,T11,T45
StableSt	-	-	-	-	-	-	0	Covered	T29,T11,T45
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5823894	3041	0	0
CntIncr_A	5823894	135935	0	0
CntNoWrap_A	5823894	5157630	0	0
DetectStDropOut_A	5823894	459	0	0
DetectedOut_A	5823894	74918	0	0
DetectedPulseOut_A	5823894	792	0	0
DisabledIdleSt_A	5823894	4639359	0	0
DisabledNoDetection_A	5823894	4641518	0	0
EnterDebounceSt_A	5823894	1539	0	0
EnterDetectSt_A	5823894	1502	0	0
EnterStableSt_A	5823894	792	0	0
PulseIsPulse_A	5823894	792	0	0
StayInStableSt	5823894	74025	0	0
gen_high_event_sva.HighLevelEvent_A	5823894	5163025	0	0
gen_high_level_sva.HighLevelEvent_A	5823894	5163025	0	0
gen_not_sticky_sva.StableStDropOut_A	5823894	659	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	3041	0	0
T6	20803	52	0	0
T7	21857	0	0	0
T8	2288	0	0	0
T11	0	62	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T29	0	48	0	0
T34	0	22	0	0
T45	0	14	0	0
T46	0	54	0	0
T47	0	48	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T73	0	20	0	0
T74	0	18	0	0
T75	0	16	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	135935	0	0
T6	20803	2021	0	0
T7	21857	0	0	0
T8	2288	0	0	0
T11	0	1705	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T29	0	1608	0	0
T34	0	661	0	0
T45	0	259	0	0
T46	0	8042	0	0
T47	0	6941	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T73	0	598	0	0
T74	0	432	0	0
T75	0	550	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5157630	0	0
T1	2226	623	0	0
T2	534	133	0	0
T3	4462	972	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	459	0	0
T6	20803	11	0	0
T7	21857	0	0	0
T8	2288	0	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T34	0	6	0	0
T46	0	5	0	0
T47	0	23	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T74	0	9	0	0
T84	0	10	0	0
T97	0	15	0	0
T98	0	27	0	0
T102	0	2	0	0
T103	0	24	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	74918	0	0
T10	29861	0	0	0
T11	12359	2560	0	0
T29	7627	342	0	0
T45	32312	1196	0	0
T49	646	0	0	0
T69	503	0	0	0
T81	1088	0	0	0
T82	991	0	0	0
T86	0	622	0	0
T94	0	137	0	0
T142	0	1626	0	0
T239	0	1389	0	0
T252	0	2397	0	0
T256	762	0	0	0
T257	580	0	0	0
T261	0	2513	0	0
T262	0	646	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	792	0	0
T10	29861	0	0	0
T11	12359	31	0	0
T29	7627	24	0	0
T45	32312	7	0	0
T49	646	0	0	0
T69	503	0	0	0
T81	1088	0	0	0
T82	991	0	0	0
T86	0	18	0	0
T94	0	1	0	0
T142	0	11	0	0
T239	0	23	0	0
T252	0	25	0	0
T256	762	0	0	0
T257	580	0	0	0
T261	0	11	0	0
T262	0	16	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	4639359	0	0
T1	2226	623	0	0
T2	534	133	0	0
T3	4462	972	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	4641518	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	1539	0	0
T6	20803	26	0	0
T7	21857	0	0	0
T8	2288	0	0	0
T11	0	31	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T29	0	24	0	0
T34	0	11	0	0
T45	0	7	0	0
T46	0	27	0	0
T47	0	24	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T73	0	10	0	0
T74	0	9	0	0
T75	0	8	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	1502	0	0
T6	20803	26	0	0
T7	21857	0	0	0
T8	2288	0	0	0
T11	0	31	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T29	0	24	0	0
T34	0	11	0	0
T45	0	7	0	0
T46	0	27	0	0
T47	0	24	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T73	0	10	0	0
T74	0	9	0	0
T75	0	8	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	792	0	0
T10	29861	0	0	0
T11	12359	31	0	0
T29	7627	24	0	0
T45	32312	7	0	0
T49	646	0	0	0
T69	503	0	0	0
T81	1088	0	0	0
T82	991	0	0	0
T86	0	18	0	0
T94	0	1	0	0
T142	0	11	0	0
T239	0	23	0	0
T252	0	25	0	0
T256	762	0	0	0
T257	580	0	0	0
T261	0	11	0	0
T262	0	16	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	792	0	0
T10	29861	0	0	0
T11	12359	31	0	0
T29	7627	24	0	0
T45	32312	7	0	0
T49	646	0	0	0
T69	503	0	0	0
T81	1088	0	0	0
T82	991	0	0	0
T86	0	18	0	0
T94	0	1	0	0
T142	0	11	0	0
T239	0	23	0	0
T252	0	25	0	0
T256	762	0	0	0
T257	580	0	0	0
T261	0	11	0	0
T262	0	16	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	74025	0	0
T10	29861	0	0	0
T11	12359	2527	0	0
T29	7627	318	0	0
T45	32312	1184	0	0
T49	646	0	0	0
T69	503	0	0	0
T81	1088	0	0	0
T82	991	0	0	0
T86	0	604	0	0
T94	0	136	0	0
T142	0	1615	0	0
T239	0	1366	0	0
T252	0	2368	0	0
T256	762	0	0	0
T257	580	0	0	0
T261	0	2495	0	0
T262	0	630	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5163025	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5163025	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	659	0	0
T10	29861	0	0	0
T11	12359	29	0	0
T29	7627	24	0	0
T45	32312	2	0	0
T49	646	0	0	0
T69	503	0	0	0
T81	1088	0	0	0
T82	991	0	0	0
T86	0	8	0	0
T94	0	1	0	0
T142	0	11	0	0
T239	0	23	0	0
T252	0	21	0	0
T256	762	0	0	0
T257	580	0	0	0
T261	0	4	0	0
T262	0	16	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T6,T7
1	Covered	T1,T5,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T4,T7,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T2	VC_COV_UNR
1	Covered	T4,T7,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T4,T7,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T9
1	0	Covered	T1,T3,T32
1	1	Covered	T4,T7,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T9
0	1	Covered	T7,T35,T101
1	0	Covered	T83,T58

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T9,T10
0	1	Covered	T4,T9,T10
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T9,T10
1	-	Covered	T4,T9,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T7,T9
DetectSt	168	Covered	T4,T7,T9
IdleSt	163	Covered	T1,T5,T2
StableSt	191	Covered	T4,T9,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T7,T9
DebounceSt->IdleSt	163	Covered	T4,T35,T263
DetectSt->IdleSt	186	Covered	T7,T35,T101
DetectSt->StableSt	191	Covered	T4,T9,T10
IdleSt->DebounceSt	148	Covered	T4,T7,T9
StableSt->IdleSt	206	Covered	T4,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T7,T9
0	1	Covered	T4,T7,T9
0	0	Excluded	T1,T5,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T9
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T7,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T83,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T7,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T35,T263
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T7,T9
DetectSt	-	-	-	-	1	-	-	Covered	T7,T35,T101
DetectSt	-	-	-	-	0	1	-	Covered	T4,T9,T10
DetectSt	-	-	-	-	0	0	-	Covered	T4,T7,T9
StableSt	-	-	-	-	-	-	1	Covered	T4,T9,T10
StableSt	-	-	-	-	-	-	0	Covered	T4,T9,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5823894	876	0	0
CntIncr_A	5823894	48647	0	0
CntNoWrap_A	5823894	5159795	0	0
DetectStDropOut_A	5823894	54	0	0
DetectedOut_A	5823894	15322	0	0
DetectedPulseOut_A	5823894	348	0	0
DisabledIdleSt_A	5823894	4807516	0	0
DisabledNoDetection_A	5823894	4809228	0	0
EnterDebounceSt_A	5823894	470	0	0
EnterDetectSt_A	5823894	406	0	0
EnterStableSt_A	5823894	348	0	0
PulseIsPulse_A	5823894	348	0	0
StayInStableSt	5823894	14941	0	0
gen_high_level_sva.HighLevelEvent_A	5823894	5163025	0	0
gen_not_sticky_sva.StableStDropOut_A	5823894	313	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	876	0	0
T4	28273	21	0	0
T6	20803	0	0	0
T7	21857	2	0	0
T9	0	10	0	0
T10	0	4	0	0
T11	0	4	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T35	0	21	0	0
T45	0	10	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T96	0	10	0	0
T113	0	2	0	0
T126	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	48647	0	0
T4	28273	1971	0	0
T6	20803	0	0	0
T7	21857	116	0	0
T9	0	550	0	0
T10	0	294	0	0
T11	0	120	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T35	0	541	0	0
T45	0	210	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T96	0	495	0	0
T113	0	142	0	0
T126	0	252	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5159795	0	0
T1	2226	623	0	0
T2	534	133	0	0
T3	4462	972	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	54	0	0
T7	21857	1	0	0
T8	2288	0	0	0
T9	20544	0	0	0
T10	29861	0	0	0
T24	498	0	0	0
T29	7627	0	0	0
T35	0	9	0	0
T48	724	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T60	630	0	0	0
T101	0	1	0	0
T107	0	5	0	0
T120	0	1	0	0
T191	0	11	0	0
T207	0	2	0	0
T264	0	9	0	0
T265	0	4	0	0
T266	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	15322	0	0
T4	28273	142	0	0
T6	20803	0	0	0
T7	21857	0	0	0
T9	0	134	0	0
T10	0	72	0	0
T11	0	179	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T45	0	361	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T65	0	17	0	0
T96	0	167	0	0
T113	0	51	0	0
T126	0	106	0	0
T267	0	131	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	348	0	0
T4	28273	10	0	0
T6	20803	0	0	0
T7	21857	0	0	0
T9	0	5	0	0
T10	0	2	0	0
T11	0	2	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T45	0	5	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T65	0	2	0	0
T96	0	5	0	0
T113	0	1	0	0
T126	0	2	0	0
T267	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	4807516	0	0
T1	2226	623	0	0
T2	534	133	0	0
T3	4462	972	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	4809228	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	470	0	0
T4	28273	11	0	0
T6	20803	0	0	0
T7	21857	1	0	0
T9	0	5	0	0
T10	0	2	0	0
T11	0	2	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T35	0	12	0	0
T45	0	5	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T96	0	5	0	0
T113	0	1	0	0
T126	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	406	0	0
T4	28273	10	0	0
T6	20803	0	0	0
T7	21857	1	0	0
T9	0	5	0	0
T10	0	2	0	0
T11	0	2	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T35	0	9	0	0
T45	0	5	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T96	0	5	0	0
T113	0	1	0	0
T126	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	348	0	0
T4	28273	10	0	0
T6	20803	0	0	0
T7	21857	0	0	0
T9	0	5	0	0
T10	0	2	0	0
T11	0	2	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T45	0	5	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T65	0	2	0	0
T96	0	5	0	0
T113	0	1	0	0
T126	0	2	0	0
T267	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	348	0	0
T4	28273	10	0	0
T6	20803	0	0	0
T7	21857	0	0	0
T9	0	5	0	0
T10	0	2	0	0
T11	0	2	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T45	0	5	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T65	0	2	0	0
T96	0	5	0	0
T113	0	1	0	0
T126	0	2	0	0
T267	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	14941	0	0
T4	28273	132	0	0
T6	20803	0	0	0
T7	21857	0	0	0
T9	0	129	0	0
T10	0	70	0	0
T11	0	177	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T45	0	351	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T65	0	15	0	0
T96	0	162	0	0
T113	0	50	0	0
T126	0	104	0	0
T267	0	128	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5163025	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	313	0	0
T4	28273	10	0	0
T6	20803	0	0	0
T7	21857	0	0	0
T9	0	5	0	0
T10	0	2	0	0
T11	0	2	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T65	0	2	0	0
T96	0	5	0	0
T113	0	1	0	0
T126	0	2	0	0
T263	0	9	0	0
T267	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T29,T11
1	Covered	T1,T5,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T6,T29,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T6,T29,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T6,T29,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T29,T11
1	0	Covered	T6,T29,T11
1	1	Covered	T6,T29,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T29,T11
0	1	Covered	T6,T29,T45
1	0	Covered	T6,T29,T45

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T34,T46
0	1	Covered	T11,T34,T46
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T34,T46
1	-	Covered	T11,T34,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T29,T11
DetectSt	168	Covered	T6,T29,T11
IdleSt	163	Covered	T1,T5,T2
StableSt	191	Covered	T11,T34,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T29,T11
DebounceSt->IdleSt	163	Covered	T94,T83,T231
DetectSt->IdleSt	186	Covered	T6,T29,T45
DetectSt->StableSt	191	Covered	T11,T34,T46
IdleSt->DebounceSt	148	Covered	T6,T29,T11
StableSt->IdleSt	206	Covered	T11,T34,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T29,T11
0	1	Covered	T6,T29,T11
0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T29,T11
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T6,T29,T11
IdleSt	0	-	-	-	-	-	-	Covered	T6,T29,T11
DebounceSt	-	1	-	-	-	-	-	Covered	T83,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T29,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T94,T83,T231
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T29,T11
DetectSt	-	-	-	-	1	-	-	Covered	T6,T29,T45
DetectSt	-	-	-	-	0	1	-	Covered	T11,T34,T46
DetectSt	-	-	-	-	0	0	-	Covered	T6,T29,T11
StableSt	-	-	-	-	-	-	1	Covered	T11,T34,T46
StableSt	-	-	-	-	-	-	0	Covered	T11,T34,T46
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5823894	3243	0	0
CntIncr_A	5823894	124474	0	0
CntNoWrap_A	5823894	5157428	0	0
DetectStDropOut_A	5823894	497	0	0
DetectedOut_A	5823894	80528	0	0
DetectedPulseOut_A	5823894	922	0	0
DisabledIdleSt_A	5823894	4635001	0	0
DisabledNoDetection_A	5823894	4637167	0	0
EnterDebounceSt_A	5823894	1638	0	0
EnterDetectSt_A	5823894	1605	0	0
EnterStableSt_A	5823894	922	0	0
PulseIsPulse_A	5823894	922	0	0
StayInStableSt	5823894	79512	0	0
gen_high_event_sva.HighLevelEvent_A	5823894	5163025	0	0
gen_high_level_sva.HighLevelEvent_A	5823894	5163025	0	0
gen_not_sticky_sva.StableStDropOut_A	5823894	828	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	3243	0	0
T6	20803	52	0	0
T7	21857	0	0	0
T8	2288	0	0	0
T11	0	28	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T29	0	44	0	0
T34	0	26	0	0
T45	0	34	0	0
T46	0	50	0	0
T47	0	36	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T73	0	14	0	0
T74	0	28	0	0
T75	0	16	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	124474	0	0
T6	20803	2021	0	0
T7	21857	0	0	0
T8	2288	0	0	0
T11	0	840	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T29	0	1620	0	0
T34	0	767	0	0
T45	0	932	0	0
T46	0	4275	0	0
T47	0	5208	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T73	0	417	0	0
T74	0	665	0	0
T75	0	528	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5157428	0	0
T1	2226	623	0	0
T2	534	133	0	0
T3	4462	972	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	497	0	0
T6	20803	11	0	0
T7	21857	0	0	0
T8	2288	0	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T29	0	8	0	0
T45	0	7	0	0
T47	0	11	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T74	0	14	0	0
T97	0	24	0	0
T98	0	27	0	0
T103	0	29	0	0
T142	0	8	0	0
T239	0	15	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	80528	0	0
T11	12359	559	0	0
T21	2140	0	0	0
T22	2297	0	0	0
T34	0	2067	0	0
T45	32312	0	0	0
T46	0	3743	0	0
T49	646	0	0	0
T69	503	0	0	0
T75	0	37	0	0
T82	991	0	0	0
T84	0	1350	0	0
T86	0	1318	0	0
T94	0	1410	0	0
T102	0	221	0	0
T252	0	1787	0	0
T256	762	0	0	0
T257	580	0	0	0
T258	842	0	0	0
T262	0	601	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	922	0	0
T11	12359	14	0	0
T21	2140	0	0	0
T22	2297	0	0	0
T34	0	13	0	0
T45	32312	0	0	0
T46	0	25	0	0
T49	646	0	0	0
T69	503	0	0	0
T75	0	8	0	0
T82	991	0	0	0
T84	0	6	0	0
T86	0	12	0	0
T94	0	10	0	0
T102	0	7	0	0
T252	0	35	0	0
T256	762	0	0	0
T257	580	0	0	0
T258	842	0	0	0
T262	0	30	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	4635001	0	0
T1	2226	623	0	0
T2	534	133	0	0
T3	4462	972	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	4637167	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	1638	0	0
T6	20803	26	0	0
T7	21857	0	0	0
T8	2288	0	0	0
T11	0	14	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T29	0	22	0	0
T34	0	13	0	0
T45	0	17	0	0
T46	0	25	0	0
T47	0	18	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T73	0	7	0	0
T74	0	14	0	0
T75	0	8	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	1605	0	0
T6	20803	26	0	0
T7	21857	0	0	0
T8	2288	0	0	0
T11	0	14	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T29	0	22	0	0
T34	0	13	0	0
T45	0	17	0	0
T46	0	25	0	0
T47	0	18	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T73	0	7	0	0
T74	0	14	0	0
T75	0	8	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	922	0	0
T11	12359	14	0	0
T21	2140	0	0	0
T22	2297	0	0	0
T34	0	13	0	0
T45	32312	0	0	0
T46	0	25	0	0
T49	646	0	0	0
T69	503	0	0	0
T75	0	8	0	0
T82	991	0	0	0
T84	0	6	0	0
T86	0	12	0	0
T94	0	10	0	0
T102	0	7	0	0
T252	0	35	0	0
T256	762	0	0	0
T257	580	0	0	0
T258	842	0	0	0
T262	0	30	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	922	0	0
T11	12359	14	0	0
T21	2140	0	0	0
T22	2297	0	0	0
T34	0	13	0	0
T45	32312	0	0	0
T46	0	25	0	0
T49	646	0	0	0
T69	503	0	0	0
T75	0	8	0	0
T82	991	0	0	0
T84	0	6	0	0
T86	0	12	0	0
T94	0	10	0	0
T102	0	7	0	0
T252	0	35	0	0
T256	762	0	0	0
T257	580	0	0	0
T258	842	0	0	0
T262	0	30	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	79512	0	0
T11	12359	544	0	0
T21	2140	0	0	0
T22	2297	0	0	0
T34	0	2049	0	0
T45	32312	0	0	0
T46	0	3717	0	0
T49	646	0	0	0
T69	503	0	0	0
T75	0	29	0	0
T82	991	0	0	0
T84	0	1344	0	0
T86	0	1304	0	0
T94	0	1400	0	0
T102	0	214	0	0
T252	0	1748	0	0
T256	762	0	0	0
T257	580	0	0	0
T258	842	0	0	0
T262	0	571	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5163025	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5163025	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	828	0	0
T11	12359	13	0	0
T21	2140	0	0	0
T22	2297	0	0	0
T34	0	8	0	0
T45	32312	0	0	0
T46	0	24	0	0
T49	646	0	0	0
T69	503	0	0	0
T75	0	8	0	0
T82	991	0	0	0
T84	0	6	0	0
T86	0	10	0	0
T94	0	10	0	0
T102	0	7	0	0
T252	0	31	0	0
T256	762	0	0	0
T257	580	0	0	0
T258	842	0	0	0
T262	0	30	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T6,T7
1	Covered	T1,T5,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T4,T7,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T2	VC_COV_UNR
1	Covered	T4,T7,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T4,T7,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T9
1	0	Covered	T1,T3,T32
1	1	Covered	T4,T7,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T9
0	1	Covered	T9,T100,T221
1	0	Covered	T83,T58

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T10
0	1	Covered	T4,T7,T10
1	0	Covered	T84,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T7,T10
1	-	Covered	T4,T7,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T7,T9
DetectSt	168	Covered	T4,T7,T9
IdleSt	163	Covered	T1,T5,T2
StableSt	191	Covered	T4,T7,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T7,T9
DebounceSt->IdleSt	163	Covered	T4,T126,T35
DetectSt->IdleSt	186	Covered	T9,T100,T221
DetectSt->StableSt	191	Covered	T4,T7,T10
IdleSt->DebounceSt	148	Covered	T4,T7,T9
StableSt->IdleSt	206	Covered	T4,T7,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T7,T9
0	1	Covered	T4,T7,T9
0	0	Excluded	T1,T5,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T9
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T7,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T83,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T7,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T126,T35
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T7,T9
DetectSt	-	-	-	-	1	-	-	Covered	T9,T100,T221
DetectSt	-	-	-	-	0	1	-	Covered	T4,T7,T10
DetectSt	-	-	-	-	0	0	-	Covered	T4,T7,T9
StableSt	-	-	-	-	-	-	1	Covered	T4,T7,T10
StableSt	-	-	-	-	-	-	0	Covered	T4,T7,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5823894	821	0	0
CntIncr_A	5823894	45024	0	0
CntNoWrap_A	5823894	5159850	0	0
DetectStDropOut_A	5823894	56	0	0
DetectedOut_A	5823894	13877	0	0
DetectedPulseOut_A	5823894	327	0	0
DisabledIdleSt_A	5823894	4789657	0	0
DisabledNoDetection_A	5823894	4791359	0	0
EnterDebounceSt_A	5823894	435	0	0
EnterDetectSt_A	5823894	386	0	0
EnterStableSt_A	5823894	327	0	0
PulseIsPulse_A	5823894	327	0	0
StayInStableSt	5823894	13516	0	0
gen_high_level_sva.HighLevelEvent_A	5823894	5163025	0	0
gen_not_sticky_sva.StableStDropOut_A	5823894	289	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	821	0	0
T4	28273	11	0	0
T6	20803	0	0	0
T7	21857	6	0	0
T9	0	14	0	0
T10	0	18	0	0
T11	0	2	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T33	0	2	0	0
T34	0	10	0	0
T35	0	29	0	0
T46	0	2	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T126	0	25	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	45024	0	0
T4	28273	671	0	0
T6	20803	0	0	0
T7	21857	198	0	0
T9	0	957	0	0
T10	0	1512	0	0
T11	0	66	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T33	0	138	0	0
T34	0	370	0	0
T35	0	636	0	0
T46	0	206	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T126	0	2186	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5159850	0	0
T1	2226	623	0	0
T2	534	133	0	0
T3	4462	972	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	56	0	0
T9	20544	7	0	0
T10	29861	0	0	0
T11	12359	0	0	0
T29	7627	0	0	0
T45	32312	0	0	0
T69	503	0	0	0
T81	1088	0	0	0
T82	991	0	0	0
T93	0	1	0	0
T100	0	2	0	0
T108	0	2	0	0
T191	0	11	0	0
T192	0	5	0	0
T221	0	1	0	0
T242	0	2	0	0
T256	762	0	0	0
T257	580	0	0	0
T268	0	6	0	0
T269	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	13877	0	0
T4	28273	427	0	0
T6	20803	0	0	0
T7	21857	151	0	0
T10	0	142	0	0
T11	0	83	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T33	0	54	0	0
T34	0	281	0	0
T35	0	110	0	0
T46	0	54	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T113	0	217	0	0
T126	0	91	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	327	0	0
T4	28273	5	0	0
T6	20803	0	0	0
T7	21857	3	0	0
T10	0	9	0	0
T11	0	1	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T33	0	1	0	0
T34	0	5	0	0
T35	0	14	0	0
T46	0	1	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T113	0	3	0	0
T126	0	11	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	4789657	0	0
T1	2226	623	0	0
T2	534	133	0	0
T3	4462	972	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	4791359	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	435	0	0
T4	28273	6	0	0
T6	20803	0	0	0
T7	21857	3	0	0
T9	0	7	0	0
T10	0	9	0	0
T11	0	1	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T33	0	1	0	0
T34	0	5	0	0
T35	0	15	0	0
T46	0	1	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T126	0	14	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	386	0	0
T4	28273	5	0	0
T6	20803	0	0	0
T7	21857	3	0	0
T9	0	7	0	0
T10	0	9	0	0
T11	0	1	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T33	0	1	0	0
T34	0	5	0	0
T35	0	14	0	0
T46	0	1	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T126	0	11	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	327	0	0
T4	28273	5	0	0
T6	20803	0	0	0
T7	21857	3	0	0
T10	0	9	0	0
T11	0	1	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T33	0	1	0	0
T34	0	5	0	0
T35	0	14	0	0
T46	0	1	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T113	0	3	0	0
T126	0	11	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	327	0	0
T4	28273	5	0	0
T6	20803	0	0	0
T7	21857	3	0	0
T10	0	9	0	0
T11	0	1	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T33	0	1	0	0
T34	0	5	0	0
T35	0	14	0	0
T46	0	1	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T113	0	3	0	0
T126	0	11	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	13516	0	0
T4	28273	422	0	0
T6	20803	0	0	0
T7	21857	148	0	0
T10	0	133	0	0
T11	0	82	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T33	0	53	0	0
T34	0	276	0	0
T35	0	96	0	0
T46	0	52	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T113	0	214	0	0
T126	0	80	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5163025	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	289	0	0
T4	28273	5	0	0
T6	20803	0	0	0
T7	21857	3	0	0
T10	0	9	0	0
T11	0	1	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T33	0	1	0	0
T34	0	5	0	0
T35	0	14	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T96	0	2	0	0
T113	0	3	0	0
T126	0	11	0	0