Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T29,T11
1	Covered	T1,T5,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T6,T29,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T6,T29,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T6,T29,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T29,T11
1	0	Covered	T6,T29,T11
1	1	Covered	T6,T29,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T29,T11
0	1	Covered	T6,T34,T74
1	0	Covered	T11,T45,T34

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T29,T47
0	1	Covered	T6,T29,T47
1	0	Covered	T6,T47,T270

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T29,T47
1	-	Covered	T6,T29,T47

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T29,T11
DetectSt	168	Covered	T6,T29,T11
IdleSt	163	Covered	T1,T5,T2
StableSt	191	Covered	T6,T29,T47

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T29,T11
DebounceSt->IdleSt	163	Covered	T94,T83,T231
DetectSt->IdleSt	186	Covered	T6,T11,T45
DetectSt->StableSt	191	Covered	T6,T29,T47
IdleSt->DebounceSt	148	Covered	T6,T29,T11
StableSt->IdleSt	206	Covered	T6,T29,T47

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T29,T11
0	1	Covered	T6,T29,T11
0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T29,T11
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T6,T29,T11
IdleSt	0	-	-	-	-	-	-	Covered	T6,T29,T11
DebounceSt	-	1	-	-	-	-	-	Covered	T83,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T29,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T94,T83,T231
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T29,T11
DetectSt	-	-	-	-	1	-	-	Covered	T6,T11,T45
DetectSt	-	-	-	-	0	1	-	Covered	T6,T29,T47
DetectSt	-	-	-	-	0	0	-	Covered	T6,T29,T11
StableSt	-	-	-	-	-	-	1	Covered	T6,T29,T47
StableSt	-	-	-	-	-	-	0	Covered	T6,T29,T47
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5823894	3060	0	0
CntIncr_A	5823894	117869	0	0
CntNoWrap_A	5823894	5157611	0	0
DetectStDropOut_A	5823894	405	0	0
DetectedOut_A	5823894	84305	0	0
DetectedPulseOut_A	5823894	995	0	0
DisabledIdleSt_A	5823894	4634382	0	0
DisabledNoDetection_A	5823894	4636561	0	0
EnterDebounceSt_A	5823894	1542	0	0
EnterDetectSt_A	5823894	1519	0	0
EnterStableSt_A	5823894	995	0	0
PulseIsPulse_A	5823894	995	0	0
StayInStableSt	5823894	83229	0	0
gen_high_event_sva.HighLevelEvent_A	5823894	5163025	0	0
gen_high_level_sva.HighLevelEvent_A	5823894	5163025	0	0
gen_not_sticky_sva.StableStDropOut_A	5823894	902	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	3060	0	0
T6	20803	22	0	0
T7	21857	0	0	0
T8	2288	0	0	0
T11	0	28	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T29	0	48	0	0
T34	0	54	0	0
T45	0	8	0	0
T46	0	42	0	0
T47	0	48	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T73	0	50	0	0
T74	0	24	0	0
T75	0	54	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	117869	0	0
T6	20803	836	0	0
T7	21857	0	0	0
T8	2288	0	0	0
T11	0	1064	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T29	0	1104	0	0
T34	0	1625	0	0
T45	0	220	0	0
T46	0	3696	0	0
T47	0	6696	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T73	0	975	0	0
T74	0	574	0	0
T75	0	1485	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5157611	0	0
T1	2226	623	0	0
T2	534	133	0	0
T3	4462	972	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	405	0	0
T6	20803	3	0	0
T7	21857	0	0	0
T8	2288	0	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T34	0	19	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T74	0	12	0	0
T84	0	5	0	0
T97	0	24	0	0
T98	0	30	0	0
T103	0	15	0	0
T239	0	10	0	0
T271	0	22	0	0
T272	0	7	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	84305	0	0
T6	20803	13	0	0
T7	21857	0	0	0
T8	2288	0	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T29	0	1825	0	0
T46	0	5029	0	0
T47	0	245	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T73	0	811	0	0
T75	0	1583	0	0
T86	0	3557	0	0
T94	0	1984	0	0
T102	0	1396	0	0
T142	0	762	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	995	0	0
T6	20803	8	0	0
T7	21857	0	0	0
T8	2288	0	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T29	0	24	0	0
T46	0	21	0	0
T47	0	24	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T73	0	25	0	0
T75	0	27	0	0
T86	0	30	0	0
T94	0	12	0	0
T102	0	21	0	0
T142	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	4634382	0	0
T1	2226	623	0	0
T2	534	133	0	0
T3	4462	972	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	4636561	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	1542	0	0
T6	20803	11	0	0
T7	21857	0	0	0
T8	2288	0	0	0
T11	0	14	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T29	0	24	0	0
T34	0	27	0	0
T45	0	4	0	0
T46	0	21	0	0
T47	0	24	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T73	0	25	0	0
T74	0	12	0	0
T75	0	27	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	1519	0	0
T6	20803	11	0	0
T7	21857	0	0	0
T8	2288	0	0	0
T11	0	14	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T29	0	24	0	0
T34	0	27	0	0
T45	0	4	0	0
T46	0	21	0	0
T47	0	24	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T73	0	25	0	0
T74	0	12	0	0
T75	0	27	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	995	0	0
T6	20803	8	0	0
T7	21857	0	0	0
T8	2288	0	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T29	0	24	0	0
T46	0	21	0	0
T47	0	24	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T73	0	25	0	0
T75	0	27	0	0
T86	0	30	0	0
T94	0	12	0	0
T102	0	21	0	0
T142	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	995	0	0
T6	20803	8	0	0
T7	21857	0	0	0
T8	2288	0	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T29	0	24	0	0
T46	0	21	0	0
T47	0	24	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T73	0	25	0	0
T75	0	27	0	0
T86	0	30	0	0
T94	0	12	0	0
T102	0	21	0	0
T142	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	83229	0	0
T6	20803	5	0	0
T7	21857	0	0	0
T8	2288	0	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T29	0	1801	0	0
T46	0	5008	0	0
T47	0	221	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T73	0	786	0	0
T75	0	1556	0	0
T86	0	3518	0	0
T94	0	1972	0	0
T102	0	1375	0	0
T142	0	752	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5163025	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5163025	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	902	0	0
T6	20803	3	0	0
T7	21857	0	0	0
T8	2288	0	0	0
T24	498	0	0	0
T25	3703	0	0	0
T26	523	0	0	0
T29	0	24	0	0
T46	0	21	0	0
T47	0	23	0	0
T48	724	0	0	0
T55	442	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T73	0	25	0	0
T75	0	27	0	0
T86	0	21	0	0
T94	0	12	0	0
T102	0	20	0	0
T142	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T6,T7
1	Covered	T1,T5,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T7,T9,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T2	VC_COV_UNR
1	Covered	T7,T9,T33

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T2
1	Covered	T7,T9,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T3,T32
1	1	Covered	T7,T9,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T33
0	1	Covered	T33,T35,T39
1	0	Covered	T83,T58

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T126
0	1	Covered	T7,T9,T126
1	0	Covered	T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T9,T126
1	-	Covered	T7,T9,T126

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T9,T33
DetectSt	168	Covered	T7,T9,T33
IdleSt	163	Covered	T1,T5,T2
StableSt	191	Covered	T7,T9,T126

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T9,T33
DebounceSt->IdleSt	163	Covered	T7,T35,T263
DetectSt->IdleSt	186	Covered	T33,T35,T39
DetectSt->StableSt	191	Covered	T7,T9,T126
IdleSt->DebounceSt	148	Covered	T7,T9,T33
StableSt->IdleSt	206	Covered	T7,T9,T126

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T9,T33
0	1	Covered	T7,T9,T33
0	0	Excluded	T1,T5,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T33
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T9,T33
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T83,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T9,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T35,T263
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T9,T33
DetectSt	-	-	-	-	1	-	-	Covered	T33,T35,T39
DetectSt	-	-	-	-	0	1	-	Covered	T7,T9,T126
DetectSt	-	-	-	-	0	0	-	Covered	T7,T9,T33
StableSt	-	-	-	-	-	-	1	Covered	T7,T9,T126
StableSt	-	-	-	-	-	-	0	Covered	T7,T9,T126
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5823894	791	0	0
CntIncr_A	5823894	42955	0	0
CntNoWrap_A	5823894	5159880	0	0
DetectStDropOut_A	5823894	58	0	0
DetectedOut_A	5823894	16198	0	0
DetectedPulseOut_A	5823894	313	0	0
DisabledIdleSt_A	5823894	4789215	0	0
DisabledNoDetection_A	5823894	4790931	0	0
EnterDebounceSt_A	5823894	417	0	0
EnterDetectSt_A	5823894	374	0	0
EnterStableSt_A	5823894	313	0	0
PulseIsPulse_A	5823894	313	0	0
StayInStableSt	5823894	15857	0	0
gen_high_level_sva.HighLevelEvent_A	5823894	5163025	0	0
gen_not_sticky_sva.StableStDropOut_A	5823894	283	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	791	0	0
T7	21857	11	0	0
T8	2288	0	0	0
T9	20544	14	0	0
T10	29861	0	0	0
T24	498	0	0	0
T29	7627	0	0	0
T33	0	2	0	0
T35	0	26	0	0
T48	724	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T60	630	0	0	0
T65	0	2	0	0
T96	0	16	0	0
T113	0	18	0	0
T126	0	26	0	0
T263	0	9	0	0
T267	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	42955	0	0
T7	21857	530	0	0
T8	2288	0	0	0
T9	20544	924	0	0
T10	29861	0	0	0
T24	498	0	0	0
T29	7627	0	0	0
T33	0	193	0	0
T35	0	796	0	0
T48	724	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T60	630	0	0	0
T65	0	146	0	0
T96	0	800	0	0
T113	0	1107	0	0
T126	0	1716	0	0
T263	0	460	0	0
T267	0	106	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5159880	0	0
T1	2226	623	0	0
T2	534	133	0	0
T3	4462	972	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	58	0	0
T27	773	0	0	0
T33	17456	1	0	0
T34	17799	0	0	0
T35	0	7	0	0
T36	258522	0	0	0
T39	0	2	0	0
T46	22587	0	0	0
T47	32569	0	0	0
T50	687	0	0	0
T70	548	0	0	0
T83	0	1	0	0
T106	0	1	0	0
T127	406	0	0	0
T186	446	0	0	0
T192	0	3	0	0
T220	0	12	0	0
T269	0	2	0	0
T273	0	1	0	0
T274	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	16198	0	0
T7	21857	94	0	0
T8	2288	0	0	0
T9	20544	33	0	0
T10	29861	0	0	0
T24	498	0	0	0
T29	7627	0	0	0
T35	0	17	0	0
T48	724	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T60	630	0	0	0
T65	0	26	0	0
T96	0	266	0	0
T113	0	633	0	0
T126	0	628	0	0
T263	0	345	0	0
T267	0	65	0	0
T275	0	170	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	313	0	0
T7	21857	5	0	0
T8	2288	0	0	0
T9	20544	7	0	0
T10	29861	0	0	0
T24	498	0	0	0
T29	7627	0	0	0
T35	0	4	0	0
T48	724	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T60	630	0	0	0
T65	0	1	0	0
T96	0	8	0	0
T113	0	9	0	0
T126	0	13	0	0
T263	0	4	0	0
T267	0	1	0	0
T275	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	4789215	0	0
T1	2226	623	0	0
T2	534	133	0	0
T3	4462	972	0	0
T5	402	1	0	0
T12	402	1	0	0
T13	683	282	0	0
T14	1128	727	0	0
T15	423	22	0	0
T16	984	583	0	0
T17	422	21	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	4790931	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	417	0	0
T7	21857	6	0	0
T8	2288	0	0	0
T9	20544	7	0	0
T10	29861	0	0	0
T24	498	0	0	0
T29	7627	0	0	0
T33	0	1	0	0
T35	0	15	0	0
T48	724	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T60	630	0	0	0
T65	0	1	0	0
T96	0	8	0	0
T113	0	9	0	0
T126	0	13	0	0
T263	0	5	0	0
T267	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	374	0	0
T7	21857	5	0	0
T8	2288	0	0	0
T9	20544	7	0	0
T10	29861	0	0	0
T24	498	0	0	0
T29	7627	0	0	0
T33	0	1	0	0
T35	0	11	0	0
T48	724	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T60	630	0	0	0
T65	0	1	0	0
T96	0	8	0	0
T113	0	9	0	0
T126	0	13	0	0
T263	0	4	0	0
T267	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	313	0	0
T7	21857	5	0	0
T8	2288	0	0	0
T9	20544	7	0	0
T10	29861	0	0	0
T24	498	0	0	0
T29	7627	0	0	0
T35	0	4	0	0
T48	724	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T60	630	0	0	0
T65	0	1	0	0
T96	0	8	0	0
T113	0	9	0	0
T126	0	13	0	0
T263	0	4	0	0
T267	0	1	0	0
T275	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	313	0	0
T7	21857	5	0	0
T8	2288	0	0	0
T9	20544	7	0	0
T10	29861	0	0	0
T24	498	0	0	0
T29	7627	0	0	0
T35	0	4	0	0
T48	724	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T60	630	0	0	0
T65	0	1	0	0
T96	0	8	0	0
T113	0	9	0	0
T126	0	13	0	0
T263	0	4	0	0
T267	0	1	0	0
T275	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	15857	0	0
T7	21857	89	0	0
T8	2288	0	0	0
T9	20544	26	0	0
T10	29861	0	0	0
T24	498	0	0	0
T29	7627	0	0	0
T35	0	13	0	0
T48	724	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T60	630	0	0	0
T65	0	25	0	0
T96	0	258	0	0
T113	0	624	0	0
T126	0	615	0	0
T263	0	341	0	0
T267	0	64	0	0
T275	0	167	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	5163025	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5823894	283	0	0
T7	21857	5	0	0
T8	2288	0	0	0
T9	20544	7	0	0
T10	29861	0	0	0
T24	498	0	0	0
T29	7627	0	0	0
T35	0	4	0	0
T48	724	0	0	0
T56	422	0	0	0
T57	522	0	0	0
T60	630	0	0	0
T65	0	1	0	0
T96	0	8	0	0
T113	0	9	0	0
T126	0	13	0	0
T263	0	4	0	0
T267	0	1	0	0
T275	0	3	0	0