Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1166373877	10126	0	0
auto_block_debounce_ctl_rd_A	1166373877	2023	0	0
auto_block_out_ctl_rd_A	1166373877	3328	0	0
com_det_ctl_0_rd_A	1166373877	4060	0	0
com_det_ctl_1_rd_A	1166373877	4261	0	0
com_det_ctl_2_rd_A	1166373877	4182	0	0
com_det_ctl_3_rd_A	1166373877	3991	0	0
com_out_ctl_0_rd_A	1166373877	5125	0	0
com_out_ctl_1_rd_A	1166373877	5077	0	0
com_out_ctl_2_rd_A	1166373877	5073	0	0
com_out_ctl_3_rd_A	1166373877	5304	0	0
com_pre_det_ctl_0_rd_A	1166373877	1563	0	0
com_pre_det_ctl_1_rd_A	1166373877	1533	0	0
com_pre_det_ctl_2_rd_A	1166373877	1618	0	0
com_pre_det_ctl_3_rd_A	1166373877	1620	0	0
com_pre_sel_ctl_0_rd_A	1166373877	5195	0	0
com_pre_sel_ctl_1_rd_A	1166373877	5447	0	0
com_pre_sel_ctl_2_rd_A	1166373877	5403	0	0
com_pre_sel_ctl_3_rd_A	1166373877	5254	0	0
com_sel_ctl_0_rd_A	1166373877	5358	0	0
com_sel_ctl_1_rd_A	1166373877	5318	0	0
com_sel_ctl_2_rd_A	1166373877	5354	0	0
com_sel_ctl_3_rd_A	1166373877	5356	0	0
ec_rst_ctl_rd_A	1166373877	2678	0	0
intr_enable_rd_A	1166373877	2167	0	0
key_intr_ctl_rd_A	1166373877	5267	0	0
key_intr_debounce_ctl_rd_A	1166373877	1633	0	0
key_invert_ctl_rd_A	1166373877	6113	0	0
pin_allowed_ctl_rd_A	1166373877	7874	0	0
pin_out_ctl_rd_A	1166373877	5614	0	0
pin_out_value_rd_A	1166373877	5419	0	0
regwen_rd_A	1166373877	1865	0	0
ulp_ac_debounce_ctl_rd_A	1166373877	1714	0	0
ulp_ctl_rd_A	1166373877	1714	0	0
ulp_lid_debounce_ctl_rd_A	1166373877	1798	0	0
ulp_pwrb_debounce_ctl_rd_A	1166373877	1637	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	10126	0	0
T3	198545	5	0	0
T4	135708	0	0	0
T6	260047	0	0	0
T15	110191	0	0	0
T16	492251	0	0	0
T17	103549	0	0	0
T23	238399	0	0	0
T25	237750	0	0	0
T28	204416	0	0	0
T32	345456	0	0	0
T38	0	8	0	0
T39	0	18	0	0
T61	0	3	0	0
T65	0	11	0	0
T76	0	9	0	0
T77	0	5	0	0
T78	0	2	0	0
T79	0	9	0	0
T101	0	6	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	2023	0	0
T4	135708	0	0	0
T6	260047	0	0	0
T7	513558	0	0	0
T24	59788	0	0	0
T25	237750	7	0	0
T26	128275	0	0	0
T28	204416	8	0	0
T38	0	21	0	0
T48	362346	8	0	0
T49	0	8	0	0
T52	0	14	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T65	0	11	0	0
T78	0	5	0	0
T79	0	38	0	0
T302	0	4	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	3328	0	0
T4	135708	0	0	0
T6	260047	0	0	0
T7	513558	0	0	0
T24	59788	0	0	0
T25	237750	20	0	0
T26	128275	0	0	0
T28	204416	6	0	0
T38	0	7	0	0
T48	362346	2	0	0
T49	0	11	0	0
T52	0	7	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T65	0	16	0	0
T78	0	3	0	0
T79	0	40	0	0
T302	0	12	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	4060	0	0
T11	593192	62	0	0
T21	43532	0	0	0
T22	884615	0	0	0
T33	0	75	0	0
T34	0	47	0	0
T35	0	169	0	0
T38	0	11	0	0
T45	484680	68	0	0
T47	0	49	0	0
T49	48509	0	0	0
T65	0	33	0	0
T69	121047	0	0	0
T73	0	41	0	0
T75	0	33	0	0
T82	118968	0	0	0
T256	95289	0	0	0
T257	223432	0	0	0
T258	408606	0	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	4261	0	0
T11	593192	56	0	0
T21	43532	0	0	0
T22	884615	0	0	0
T33	0	87	0	0
T34	0	27	0	0
T35	0	154	0	0
T38	0	19	0	0
T45	484680	85	0	0
T47	0	59	0	0
T49	48509	0	0	0
T65	0	26	0	0
T69	121047	0	0	0
T73	0	52	0	0
T75	0	25	0	0
T82	118968	0	0	0
T256	95289	0	0	0
T257	223432	0	0	0
T258	408606	0	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	4182	0	0
T11	593192	63	0	0
T21	43532	0	0	0
T22	884615	0	0	0
T33	0	72	0	0
T34	0	35	0	0
T35	0	143	0	0
T38	0	15	0	0
T45	484680	105	0	0
T47	0	46	0	0
T49	48509	0	0	0
T65	0	28	0	0
T69	121047	0	0	0
T73	0	41	0	0
T75	0	44	0	0
T82	118968	0	0	0
T256	95289	0	0	0
T257	223432	0	0	0
T258	408606	0	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	3991	0	0
T11	593192	60	0	0
T21	43532	0	0	0
T22	884615	0	0	0
T33	0	48	0	0
T34	0	14	0	0
T35	0	133	0	0
T38	0	13	0	0
T45	484680	94	0	0
T47	0	48	0	0
T49	48509	0	0	0
T65	0	30	0	0
T69	121047	0	0	0
T73	0	25	0	0
T75	0	37	0	0
T82	118968	0	0	0
T256	95289	0	0	0
T257	223432	0	0	0
T258	408606	0	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	5125	0	0
T11	593192	58	0	0
T21	43532	0	0	0
T22	884615	0	0	0
T33	0	52	0	0
T34	0	29	0	0
T35	0	148	0	0
T38	0	20	0	0
T45	484680	107	0	0
T47	0	38	0	0
T49	48509	0	0	0
T65	0	1	0	0
T69	121047	0	0	0
T73	0	37	0	0
T75	0	40	0	0
T82	118968	0	0	0
T256	95289	0	0	0
T257	223432	0	0	0
T258	408606	0	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	5077	0	0
T11	593192	49	0	0
T21	43532	0	0	0
T22	884615	0	0	0
T33	0	68	0	0
T34	0	15	0	0
T35	0	158	0	0
T38	0	8	0	0
T45	484680	91	0	0
T47	0	39	0	0
T49	48509	0	0	0
T65	0	21	0	0
T69	121047	0	0	0
T73	0	30	0	0
T75	0	38	0	0
T82	118968	0	0	0
T256	95289	0	0	0
T257	223432	0	0	0
T258	408606	0	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	5073	0	0
T11	593192	55	0	0
T21	43532	0	0	0
T22	884615	0	0	0
T33	0	70	0	0
T34	0	49	0	0
T35	0	149	0	0
T38	0	14	0	0
T45	484680	62	0	0
T47	0	43	0	0
T49	48509	0	0	0
T65	0	30	0	0
T69	121047	0	0	0
T73	0	46	0	0
T75	0	47	0	0
T82	118968	0	0	0
T256	95289	0	0	0
T257	223432	0	0	0
T258	408606	0	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	5304	0	0
T11	593192	42	0	0
T21	43532	0	0	0
T22	884615	0	0	0
T33	0	99	0	0
T34	0	19	0	0
T35	0	145	0	0
T38	0	13	0	0
T45	484680	94	0	0
T47	0	63	0	0
T49	48509	0	0	0
T65	0	19	0	0
T69	121047	0	0	0
T73	0	45	0	0
T75	0	26	0	0
T82	118968	0	0	0
T256	95289	0	0	0
T257	223432	0	0	0
T258	408606	0	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1563	0	0
T18	0	48	0	0
T31	0	8	0	0
T38	0	14	0	0
T41	382289	0	0	0
T42	72806	0	0	0
T65	216999	14	0	0
T66	118634	0	0	0
T78	0	2	0	0
T79	0	31	0	0
T97	644521	0	0	0
T130	0	14	0	0
T145	0	24	0	0
T263	613391	0	0	0
T282	0	12	0	0
T303	0	7	0	0
T304	70849	0	0	0
T305	65757	0	0	0
T306	105326	0	0	0
T307	110055	0	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1533	0	0
T18	0	23	0	0
T31	0	7	0	0
T38	0	16	0	0
T41	382289	0	0	0
T42	72806	0	0	0
T65	216999	9	0	0
T66	118634	0	0	0
T78	0	3	0	0
T79	0	31	0	0
T97	644521	0	0	0
T130	0	9	0	0
T145	0	26	0	0
T263	613391	0	0	0
T282	0	7	0	0
T303	0	8	0	0
T304	70849	0	0	0
T305	65757	0	0	0
T306	105326	0	0	0
T307	110055	0	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1618	0	0
T18	0	17	0	0
T31	0	30	0	0
T38	0	10	0	0
T41	382289	0	0	0
T42	72806	0	0	0
T65	216999	31	0	0
T66	118634	0	0	0
T78	0	6	0	0
T79	0	37	0	0
T97	644521	0	0	0
T130	0	1	0	0
T145	0	18	0	0
T263	613391	0	0	0
T280	0	96	0	0
T303	0	13	0	0
T304	70849	0	0	0
T305	65757	0	0	0
T306	105326	0	0	0
T307	110055	0	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1620	0	0
T31	0	11	0	0
T38	0	11	0	0
T41	382289	0	0	0
T42	72806	0	0	0
T65	216999	18	0	0
T66	118634	0	0	0
T78	0	2	0	0
T79	0	24	0	0
T97	644521	0	0	0
T130	0	3	0	0
T145	0	19	0	0
T263	613391	0	0	0
T282	0	11	0	0
T303	0	15	0	0
T304	70849	0	0	0
T305	65757	0	0	0
T306	105326	0	0	0
T307	110055	0	0	0
T308	0	1	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	5195	0	0
T11	593192	46	0	0
T21	43532	0	0	0
T22	884615	0	0	0
T33	0	99	0	0
T34	0	34	0	0
T35	0	141	0	0
T38	0	17	0	0
T45	484680	106	0	0
T47	0	55	0	0
T49	48509	0	0	0
T65	0	26	0	0
T69	121047	0	0	0
T73	0	46	0	0
T75	0	40	0	0
T82	118968	0	0	0
T256	95289	0	0	0
T257	223432	0	0	0
T258	408606	0	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	5447	0	0
T11	593192	42	0	0
T21	43532	0	0	0
T22	884615	0	0	0
T33	0	84	0	0
T34	0	48	0	0
T35	0	122	0	0
T38	0	4	0	0
T45	484680	88	0	0
T47	0	61	0	0
T49	48509	0	0	0
T65	0	22	0	0
T69	121047	0	0	0
T73	0	44	0	0
T75	0	60	0	0
T82	118968	0	0	0
T256	95289	0	0	0
T257	223432	0	0	0
T258	408606	0	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	5403	0	0
T11	593192	57	0	0
T21	43532	0	0	0
T22	884615	0	0	0
T33	0	76	0	0
T34	0	27	0	0
T35	0	132	0	0
T38	0	16	0	0
T45	484680	92	0	0
T47	0	97	0	0
T49	48509	0	0	0
T65	0	26	0	0
T69	121047	0	0	0
T73	0	33	0	0
T75	0	32	0	0
T82	118968	0	0	0
T256	95289	0	0	0
T257	223432	0	0	0
T258	408606	0	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	5254	0	0
T11	593192	50	0	0
T21	43532	0	0	0
T22	884615	0	0	0
T33	0	70	0	0
T34	0	29	0	0
T35	0	117	0	0
T38	0	8	0	0
T45	484680	87	0	0
T47	0	69	0	0
T49	48509	0	0	0
T65	0	22	0	0
T69	121047	0	0	0
T73	0	34	0	0
T75	0	56	0	0
T82	118968	0	0	0
T256	95289	0	0	0
T257	223432	0	0	0
T258	408606	0	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	5358	0	0
T11	593192	74	0	0
T21	43532	0	0	0
T22	884615	0	0	0
T33	0	70	0	0
T34	0	53	0	0
T35	0	176	0	0
T38	0	10	0	0
T45	484680	96	0	0
T47	0	32	0	0
T49	48509	0	0	0
T65	0	25	0	0
T69	121047	0	0	0
T73	0	48	0	0
T75	0	43	0	0
T82	118968	0	0	0
T256	95289	0	0	0
T257	223432	0	0	0
T258	408606	0	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	5318	0	0
T11	593192	66	0	0
T21	43532	0	0	0
T22	884615	0	0	0
T33	0	70	0	0
T34	0	47	0	0
T35	0	136	0	0
T38	0	6	0	0
T45	484680	80	0	0
T47	0	59	0	0
T49	48509	0	0	0
T65	0	27	0	0
T69	121047	0	0	0
T73	0	28	0	0
T75	0	59	0	0
T82	118968	0	0	0
T256	95289	0	0	0
T257	223432	0	0	0
T258	408606	0	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	5354	0	0
T11	593192	65	0	0
T21	43532	0	0	0
T22	884615	0	0	0
T33	0	56	0	0
T34	0	43	0	0
T35	0	123	0	0
T38	0	12	0	0
T45	484680	91	0	0
T47	0	49	0	0
T49	48509	0	0	0
T65	0	18	0	0
T69	121047	0	0	0
T73	0	31	0	0
T75	0	50	0	0
T82	118968	0	0	0
T256	95289	0	0	0
T257	223432	0	0	0
T258	408606	0	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	5356	0	0
T11	593192	55	0	0
T21	43532	0	0	0
T22	884615	0	0	0
T33	0	54	0	0
T34	0	15	0	0
T35	0	118	0	0
T38	0	9	0	0
T45	484680	85	0	0
T47	0	57	0	0
T49	48509	0	0	0
T65	0	29	0	0
T69	121047	0	0	0
T73	0	53	0	0
T75	0	55	0	0
T82	118968	0	0	0
T256	95289	0	0	0
T257	223432	0	0	0
T258	408606	0	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	2678	0	0
T1	513276	1	0	0
T2	110326	0	0	0
T3	198545	0	0	0
T5	201266	0	0	0
T11	0	11	0	0
T12	195243	0	0	0
T13	164028	0	0	0
T14	202183	0	0	0
T15	110191	0	0	0
T16	492251	0	0	0
T17	103549	0	0	0
T25	0	2	0	0
T32	0	7	0	0
T33	0	11	0	0
T45	0	42	0	0
T60	0	8	0	0
T81	0	3	0	0
T256	0	7	0	0
T257	0	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	2167	0	0
T1	513276	11	0	0
T2	110326	0	0	0
T3	198545	0	0	0
T5	201266	0	0	0
T12	195243	0	0	0
T13	164028	0	0	0
T14	202183	0	0	0
T15	110191	0	0	0
T16	492251	0	0	0
T17	103549	0	0	0
T32	0	16	0	0
T38	0	6	0	0
T65	0	58	0	0
T78	0	20	0	0
T79	0	32	0	0
T130	0	39	0	0
T158	0	13	0	0
T309	0	10	0	0
T310	0	17	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	5267	0	0
T1	513276	5	0	0
T2	110326	0	0	0
T3	198545	0	0	0
T5	201266	0	0	0
T12	195243	0	0	0
T13	164028	0	0	0
T14	202183	0	0	0
T15	110191	0	0	0
T16	492251	0	0	0
T17	103549	0	0	0
T35	0	8	0	0
T38	0	18	0	0
T42	0	1	0	0
T43	0	7	0	0
T65	0	21	0	0
T78	0	6	0	0
T79	0	44	0	0
T85	0	10	0	0
T199	0	3	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1633	0	0
T31	0	10	0	0
T38	0	13	0	0
T41	382289	0	0	0
T42	72806	0	0	0
T65	216999	24	0	0
T66	118634	0	0	0
T78	0	9	0	0
T79	0	20	0	0
T97	644521	0	0	0
T130	0	2	0	0
T145	0	14	0	0
T263	613391	0	0	0
T282	0	1	0	0
T303	0	15	0	0
T304	70849	0	0	0
T305	65757	0	0	0
T306	105326	0	0	0
T307	110055	0	0	0
T308	0	8	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	6113	0	0
T4	135708	0	0	0
T6	260047	0	0	0
T7	513558	0	0	0
T22	0	66	0	0
T23	238399	81	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T28	204416	0	0	0
T32	345456	0	0	0
T38	0	9	0	0
T55	221254	0	0	0
T65	0	132	0	0
T78	0	74	0	0
T79	0	21	0	0
T130	0	112	0	0
T172	0	69	0	0
T301	0	77	0	0
T311	0	52	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	7874	0	0
T22	884615	68	0	0
T27	85067	0	0	0
T33	872837	0	0	0
T34	863277	0	0	0
T36	84377	0	0	0
T38	0	11	0	0
T46	553420	0	0	0
T47	911962	0	0	0
T50	330122	0	0	0
T65	0	267	0	0
T70	16442	0	0	0
T78	0	71	0	0
T79	0	87	0	0
T127	199026	0	0	0
T130	0	15	0	0
T178	0	66	0	0
T312	0	65	0	0
T313	0	20	0	0
T314	0	65	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	5614	0	0
T22	884615	52	0	0
T27	85067	0	0	0
T33	872837	0	0	0
T34	863277	0	0	0
T36	84377	0	0	0
T38	0	12	0	0
T46	553420	0	0	0
T47	911962	0	0	0
T50	330122	0	0	0
T65	0	234	0	0
T70	16442	0	0	0
T78	0	63	0	0
T79	0	78	0	0
T127	199026	0	0	0
T130	0	10	0	0
T178	0	69	0	0
T312	0	57	0	0
T313	0	36	0	0
T314	0	79	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	5419	0	0
T22	884615	51	0	0
T27	85067	0	0	0
T33	872837	0	0	0
T34	863277	0	0	0
T36	84377	0	0	0
T38	0	4	0	0
T46	553420	0	0	0
T47	911962	0	0	0
T50	330122	0	0	0
T65	0	204	0	0
T70	16442	0	0	0
T78	0	80	0	0
T79	0	91	0	0
T127	199026	0	0	0
T130	0	10	0	0
T178	0	63	0	0
T312	0	72	0	0
T313	0	27	0	0
T314	0	59	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1865	0	0
T31	0	19	0	0
T38	0	15	0	0
T41	382289	0	0	0
T42	72806	0	0	0
T65	216999	13	0	0
T66	118634	0	0	0
T78	0	3	0	0
T79	0	36	0	0
T97	644521	0	0	0
T130	0	6	0	0
T145	0	13	0	0
T263	613391	0	0	0
T282	0	3	0	0
T303	0	18	0	0
T304	70849	0	0	0
T305	65757	0	0	0
T306	105326	0	0	0
T307	110055	0	0	0
T308	0	6	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1714	0	0
T4	135708	0	0	0
T6	260047	0	0	0
T7	513558	0	0	0
T8	0	11	0	0
T22	0	1	0	0
T24	59788	0	0	0
T25	237750	1	0	0
T26	128275	0	0	0
T28	204416	0	0	0
T32	345456	5	0	0
T38	0	16	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T65	0	19	0	0
T78	0	17	0	0
T79	0	32	0	0
T87	0	5	0	0
T315	0	14	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1714	0	0
T4	135708	0	0	0
T6	260047	0	0	0
T7	513558	0	0	0
T8	0	7	0	0
T22	0	8	0	0
T24	59788	0	0	0
T25	237750	3	0	0
T26	128275	0	0	0
T28	204416	0	0	0
T32	345456	3	0	0
T38	0	16	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T65	0	19	0	0
T78	0	4	0	0
T79	0	27	0	0
T87	0	10	0	0
T315	0	21	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1798	0	0
T3	198545	0	0	0
T4	135708	0	0	0
T6	260047	0	0	0
T8	0	12	0	0
T14	202183	4	0	0
T15	110191	0	0	0
T16	492251	0	0	0
T17	103549	0	0	0
T23	238399	0	0	0
T25	0	2	0	0
T28	204416	0	0	0
T32	345456	4	0	0
T38	0	12	0	0
T65	0	25	0	0
T78	0	3	0	0
T79	0	38	0	0
T87	0	10	0	0
T315	0	15	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1637	0	0
T4	135708	0	0	0
T6	260047	0	0	0
T7	513558	0	0	0
T8	0	8	0	0
T24	59788	0	0	0
T25	237750	8	0	0
T26	128275	0	0	0
T28	204416	0	0	0
T32	345456	1	0	0
T38	0	15	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T65	0	15	0	0
T78	0	6	0	0
T79	0	30	0	0
T87	0	8	0	0
T88	0	7	0	0
T315	0	7	0	0