Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	89.20			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_wkup_status_cdc	96.88	100.00	87.50			100.00	100.00
tb.dut.u_reg.u_ec_rst_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_invert_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_value_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ctl_cdc	98.08	100.00	92.31			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.79	96.99	84.93			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_value_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ec_rst_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_allowed_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_invert_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_value_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T1,T13,T14

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T13,T14
1	1	Covered	T1,T13,T14

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T1,T13,T14

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T13,T14
1	1	Covered	T1,T13,T14

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Unreachable

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
98.08	92.31

tb.dut.u_reg.u_ulp_ctl_cdc

SCORE	COND
96.88	87.50

tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T4,T6,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T8,T21,T22
1	-	Covered	T4,T6,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T1,T13,T14
0	0	1	Covered	T1,T13,T14
0	0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T1,T13,T14
0	0	1	Covered	T1,T13,T14
0	0	0	Covered	T1,T5,T2

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	109927835	0	0
DstReqKnown_A	207710930	178055348	0	0
SrcAckBusyChk_A	2147483647	121196	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	109927835	0	0
T1	513276	0	0	0
T2	110326	0	0	0
T3	1191270	17067	0	0
T4	1899912	148867	0	0
T5	201266	0	0	0
T6	5721034	24794	0	0
T7	8730486	53952	0	0
T8	463376	0	0	0
T9	0	112361	0	0
T10	0	44520	0	0
T11	0	44516	0	0
T15	661146	0	0	0
T16	2953506	0	0	0
T17	621294	0	0	0
T23	1191995	0	0	0
T24	1016396	0	0	0
T25	5230500	2565	0	0
T26	2180675	0	0	0
T28	1022080	2771	0	0
T29	0	17291	0	0
T32	1727280	0	0	0
T33	0	87998	0	0
T34	0	10144	0	0
T45	0	54469	0	0
T47	0	29961	0	0
T48	6159882	11945	0	0
T49	0	2322	0	0
T50	0	10982	0	0
T51	0	11983	0	0
T52	0	9914	0	0
T53	0	6798	0	0
T54	0	1239	0	0
T55	3761318	0	0	0
T56	3523539	0	0	0
T57	4391202	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207710930	178055348	0	0
T1	75684	21284	0	0
T2	18156	4556	0	0
T3	151708	33354	0	0
T5	13668	68	0	0
T12	13668	68	0	0
T13	23222	9622	0	0
T14	38352	24752	0	0
T15	14382	782	0	0
T16	33456	19856	0	0
T17	14348	748	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	121196	0	0
T1	513276	0	0	0
T2	110326	0	0	0
T3	1191270	11	0	0
T4	1899912	88	0	0
T5	201266	0	0	0
T6	5721034	63	0	0
T7	8730486	64	0	0
T8	463376	0	0	0
T9	0	64	0	0
T10	0	96	0	0
T11	0	27	0	0
T15	661146	0	0	0
T16	2953506	0	0	0
T17	621294	0	0	0
T23	1191995	0	0	0
T24	1016396	0	0	0
T25	5230500	8	0	0
T26	2180675	0	0	0
T28	1022080	8	0	0
T29	0	9	0	0
T32	1727280	0	0	0
T33	0	48	0	0
T34	0	6	0	0
T45	0	117	0	0
T47	0	42	0	0
T48	6159882	7	0	0
T49	0	9	0	0
T50	0	7	0	0
T51	0	7	0	0
T52	0	5	0	0
T53	0	8	0	0
T54	0	9	0	0
T55	3761318	0	0	0
T56	3523539	0	0	0
T57	4391202	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	17451384	17441660	0	0
T2	3751084	3747752	0	0
T3	6750530	6726662	0	0
T5	6843044	6841038	0	0
T12	6638262	6634998	0	0
T13	5576952	5574674	0	0
T14	6874222	6872352	0	0
T15	3746494	3744114	0	0
T16	16736534	16733440	0	0
T17	3520666	3517266	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T4,T6,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T58,T19,T59
1	-	Covered	T4,T6,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T4,T6,T7
0	0	1	Covered	T4,T6,T7
0	0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T4,T6,T7
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1166373877	1239236	0	0
DstReqKnown_A	6109145	5236922	0	0
SrcAckBusyChk_A	1166373877	1219	0	0
SrcBusyKnown_A	1166373877	1164631351	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1239236	0	0
T4	135708	17121	0	0
T6	260047	2656	0	0
T7	513558	4392	0	0
T8	0	326	0	0
T9	0	17293	0	0
T10	0	5143	0	0
T11	0	3794	0	0
T21	0	579	0	0
T22	0	1870	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T45	0	3298	0	0
T48	362346	0	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T57	258306	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6109145	5236922	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1219	0	0
T4	135708	10	0	0
T6	260047	6	0	0
T7	513558	5	0	0
T8	0	1	0	0
T9	0	10	0	0
T10	0	11	0	0
T11	0	2	0	0
T21	0	2	0	0
T22	0	1	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T45	0	7	0	0
T48	362346	0	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T57	258306	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1164631351	0	0
T1	513276	512990	0	0
T2	110326	110228	0	0
T3	198545	197843	0	0
T5	201266	201207	0	0
T12	195243	195147	0	0
T13	164028	163961	0	0
T14	202183	202128	0	0
T15	110191	110121	0	0
T16	492251	492160	0	0
T17	103549	103449	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T1,T13,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T13,T3
1	1	Covered	T1,T13,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T1,T13,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T13,T3
1	1	Covered	T1,T13,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T1,T13,T3
0	0	1	Covered	T1,T13,T3
0	0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T1,T13,T3
0	0	1	Covered	T1,T13,T3
0	0	0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1166373877	2080567	0	0
DstReqKnown_A	6109145	5236922	0	0
SrcAckBusyChk_A	1166373877	2116	0	0
SrcBusyKnown_A	1166373877	1164631351	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	2080567	0	0
T1	513276	947	0	0
T2	110326	0	0	0
T3	198545	2838	0	0
T4	0	18248	0	0
T5	201266	0	0	0
T6	0	2978	0	0
T7	0	6672	0	0
T12	195243	0	0	0
T13	164028	952	0	0
T14	202183	0	0	0
T15	110191	0	0	0
T16	492251	1483	0	0
T17	103549	0	0	0
T25	0	334	0	0
T32	0	619	0	0
T60	0	1971	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6109145	5236922	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	2116	0	0
T1	513276	1	0	0
T2	110326	0	0	0
T3	198545	2	0	0
T4	0	11	0	0
T5	201266	0	0	0
T6	0	7	0	0
T7	0	8	0	0
T12	195243	0	0	0
T13	164028	1	0	0
T14	202183	0	0	0
T15	110191	0	0	0
T16	492251	1	0	0
T17	103549	0	0	0
T25	0	1	0	0
T32	0	1	0	0
T60	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1164631351	0	0
T1	513276	512990	0	0
T2	110326	110228	0	0
T3	198545	197843	0	0
T5	201266	201207	0	0
T12	195243	195147	0	0
T13	164028	163961	0	0
T14	202183	202128	0	0
T15	110191	110121	0	0
T16	492251	492160	0	0
T17	103549	103449	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T14,T3,T32

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T14,T3,T32
1	1	Covered	T14,T3,T32

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T14,T3,T32

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T3,T32
1	1	Covered	T14,T3,T32

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T14,T3,T32
0	0	1	Covered	T14,T3,T32
0	0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T14,T3,T32
0	0	1	Covered	T14,T3,T32
0	0	0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1166373877	1249144	0	0
DstReqKnown_A	6109145	5236922	0	0
SrcAckBusyChk_A	1166373877	1141	0	0
SrcBusyKnown_A	1166373877	1164631351	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1249144	0	0
T3	198545	1421	0	0
T4	135708	0	0	0
T6	260047	0	0	0
T7	0	731	0	0
T8	0	1211	0	0
T14	202183	1480	0	0
T15	110191	0	0	0
T16	492251	0	0	0
T17	103549	0	0	0
T21	0	932	0	0
T22	0	1897	0	0
T23	238399	0	0	0
T25	0	340	0	0
T28	204416	0	0	0
T32	345456	625	0	0
T36	0	72	0	0
T61	0	1983	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6109145	5236922	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1141	0	0
T3	198545	1	0	0
T4	135708	0	0	0
T6	260047	0	0	0
T7	0	1	0	0
T8	0	3	0	0
T14	202183	1	0	0
T15	110191	0	0	0
T16	492251	0	0	0
T17	103549	0	0	0
T21	0	3	0	0
T22	0	1	0	0
T23	238399	0	0	0
T25	0	1	0	0
T28	204416	0	0	0
T32	345456	1	0	0
T36	0	1	0	0
T61	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1164631351	0	0
T1	513276	512990	0	0
T2	110326	110228	0	0
T3	198545	197843	0	0
T5	201266	201207	0	0
T12	195243	195147	0	0
T13	164028	163961	0	0
T14	202183	202128	0	0
T15	110191	110121	0	0
T16	492251	492160	0	0
T17	103549	103449	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T14,T3,T32

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T14,T3,T32
1	1	Covered	T14,T3,T32

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T14,T3,T32

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T3,T32
1	1	Covered	T14,T3,T32

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T14,T3,T32
0	0	1	Covered	T14,T3,T32
0	0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T14,T3,T32
0	0	1	Covered	T14,T3,T32
0	0	0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1166373877	1266122	0	0
DstReqKnown_A	6109145	5236922	0	0
SrcAckBusyChk_A	1166373877	1182	0	0
SrcBusyKnown_A	1166373877	1164631351	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1266122	0	0
T3	198545	1419	0	0
T4	135708	0	0	0
T6	260047	0	0	0
T7	0	729	0	0
T8	0	1180	0	0
T14	202183	1470	0	0
T15	110191	0	0	0
T16	492251	0	0	0
T17	103549	0	0	0
T21	0	926	0	0
T22	0	1877	0	0
T23	238399	0	0	0
T25	0	324	0	0
T28	204416	0	0	0
T32	345456	615	0	0
T36	0	69	0	0
T61	0	1974	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6109145	5236922	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1182	0	0
T3	198545	1	0	0
T4	135708	0	0	0
T6	260047	0	0	0
T7	0	1	0	0
T8	0	3	0	0
T14	202183	1	0	0
T15	110191	0	0	0
T16	492251	0	0	0
T17	103549	0	0	0
T21	0	3	0	0
T22	0	1	0	0
T23	238399	0	0	0
T25	0	1	0	0
T28	204416	0	0	0
T32	345456	1	0	0
T36	0	1	0	0
T61	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1164631351	0	0
T1	513276	512990	0	0
T2	110326	110228	0	0
T3	198545	197843	0	0
T5	201266	201207	0	0
T12	195243	195147	0	0
T13	164028	163961	0	0
T14	202183	202128	0	0
T15	110191	110121	0	0
T16	492251	492160	0	0
T17	103549	103449	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T14,T3,T32

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T14,T3,T32
1	1	Covered	T14,T3,T32

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T14,T3,T32

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T3,T32
1	1	Covered	T14,T3,T32

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T14,T3,T32
0	0	1	Covered	T14,T3,T32
0	0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T14,T3,T32
0	0	1	Covered	T14,T3,T32
0	0	0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1166373877	1250050	0	0
DstReqKnown_A	6109145	5236922	0	0
SrcAckBusyChk_A	1166373877	1162	0	0
SrcBusyKnown_A	1166373877	1164631351	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1250050	0	0
T3	198545	1417	0	0
T4	135708	0	0	0
T6	260047	0	0	0
T7	0	727	0	0
T8	0	1142	0	0
T14	202183	1463	0	0
T15	110191	0	0	0
T16	492251	0	0	0
T17	103549	0	0	0
T21	0	920	0	0
T22	0	1861	0	0
T23	238399	0	0	0
T25	0	306	0	0
T28	204416	0	0	0
T32	345456	608	0	0
T36	0	62	0	0
T61	0	1962	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6109145	5236922	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1162	0	0
T3	198545	1	0	0
T4	135708	0	0	0
T6	260047	0	0	0
T7	0	1	0	0
T8	0	3	0	0
T14	202183	1	0	0
T15	110191	0	0	0
T16	492251	0	0	0
T17	103549	0	0	0
T21	0	3	0	0
T22	0	1	0	0
T23	238399	0	0	0
T25	0	1	0	0
T28	204416	0	0	0
T32	345456	1	0	0
T36	0	1	0	0
T61	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1164631351	0	0
T1	513276	512990	0	0
T2	110326	110228	0	0
T3	198545	197843	0	0
T5	201266	201207	0	0
T12	195243	195147	0	0
T13	164028	163961	0	0
T14	202183	202128	0	0
T15	110191	110121	0	0
T16	492251	492160	0	0
T17	103549	103449	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T23,T24,T22

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T23,T24,T22
1	1	Covered	T23,T24,T22

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T23,T24,T22

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T23,T24,T22
1	1	Covered	T23,T24,T22

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T23,T24,T22
0	0	1	Covered	T23,T24,T22
0	0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T23,T24,T22
0	0	1	Covered	T23,T24,T22
0	0	0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1166373877	3051779	0	0
DstReqKnown_A	6109145	5236922	0	0
SrcAckBusyChk_A	1166373877	3126	0	0
SrcBusyKnown_A	1166373877	1164631351	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	3051779	0	0
T4	135708	0	0	0
T6	260047	0	0	0
T7	513558	0	0	0
T22	0	34437	0	0
T23	238399	33382	0	0
T24	59788	8652	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T28	204416	0	0	0
T32	345456	0	0	0
T55	221254	0	0	0
T62	0	32643	0	0
T63	0	16462	0	0
T64	0	35317	0	0
T65	0	13977	0	0
T66	0	17043	0	0
T67	0	5999	0	0
T68	0	8042	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6109145	5236922	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	3126	0	0
T4	135708	0	0	0
T6	260047	0	0	0
T7	513558	0	0	0
T22	0	20	0	0
T23	238399	20	0	0
T24	59788	20	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T28	204416	0	0	0
T32	345456	0	0	0
T55	221254	0	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	0	20	0	0
T65	0	40	0	0
T66	0	20	0	0
T67	0	20	0	0
T68	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1164631351	0	0
T1	513276	512990	0	0
T2	110326	110228	0	0
T3	198545	197843	0	0
T5	201266	201207	0	0
T12	195243	195147	0	0
T13	164028	163961	0	0
T14	202183	202128	0	0
T15	110191	110121	0	0
T16	492251	492160	0	0
T17	103549	103449	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T3,T23,T25

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T3,T23,T25
1	1	Covered	T3,T23,T25

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T3,T23,T25

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T23,T25
1	1	Covered	T3,T23,T25

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T3,T23,T25
0	0	1	Covered	T3,T23,T25
0	0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T3,T23,T25
0	0	1	Covered	T3,T23,T25
0	0	0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1166373877	5748991	0	0
DstReqKnown_A	6109145	5236922	0	0
SrcAckBusyChk_A	1166373877	6689	0	0
SrcBusyKnown_A	1166373877	1164631351	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	5748991	0	0
T3	198545	34129	0	0
T4	135708	0	0	0
T6	260047	0	0	0
T15	110191	0	0	0
T16	492251	0	0	0
T17	103549	0	0	0
T22	0	35496	0	0
T23	238399	1444	0	0
T24	0	472	0	0
T25	237750	5447	0	0
T26	0	16146	0	0
T28	204416	0	0	0
T32	345456	0	0	0
T36	0	1792	0	0
T57	0	34080	0	0
T69	0	16967	0	0
T70	0	1806	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6109145	5236922	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	6689	0	0
T3	198545	20	0	0
T4	135708	0	0	0
T6	260047	0	0	0
T15	110191	0	0	0
T16	492251	0	0	0
T17	103549	0	0	0
T22	0	21	0	0
T23	238399	1	0	0
T24	0	1	0	0
T25	237750	20	0	0
T26	0	20	0	0
T28	204416	0	0	0
T32	345456	0	0	0
T36	0	20	0	0
T57	0	20	0	0
T69	0	20	0	0
T70	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1164631351	0	0
T1	513276	512990	0	0
T2	110326	110228	0	0
T3	198545	197843	0	0
T5	201266	201207	0	0
T12	195243	195147	0	0
T13	164028	163961	0	0
T14	202183	202128	0	0
T15	110191	110121	0	0
T16	492251	492160	0	0
T17	103549	103449	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T1,T13,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T13,T3
1	1	Covered	T1,T13,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T1,T13,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T13,T3
1	1	Covered	T1,T13,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T1,T13,T3
0	0	1	Covered	T1,T13,T3
0	0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T1,T13,T3
0	0	1	Covered	T1,T13,T3
0	0	0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1166373877	6803398	0	0
DstReqKnown_A	6109145	5236922	0	0
SrcAckBusyChk_A	1166373877	7811	0	0
SrcBusyKnown_A	1166373877	1164631351	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	6803398	0	0
T1	513276	959	0	0
T2	110326	0	0	0
T3	198545	38009	0	0
T4	0	19026	0	0
T5	201266	0	0	0
T6	0	3048	0	0
T12	195243	0	0	0
T13	164028	954	0	0
T14	202183	0	0	0
T15	110191	0	0	0
T16	492251	1487	0	0
T17	103549	0	0	0
T23	0	1449	0	0
T25	0	6217	0	0
T26	0	16562	0	0
T32	0	625	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6109145	5236922	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	7811	0	0
T1	513276	1	0	0
T2	110326	0	0	0
T3	198545	22	0	0
T4	0	11	0	0
T5	201266	0	0	0
T6	0	7	0	0
T12	195243	0	0	0
T13	164028	1	0	0
T14	202183	0	0	0
T15	110191	0	0	0
T16	492251	1	0	0
T17	103549	0	0	0
T23	0	1	0	0
T25	0	21	0	0
T26	0	20	0	0
T32	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1164631351	0	0
T1	513276	512990	0	0
T2	110326	110228	0	0
T3	198545	197843	0	0
T5	201266	201207	0	0
T12	195243	195147	0	0
T13	164028	163961	0	0
T14	202183	202128	0	0
T15	110191	110121	0	0
T16	492251	492160	0	0
T17	103549	103449	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T3,T25,T26

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T3,T25,T26
1	1	Covered	T3,T25,T26

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T3,T25,T26

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T25,T26
1	1	Covered	T3,T25,T26

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T3,T25,T26
0	0	1	Covered	T3,T25,T26
0	0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T3,T25,T26
0	0	1	Covered	T3,T25,T26
0	0	0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1166373877	5670559	0	0
DstReqKnown_A	6109145	5236922	0	0
SrcAckBusyChk_A	1166373877	6567	0	0
SrcBusyKnown_A	1166373877	1164631351	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	5670559	0	0
T3	198545	34169	0	0
T4	135708	0	0	0
T6	260047	0	0	0
T15	110191	0	0	0
T16	492251	0	0	0
T17	103549	0	0	0
T22	0	34257	0	0
T23	238399	0	0	0
T25	237750	5657	0	0
T26	0	16360	0	0
T28	204416	0	0	0
T32	345456	0	0	0
T36	0	1873	0	0
T57	0	34120	0	0
T69	0	17007	0	0
T70	0	1825	0	0
T71	0	16528	0	0
T72	0	3645	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6109145	5236922	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	6567	0	0
T3	198545	20	0	0
T4	135708	0	0	0
T6	260047	0	0	0
T15	110191	0	0	0
T16	492251	0	0	0
T17	103549	0	0	0
T22	0	20	0	0
T23	238399	0	0	0
T25	237750	20	0	0
T26	0	20	0	0
T28	204416	0	0	0
T32	345456	0	0	0
T36	0	20	0	0
T57	0	20	0	0
T69	0	20	0	0
T70	0	20	0	0
T71	0	20	0	0
T72	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1164631351	0	0
T1	513276	512990	0	0
T2	110326	110228	0	0
T3	198545	197843	0	0
T5	201266	201207	0	0
T12	195243	195147	0	0
T13	164028	163961	0	0
T14	202183	202128	0	0
T15	110191	110121	0	0
T16	492251	492160	0	0
T17	103549	103449	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T1,T2,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T2,T27
1	1	Covered	T1,T2,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T1,T2,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T27
1	1	Covered	T1,T2,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T1,T2,T27
0	0	1	Covered	T1,T2,T27
0	0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T1,T2,T27
0	0	1	Covered	T1,T2,T27
0	0	0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1166373877	1302349	0	0
DstReqKnown_A	6109145	5236922	0	0
SrcAckBusyChk_A	1166373877	1210	0	0
SrcBusyKnown_A	1166373877	1164631351	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1302349	0	0
T1	513276	944	0	0
T2	110326	737	0	0
T3	198545	0	0	0
T5	201266	0	0	0
T12	195243	0	0	0
T13	164028	0	0	0
T14	202183	0	0	0
T15	110191	0	0	0
T16	492251	0	0	0
T17	103549	0	0	0
T27	0	437	0	0
T35	0	1477	0	0
T36	0	83	0	0
T37	0	650	0	0
T38	0	954	0	0
T40	0	917	0	0
T41	0	1960	0	0
T42	0	551	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6109145	5236922	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1210	0	0
T1	513276	1	0	0
T2	110326	1	0	0
T3	198545	0	0	0
T5	201266	0	0	0
T12	195243	0	0	0
T13	164028	0	0	0
T14	202183	0	0	0
T15	110191	0	0	0
T16	492251	0	0	0
T17	103549	0	0	0
T27	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1164631351	0	0
T1	513276	512990	0	0
T2	110326	110228	0	0
T3	198545	197843	0	0
T5	201266	201207	0	0
T12	195243	195147	0	0
T13	164028	163961	0	0
T14	202183	202128	0	0
T15	110191	110121	0	0
T16	492251	492160	0	0
T17	103549	103449	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1166373877	2088729	0	0
DstReqKnown_A	6109145	5236922	0	0
SrcAckBusyChk_A	1166373877	2131	0	0
SrcBusyKnown_A	1166373877	1164631351	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	2088729	0	0
T1	513276	940	0	0
T2	110326	732	0	0
T3	198545	1414	0	0
T4	0	18182	0	0
T5	201266	0	0	0
T6	0	2946	0	0
T7	0	6656	0	0
T9	0	13748	0	0
T10	0	5433	0	0
T11	0	4581	0	0
T12	195243	0	0	0
T13	164028	0	0	0
T14	202183	0	0	0
T15	110191	0	0	0
T16	492251	0	0	0
T17	103549	0	0	0
T29	0	1899	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6109145	5236922	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	2131	0	0
T1	513276	1	0	0
T2	110326	1	0	0
T3	198545	1	0	0
T4	0	11	0	0
T5	201266	0	0	0
T6	0	7	0	0
T7	0	8	0	0
T9	0	8	0	0
T10	0	12	0	0
T11	0	3	0	0
T12	195243	0	0	0
T13	164028	0	0	0
T14	202183	0	0	0
T15	110191	0	0	0
T16	492251	0	0	0
T17	103549	0	0	0
T29	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1164631351	0	0
T1	513276	512990	0	0
T2	110326	110228	0	0
T3	198545	197843	0	0
T5	201266	201207	0	0
T12	195243	195147	0	0
T13	164028	163961	0	0
T14	202183	202128	0	0
T15	110191	110121	0	0
T16	492251	492160	0	0
T17	103549	103449	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T3,T28,T25

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T3,T28,T25
1	1	Covered	T3,T28,T25

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T3,T28,T25

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T28,T25
1	1	Covered	T3,T28,T25

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T3,T28,T25
0	0	1	Covered	T3,T28,T25
0	0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T3,T28,T25
0	0	1	Covered	T3,T28,T25
0	0	0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1166373877	1480336	0	0
DstReqKnown_A	6109145	5236922	0	0
SrcAckBusyChk_A	1166373877	1428	0	0
SrcBusyKnown_A	1166373877	1164631351	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1480336	0	0
T3	198545	9967	0	0
T4	135708	0	0	0
T6	260047	0	0	0
T15	110191	0	0	0
T16	492251	0	0	0
T17	103549	0	0	0
T23	238399	0	0	0
T25	237750	1587	0	0
T28	204416	1716	0	0
T32	345456	0	0	0
T48	0	6983	0	0
T49	0	1542	0	0
T50	0	6218	0	0
T51	0	6995	0	0
T52	0	5961	0	0
T53	0	4223	0	0
T54	0	821	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6109145	5236922	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1428	0	0
T3	198545	6	0	0
T4	135708	0	0	0
T6	260047	0	0	0
T15	110191	0	0	0
T16	492251	0	0	0
T17	103549	0	0	0
T23	238399	0	0	0
T25	237750	5	0	0
T28	204416	5	0	0
T32	345456	0	0	0
T48	0	4	0	0
T49	0	6	0	0
T50	0	4	0	0
T51	0	4	0	0
T52	0	3	0	0
T53	0	5	0	0
T54	0	6	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1164631351	0	0
T1	513276	512990	0	0
T2	110326	110228	0	0
T3	198545	197843	0	0
T5	201266	201207	0	0
T12	195243	195147	0	0
T13	164028	163961	0	0
T14	202183	202128	0	0
T15	110191	110121	0	0
T16	492251	492160	0	0
T17	103549	103449	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T3,T28,T25

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T3,T28,T25
1	1	Covered	T3,T28,T25

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T3,T28,T25

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T28,T25
1	1	Covered	T3,T28,T25

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T3,T28,T25
0	0	1	Covered	T3,T28,T25
0	0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T3,T28,T25
0	0	1	Covered	T3,T28,T25
0	0	0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1166373877	1366928	0	0
DstReqKnown_A	6109145	5236922	0	0
SrcAckBusyChk_A	1166373877	1291	0	0
SrcBusyKnown_A	1166373877	1164631351	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1366928	0	0
T3	198545	4262	0	0
T4	135708	0	0	0
T6	260047	0	0	0
T15	110191	0	0	0
T16	492251	0	0	0
T17	103549	0	0	0
T23	238399	0	0	0
T25	237750	978	0	0
T28	204416	1055	0	0
T32	345456	0	0	0
T48	0	4962	0	0
T49	0	780	0	0
T50	0	4764	0	0
T51	0	4988	0	0
T52	0	3953	0	0
T53	0	2575	0	0
T54	0	418	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6109145	5236922	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1291	0	0
T3	198545	3	0	0
T4	135708	0	0	0
T6	260047	0	0	0
T15	110191	0	0	0
T16	492251	0	0	0
T17	103549	0	0	0
T23	238399	0	0	0
T25	237750	3	0	0
T28	204416	3	0	0
T32	345456	0	0	0
T48	0	3	0	0
T49	0	3	0	0
T50	0	3	0	0
T51	0	3	0	0
T52	0	2	0	0
T53	0	3	0	0
T54	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1164631351	0	0
T1	513276	512990	0	0
T2	110326	110228	0	0
T3	198545	197843	0	0
T5	201266	201207	0	0
T12	195243	195147	0	0
T13	164028	163961	0	0
T14	202183	202128	0	0
T15	110191	110121	0	0
T16	492251	492160	0	0
T17	103549	103449	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T6,T29,T11

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T6,T29,T11
1	1	Covered	T6,T29,T11

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T6,T29,T11

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T29,T11
1	1	Covered	T6,T29,T11

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T6,T29,T11
0	0	1	Covered	T6,T29,T11
0	0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T6,T29,T11
0	0	1	Covered	T6,T29,T11
0	0	0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1166373877	6350722	0	0
DstReqKnown_A	6109145	5236922	0	0
SrcAckBusyChk_A	1166373877	7355	0	0
SrcBusyKnown_A	1166373877	1164631351	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	6350722	0	0
T6	260047	24651	0	0
T7	513558	0	0	0
T8	57922	0	0	0
T11	0	140271	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T29	0	125407	0	0
T34	0	116919	0	0
T45	0	34373	0	0
T46	0	60335	0	0
T47	0	53813	0	0
T48	362346	0	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T57	258306	0	0	0
T73	0	59263	0	0
T74	0	20402	0	0
T75	0	9371	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6109145	5236922	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	7355	0	0
T6	260047	57	0	0
T7	513558	0	0	0
T8	57922	0	0	0
T11	0	84	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T29	0	75	0	0
T34	0	69	0	0
T45	0	69	0	0
T46	0	71	0	0
T47	0	56	0	0
T48	362346	0	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T57	258306	0	0	0
T73	0	68	0	0
T74	0	51	0	0
T75	0	70	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1164631351	0	0
T1	513276	512990	0	0
T2	110326	110228	0	0
T3	198545	197843	0	0
T5	201266	201207	0	0
T12	195243	195147	0	0
T13	164028	163961	0	0
T14	202183	202128	0	0
T15	110191	110121	0	0
T16	492251	492160	0	0
T17	103549	103449	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T6,T29,T11

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T6,T29,T11
1	1	Covered	T6,T29,T11

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T6,T29,T11

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T29,T11
1	1	Covered	T6,T29,T11

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T6,T29,T11
0	0	1	Covered	T6,T29,T11
0	0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T6,T29,T11
0	0	1	Covered	T6,T29,T11
0	0	0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1166373877	6370795	0	0
DstReqKnown_A	6109145	5236922	0	0
SrcAckBusyChk_A	1166373877	7523	0	0
SrcBusyKnown_A	1166373877	1164631351	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	6370795	0	0
T6	260047	35603	0	0
T7	513558	0	0	0
T8	57922	0	0	0
T11	0	87202	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T29	0	104801	0	0
T34	0	115526	0	0
T45	0	34401	0	0
T46	0	79184	0	0
T47	0	59912	0	0
T48	362346	0	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T57	258306	0	0	0
T73	0	75141	0	0
T74	0	19400	0	0
T75	0	11369	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6109145	5236922	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	7523	0	0
T6	260047	84	0	0
T7	513558	0	0	0
T8	57922	0	0	0
T11	0	53	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T29	0	63	0	0
T34	0	69	0	0
T45	0	72	0	0
T46	0	92	0	0
T47	0	63	0	0
T48	362346	0	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T57	258306	0	0	0
T73	0	88	0	0
T74	0	51	0	0
T75	0	91	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1164631351	0	0
T1	513276	512990	0	0
T2	110326	110228	0	0
T3	198545	197843	0	0
T5	201266	201207	0	0
T12	195243	195147	0	0
T13	164028	163961	0	0
T14	202183	202128	0	0
T15	110191	110121	0	0
T16	492251	492160	0	0
T17	103549	103449	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T6,T29,T11

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T6,T29,T11
1	1	Covered	T6,T29,T11

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T6,T29,T11

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T29,T11
1	1	Covered	T6,T29,T11

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T6,T29,T11
0	0	1	Covered	T6,T29,T11
0	0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T6,T29,T11
0	0	1	Covered	T6,T29,T11
0	0	0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1166373877	6230738	0	0
DstReqKnown_A	6109145	5236922	0	0
SrcAckBusyChk_A	1166373877	7380	0	0
SrcBusyKnown_A	1166373877	1164631351	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	6230738	0	0
T6	260047	34278	0	0
T7	513558	0	0	0
T8	57922	0	0	0
T11	0	113377	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T29	0	146230	0	0
T34	0	92002	0	0
T45	0	36011	0	0
T46	0	55753	0	0
T47	0	58368	0	0
T48	362346	0	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T57	258306	0	0	0
T73	0	73488	0	0
T74	0	18384	0	0
T75	0	10793	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6109145	5236922	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	7380	0	0
T6	260047	84	0	0
T7	513558	0	0	0
T8	57922	0	0	0
T11	0	70	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T29	0	87	0	0
T34	0	56	0	0
T45	0	79	0	0
T46	0	67	0	0
T47	0	63	0	0
T48	362346	0	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T57	258306	0	0	0
T73	0	88	0	0
T74	0	51	0	0
T75	0	83	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1164631351	0	0
T1	513276	512990	0	0
T2	110326	110228	0	0
T3	198545	197843	0	0
T5	201266	201207	0	0
T12	195243	195147	0	0
T13	164028	163961	0	0
T14	202183	202128	0	0
T15	110191	110121	0	0
T16	492251	492160	0	0
T17	103549	103449	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T6,T29,T11

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T6,T29,T11
1	1	Covered	T6,T29,T11

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T6,T29,T11

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T29,T11
1	1	Covered	T6,T29,T11

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T6,T29,T11
0	0	1	Covered	T6,T29,T11
0	0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T6,T29,T11
0	0	1	Covered	T6,T29,T11
0	0	0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1166373877	6048300	0	0
DstReqKnown_A	6109145	5236922	0	0
SrcAckBusyChk_A	1166373877	7350	0	0
SrcBusyKnown_A	1166373877	1164631351	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	6048300	0	0
T6	260047	33277	0	0
T7	513558	0	0	0
T8	57922	0	0	0
T11	0	135780	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T29	0	104414	0	0
T34	0	112889	0	0
T45	0	36194	0	0
T46	0	57921	0	0
T47	0	56850	0	0
T48	362346	0	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T57	258306	0	0	0
T73	0	51661	0	0
T74	0	17584	0	0
T75	0	7968	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6109145	5236922	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	7350	0	0
T6	260047	84	0	0
T7	513558	0	0	0
T8	57922	0	0	0
T11	0	84	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T29	0	63	0	0
T34	0	69	0	0
T45	0	79	0	0
T46	0	71	0	0
T47	0	63	0	0
T48	362346	0	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T57	258306	0	0	0
T73	0	63	0	0
T74	0	51	0	0
T75	0	64	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1164631351	0	0
T1	513276	512990	0	0
T2	110326	110228	0	0
T3	198545	197843	0	0
T5	201266	201207	0	0
T12	195243	195147	0	0
T13	164028	163961	0	0
T14	202183	202128	0	0
T15	110191	110121	0	0
T16	492251	492160	0	0
T17	103549	103449	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T6,T29,T11

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T6,T29,T11
1	1	Covered	T6,T29,T11

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T6,T29,T11

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T29,T11
1	1	Covered	T6,T29,T11

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T6,T29,T11
0	0	1	Covered	T6,T29,T11
0	0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T6,T29,T11
0	0	1	Covered	T6,T29,T11
0	0	0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1166373877	1466857	0	0
DstReqKnown_A	6109145	5236922	0	0
SrcAckBusyChk_A	1166373877	1393	0	0
SrcBusyKnown_A	1166373877	1164631351	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1466857	0	0
T6	260047	3055	0	0
T7	513558	0	0	0
T8	57922	0	0	0
T11	0	5220	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T29	0	1939	0	0
T34	0	10144	0	0
T45	0	6593	0	0
T46	0	1703	0	0
T47	0	4949	0	0
T48	362346	0	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T57	258306	0	0	0
T73	0	734	0	0
T74	0	326	0	0
T75	0	116	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6109145	5236922	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1393	0	0
T6	260047	7	0	0
T7	513558	0	0	0
T8	57922	0	0	0
T11	0	3	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T29	0	1	0	0
T34	0	6	0	0
T45	0	13	0	0
T46	0	2	0	0
T47	0	6	0	0
T48	362346	0	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T57	258306	0	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1164631351	0	0
T1	513276	512990	0	0
T2	110326	110228	0	0
T3	198545	197843	0	0
T5	201266	201207	0	0
T12	195243	195147	0	0
T13	164028	163961	0	0
T14	202183	202128	0	0
T15	110191	110121	0	0
T16	492251	492160	0	0
T17	103549	103449	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T6,T29,T11

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T6,T29,T11
1	1	Covered	T6,T29,T11

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T6,T29,T11

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T29,T11
1	1	Covered	T6,T29,T11

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T6,T29,T11
0	0	1	Covered	T6,T29,T11
0	0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T6,T29,T11
0	0	1	Covered	T6,T29,T11
0	0	0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1166373877	1431839	0	0
DstReqKnown_A	6109145	5236922	0	0
SrcAckBusyChk_A	1166373877	1392	0	0
SrcBusyKnown_A	1166373877	1164631351	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1431839	0	0
T6	260047	2781	0	0
T7	513558	0	0	0
T8	57922	0	0	0
T11	0	5084	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T29	0	1929	0	0
T34	0	9902	0	0
T45	0	5863	0	0
T46	0	1618	0	0
T47	0	4653	0	0
T48	362346	0	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T57	258306	0	0	0
T73	0	692	0	0
T74	0	285	0	0
T75	0	111	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6109145	5236922	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1392	0	0
T6	260047	7	0	0
T7	513558	0	0	0
T8	57922	0	0	0
T11	0	3	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T29	0	1	0	0
T34	0	6	0	0
T45	0	13	0	0
T46	0	2	0	0
T47	0	6	0	0
T48	362346	0	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T57	258306	0	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1164631351	0	0
T1	513276	512990	0	0
T2	110326	110228	0	0
T3	198545	197843	0	0
T5	201266	201207	0	0
T12	195243	195147	0	0
T13	164028	163961	0	0
T14	202183	202128	0	0
T15	110191	110121	0	0
T16	492251	492160	0	0
T17	103549	103449	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T6,T29,T11

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T6,T29,T11
1	1	Covered	T6,T29,T11

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T6,T29,T11

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T29,T11
1	1	Covered	T6,T29,T11

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T6,T29,T11
0	0	1	Covered	T6,T29,T11
0	0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T6,T29,T11
0	0	1	Covered	T6,T29,T11
0	0	0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1166373877	1415363	0	0
DstReqKnown_A	6109145	5236922	0	0
SrcAckBusyChk_A	1166373877	1387	0	0
SrcBusyKnown_A	1166373877	1164631351	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1415363	0	0
T6	260047	2527	0	0
T7	513558	0	0	0
T8	57922	0	0	0
T11	0	4927	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T29	0	1919	0	0
T34	0	9603	0	0
T45	0	5115	0	0
T46	0	1537	0	0
T47	0	4326	0	0
T48	362346	0	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T57	258306	0	0	0
T73	0	627	0	0
T74	0	346	0	0
T75	0	103	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6109145	5236922	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1387	0	0
T6	260047	7	0	0
T7	513558	0	0	0
T8	57922	0	0	0
T11	0	3	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T29	0	1	0	0
T34	0	6	0	0
T45	0	13	0	0
T46	0	2	0	0
T47	0	6	0	0
T48	362346	0	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T57	258306	0	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1164631351	0	0
T1	513276	512990	0	0
T2	110326	110228	0	0
T3	198545	197843	0	0
T5	201266	201207	0	0
T12	195243	195147	0	0
T13	164028	163961	0	0
T14	202183	202128	0	0
T15	110191	110121	0	0
T16	492251	492160	0	0
T17	103549	103449	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T6,T29,T11

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T6,T29,T11
1	1	Covered	T6,T29,T11

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T6,T29,T11

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T29,T11
1	1	Covered	T6,T29,T11

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T6,T29,T11
0	0	1	Covered	T6,T29,T11
0	0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T6,T29,T11
0	0	1	Covered	T6,T29,T11
0	0	0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1166373877	1420400	0	0
DstReqKnown_A	6109145	5236922	0	0
SrcAckBusyChk_A	1166373877	1392	0	0
SrcBusyKnown_A	1166373877	1164631351	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1420400	0	0
T6	260047	2545	0	0
T7	513558	0	0	0
T8	57922	0	0	0
T11	0	4744	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T29	0	1909	0	0
T34	0	9324	0	0
T45	0	6381	0	0
T46	0	1449	0	0
T47	0	4011	0	0
T48	362346	0	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T57	258306	0	0	0
T73	0	580	0	0
T74	0	299	0	0
T75	0	93	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6109145	5236922	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1392	0	0
T6	260047	7	0	0
T7	513558	0	0	0
T8	57922	0	0	0
T11	0	3	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T29	0	1	0	0
T34	0	6	0	0
T45	0	13	0	0
T46	0	2	0	0
T47	0	6	0	0
T48	362346	0	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T57	258306	0	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1164631351	0	0
T1	513276	512990	0	0
T2	110326	110228	0	0
T3	198545	197843	0	0
T5	201266	201207	0	0
T12	195243	195147	0	0
T13	164028	163961	0	0
T14	202183	202128	0	0
T15	110191	110121	0	0
T16	492251	492160	0	0
T17	103549	103449	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T3,T4,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T3,T4,T6
1	1	Covered	T3,T4,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T3,T4,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T6
1	1	Covered	T3,T4,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T3,T4,T6
0	0	1	Covered	T3,T4,T6
0	0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T3,T4,T6
0	0	1	Covered	T3,T4,T6
0	0	0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1166373877	6970908	0	0
DstReqKnown_A	6109145	5236922	0	0
SrcAckBusyChk_A	1166373877	7966	0	0
SrcBusyKnown_A	1166373877	1164631351	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	6970908	0	0
T3	198545	1422	0	0
T4	135708	19161	0	0
T6	260047	24933	0	0
T7	0	6864	0	0
T9	0	14460	0	0
T10	0	5745	0	0
T11	0	141023	0	0
T15	110191	0	0	0
T16	492251	0	0	0
T17	103549	0	0	0
T23	238399	0	0	0
T25	237750	0	0	0
T28	204416	0	0	0
T29	0	125551	0	0
T32	345456	0	0	0
T33	0	11469	0	0
T45	0	34604	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6109145	5236922	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	7966	0	0
T3	198545	1	0	0
T4	135708	11	0	0
T6	260047	57	0	0
T7	0	8	0	0
T9	0	8	0	0
T10	0	12	0	0
T11	0	84	0	0
T15	110191	0	0	0
T16	492251	0	0	0
T17	103549	0	0	0
T23	238399	0	0	0
T25	237750	0	0	0
T28	204416	0	0	0
T29	0	75	0	0
T32	345456	0	0	0
T33	0	6	0	0
T45	0	69	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1164631351	0	0
T1	513276	512990	0	0
T2	110326	110228	0	0
T3	198545	197843	0	0
T5	201266	201207	0	0
T12	195243	195147	0	0
T13	164028	163961	0	0
T14	202183	202128	0	0
T15	110191	110121	0	0
T16	492251	492160	0	0
T17	103549	103449	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T4,T6,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T4,T6,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T4,T6,T7
0	0	1	Covered	T4,T6,T7
0	0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T4,T6,T7
0	0	1	Covered	T4,T6,T7
0	0	0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1166373877	6948516	0	0
DstReqKnown_A	6109145	5236922	0	0
SrcAckBusyChk_A	1166373877	8093	0	0
SrcBusyKnown_A	1166373877	1164631351	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	6948516	0	0
T4	135708	19084	0	0
T6	260047	36016	0	0
T7	513558	6848	0	0
T9	0	14407	0	0
T10	0	5721	0	0
T11	0	87649	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T29	0	104921	0	0
T33	0	11405	0	0
T45	0	34686	0	0
T47	0	60428	0	0
T48	362346	0	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T57	258306	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6109145	5236922	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	8093	0	0
T4	135708	11	0	0
T6	260047	84	0	0
T7	513558	8	0	0
T9	0	8	0	0
T10	0	12	0	0
T11	0	53	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T29	0	63	0	0
T33	0	6	0	0
T45	0	72	0	0
T47	0	63	0	0
T48	362346	0	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T57	258306	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1164631351	0	0
T1	513276	512990	0	0
T2	110326	110228	0	0
T3	198545	197843	0	0
T5	201266	201207	0	0
T12	195243	195147	0	0
T13	164028	163961	0	0
T14	202183	202128	0	0
T15	110191	110121	0	0
T16	492251	492160	0	0
T17	103549	103449	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T4,T6,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T4,T6,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T4,T6,T7
0	0	1	Covered	T4,T6,T7
0	0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T4,T6,T7
0	0	1	Covered	T4,T6,T7
0	0	0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1166373877	6815844	0	0
DstReqKnown_A	6109145	5236922	0	0
SrcAckBusyChk_A	1166373877	7955	0	0
SrcBusyKnown_A	1166373877	1164631351	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	6815844	0	0
T4	135708	19020	0	0
T6	260047	34731	0	0
T7	513558	6832	0	0
T9	0	14362	0	0
T10	0	5697	0	0
T11	0	113998	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T29	0	146398	0	0
T33	0	11329	0	0
T45	0	36525	0	0
T47	0	58830	0	0
T48	362346	0	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T57	258306	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6109145	5236922	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	7955	0	0
T4	135708	11	0	0
T6	260047	84	0	0
T7	513558	8	0	0
T9	0	8	0	0
T10	0	12	0	0
T11	0	70	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T29	0	87	0	0
T33	0	6	0	0
T45	0	79	0	0
T47	0	63	0	0
T48	362346	0	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T57	258306	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1164631351	0	0
T1	513276	512990	0	0
T2	110326	110228	0	0
T3	198545	197843	0	0
T5	201266	201207	0	0
T12	195243	195147	0	0
T13	164028	163961	0	0
T14	202183	202128	0	0
T15	110191	110121	0	0
T16	492251	492160	0	0
T17	103549	103449	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T4,T6,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T4,T6,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T4,T6,T7
0	0	1	Covered	T4,T6,T7
0	0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T4,T6,T7
0	0	1	Covered	T4,T6,T7
0	0	0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1166373877	6651354	0	0
DstReqKnown_A	6109145	5236922	0	0
SrcAckBusyChk_A	1166373877	7912	0	0
SrcBusyKnown_A	1166373877	1164631351	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	6651354	0	0
T4	135708	18946	0	0
T6	260047	34015	0	0
T7	513558	6816	0	0
T9	0	14297	0	0
T10	0	5673	0	0
T11	0	136556	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T29	0	104534	0	0
T33	0	11277	0	0
T45	0	36570	0	0
T47	0	57295	0	0
T48	362346	0	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T57	258306	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6109145	5236922	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	7912	0	0
T4	135708	11	0	0
T6	260047	84	0	0
T7	513558	8	0	0
T9	0	8	0	0
T10	0	12	0	0
T11	0	84	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T29	0	63	0	0
T33	0	6	0	0
T45	0	79	0	0
T47	0	63	0	0
T48	362346	0	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T57	258306	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1164631351	0	0
T1	513276	512990	0	0
T2	110326	110228	0	0
T3	198545	197843	0	0
T5	201266	201207	0	0
T12	195243	195147	0	0
T13	164028	163961	0	0
T14	202183	202128	0	0
T15	110191	110121	0	0
T16	492251	492160	0	0
T17	103549	103449	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T3,T4,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T3,T4,T6
1	1	Covered	T3,T4,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T3,T4,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T6
1	1	Covered	T3,T4,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T3,T4,T6
0	0	1	Covered	T3,T4,T6
0	0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T3,T4,T6
0	0	1	Covered	T3,T4,T6
0	0	0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1166373877	2044419	0	0
DstReqKnown_A	6109145	5236922	0	0
SrcAckBusyChk_A	1166373877	2021	0	0
SrcBusyKnown_A	1166373877	1164631351	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	2044419	0	0
T3	198545	1420	0	0
T4	135708	18886	0	0
T6	260047	2962	0	0
T7	0	6800	0	0
T9	0	14241	0	0
T10	0	5649	0	0
T11	0	5169	0	0
T15	110191	0	0	0
T16	492251	0	0	0
T17	103549	0	0	0
T23	238399	0	0	0
T25	237750	0	0	0
T28	204416	0	0	0
T29	0	1935	0	0
T32	345456	0	0	0
T33	0	11226	0	0
T45	0	6265	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6109145	5236922	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	2021	0	0
T3	198545	1	0	0
T4	135708	11	0	0
T6	260047	7	0	0
T7	0	8	0	0
T9	0	8	0	0
T10	0	12	0	0
T11	0	3	0	0
T15	110191	0	0	0
T16	492251	0	0	0
T17	103549	0	0	0
T23	238399	0	0	0
T25	237750	0	0	0
T28	204416	0	0	0
T29	0	1	0	0
T32	345456	0	0	0
T33	0	6	0	0
T45	0	13	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1164631351	0	0
T1	513276	512990	0	0
T2	110326	110228	0	0
T3	198545	197843	0	0
T5	201266	201207	0	0
T12	195243	195147	0	0
T13	164028	163961	0	0
T14	202183	202128	0	0
T15	110191	110121	0	0
T16	492251	492160	0	0
T17	103549	103449	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T4,T6,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T4,T6,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T4,T6,T7
0	0	1	Covered	T4,T6,T7
0	0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T4,T6,T7
0	0	1	Covered	T4,T6,T7
0	0	0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1166373877	1965792	0	0
DstReqKnown_A	6109145	5236922	0	0
SrcAckBusyChk_A	1166373877	1943	0	0
SrcBusyKnown_A	1166373877	1164631351	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1965792	0	0
T4	135708	18803	0	0
T6	260047	2679	0	0
T7	513558	6784	0	0
T9	0	14173	0	0
T10	0	5625	0	0
T11	0	5015	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T29	0	1925	0	0
T33	0	11154	0	0
T45	0	5538	0	0
T47	0	4516	0	0
T48	362346	0	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T57	258306	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6109145	5236922	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1943	0	0
T4	135708	11	0	0
T6	260047	7	0	0
T7	513558	8	0	0
T9	0	8	0	0
T10	0	12	0	0
T11	0	3	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T29	0	1	0	0
T33	0	6	0	0
T45	0	13	0	0
T47	0	6	0	0
T48	362346	0	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T57	258306	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1164631351	0	0
T1	513276	512990	0	0
T2	110326	110228	0	0
T3	198545	197843	0	0
T5	201266	201207	0	0
T12	195243	195147	0	0
T13	164028	163961	0	0
T14	202183	202128	0	0
T15	110191	110121	0	0
T16	492251	492160	0	0
T17	103549	103449	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T4,T6,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T4,T6,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T4,T6,T7
0	0	1	Covered	T4,T6,T7
0	0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T4,T6,T7
0	0	1	Covered	T4,T6,T7
0	0	0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1166373877	1995453	0	0
DstReqKnown_A	6109145	5236922	0	0
SrcAckBusyChk_A	1166373877	1968	0	0
SrcBusyKnown_A	1166373877	1164631351	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1995453	0	0
T4	135708	18722	0	0
T6	260047	2434	0	0
T7	513558	6768	0	0
T9	0	14121	0	0
T10	0	5601	0	0
T11	0	4849	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T29	0	1915	0	0
T33	0	11088	0	0
T45	0	5995	0	0
T47	0	4201	0	0
T48	362346	0	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T57	258306	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6109145	5236922	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1968	0	0
T4	135708	11	0	0
T6	260047	7	0	0
T7	513558	8	0	0
T9	0	8	0	0
T10	0	12	0	0
T11	0	3	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T29	0	1	0	0
T33	0	6	0	0
T45	0	13	0	0
T47	0	6	0	0
T48	362346	0	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T57	258306	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1164631351	0	0
T1	513276	512990	0	0
T2	110326	110228	0	0
T3	198545	197843	0	0
T5	201266	201207	0	0
T12	195243	195147	0	0
T13	164028	163961	0	0
T14	202183	202128	0	0
T15	110191	110121	0	0
T16	492251	492160	0	0
T17	103549	103449	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T4,T6,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T4,T6,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T4,T6,T7
0	0	1	Covered	T4,T6,T7
0	0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T4,T6,T7
0	0	1	Covered	T4,T6,T7
0	0	0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1166373877	1984772	0	0
DstReqKnown_A	6109145	5236922	0	0
SrcAckBusyChk_A	1166373877	1958	0	0
SrcBusyKnown_A	1166373877	1164631351	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1984772	0	0
T4	135708	18638	0	0
T6	260047	2840	0	0
T7	513558	6752	0	0
T9	0	14081	0	0
T10	0	5577	0	0
T11	0	4670	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T29	0	1905	0	0
T33	0	11028	0	0
T45	0	6108	0	0
T47	0	3882	0	0
T48	362346	0	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T57	258306	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6109145	5236922	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1958	0	0
T4	135708	11	0	0
T6	260047	7	0	0
T7	513558	8	0	0
T9	0	8	0	0
T10	0	12	0	0
T11	0	3	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T29	0	1	0	0
T33	0	6	0	0
T45	0	13	0	0
T47	0	6	0	0
T48	362346	0	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T57	258306	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1164631351	0	0
T1	513276	512990	0	0
T2	110326	110228	0	0
T3	198545	197843	0	0
T5	201266	201207	0	0
T12	195243	195147	0	0
T13	164028	163961	0	0
T14	202183	202128	0	0
T15	110191	110121	0	0
T16	492251	492160	0	0
T17	103549	103449	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T3,T4,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T3,T4,T6
1	1	Covered	T3,T4,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T3,T4,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T4,T6
1	1	Covered	T3,T4,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T3,T4,T6
0	0	1	Covered	T3,T4,T6
0	0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T3,T4,T6
0	0	1	Covered	T3,T4,T6
0	0	0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1166373877	2035413	0	0
DstReqKnown_A	6109145	5236922	0	0
SrcAckBusyChk_A	1166373877	2030	0	0
SrcBusyKnown_A	1166373877	1164631351	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	2035413	0	0
T3	198545	1418	0	0
T4	135708	18559	0	0
T6	260047	2906	0	0
T7	0	6736	0	0
T9	0	14024	0	0
T10	0	5553	0	0
T11	0	5146	0	0
T15	110191	0	0	0
T16	492251	0	0	0
T17	103549	0	0	0
T23	238399	0	0	0
T25	237750	0	0	0
T28	204416	0	0	0
T29	0	1933	0	0
T32	345456	0	0	0
T33	0	10970	0	0
T45	0	6131	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6109145	5236922	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	2030	0	0
T3	198545	1	0	0
T4	135708	11	0	0
T6	260047	7	0	0
T7	0	8	0	0
T9	0	8	0	0
T10	0	12	0	0
T11	0	3	0	0
T15	110191	0	0	0
T16	492251	0	0	0
T17	103549	0	0	0
T23	238399	0	0	0
T25	237750	0	0	0
T28	204416	0	0	0
T29	0	1	0	0
T32	345456	0	0	0
T33	0	6	0	0
T45	0	13	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1164631351	0	0
T1	513276	512990	0	0
T2	110326	110228	0	0
T3	198545	197843	0	0
T5	201266	201207	0	0
T12	195243	195147	0	0
T13	164028	163961	0	0
T14	202183	202128	0	0
T15	110191	110121	0	0
T16	492251	492160	0	0
T17	103549	103449	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T4,T6,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T4,T6,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T4,T6,T7
0	0	1	Covered	T4,T6,T7
0	0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T4,T6,T7
0	0	1	Covered	T4,T6,T7
0	0	0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1166373877	1985728	0	0
DstReqKnown_A	6109145	5236922	0	0
SrcAckBusyChk_A	1166373877	1985	0	0
SrcBusyKnown_A	1166373877	1164631351	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1985728	0	0
T4	135708	18495	0	0
T6	260047	2624	0	0
T7	513558	6720	0	0
T9	0	13957	0	0
T10	0	5529	0	0
T11	0	4987	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T29	0	1923	0	0
T33	0	10892	0	0
T45	0	5405	0	0
T47	0	4455	0	0
T48	362346	0	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T57	258306	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6109145	5236922	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1985	0	0
T4	135708	11	0	0
T6	260047	7	0	0
T7	513558	8	0	0
T9	0	8	0	0
T10	0	12	0	0
T11	0	3	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T29	0	1	0	0
T33	0	6	0	0
T45	0	13	0	0
T47	0	6	0	0
T48	362346	0	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T57	258306	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1164631351	0	0
T1	513276	512990	0	0
T2	110326	110228	0	0
T3	198545	197843	0	0
T5	201266	201207	0	0
T12	195243	195147	0	0
T13	164028	163961	0	0
T14	202183	202128	0	0
T15	110191	110121	0	0
T16	492251	492160	0	0
T17	103549	103449	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T4,T6,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T4,T6,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T4,T6,T7
0	0	1	Covered	T4,T6,T7
0	0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T4,T6,T7
0	0	1	Covered	T4,T6,T7
0	0	0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1166373877	1952808	0	0
DstReqKnown_A	6109145	5236922	0	0
SrcAckBusyChk_A	1166373877	1955	0	0
SrcBusyKnown_A	1166373877	1164631351	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1952808	0	0
T4	135708	18425	0	0
T6	260047	2511	0	0
T7	513558	6704	0	0
T9	0	13908	0	0
T10	0	5505	0	0
T11	0	4819	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T29	0	1913	0	0
T33	0	10854	0	0
T45	0	6477	0	0
T47	0	4145	0	0
T48	362346	0	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T57	258306	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6109145	5236922	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1955	0	0
T4	135708	11	0	0
T6	260047	7	0	0
T7	513558	8	0	0
T9	0	8	0	0
T10	0	12	0	0
T11	0	3	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T29	0	1	0	0
T33	0	6	0	0
T45	0	13	0	0
T47	0	6	0	0
T48	362346	0	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T57	258306	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1164631351	0	0
T1	513276	512990	0	0
T2	110326	110228	0	0
T3	198545	197843	0	0
T5	201266	201207	0	0
T12	195243	195147	0	0
T13	164028	163961	0	0
T14	202183	202128	0	0
T15	110191	110121	0	0
T16	492251	492160	0	0
T17	103549	103449	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T4,T6,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T4,T6,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T4,T6,T7
0	0	1	Covered	T4,T6,T7
0	0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T4,T6,T7
0	0	1	Covered	T4,T6,T7
0	0	0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1166373877	2007243	0	0
DstReqKnown_A	6109145	5236922	0	0
SrcAckBusyChk_A	1166373877	2013	0	0
SrcBusyKnown_A	1166373877	1164631351	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	2007243	0	0
T4	135708	18339	0	0
T6	260047	2783	0	0
T7	513558	6688	0	0
T9	0	13856	0	0
T10	0	5481	0	0
T11	0	4641	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T29	0	1903	0	0
T33	0	10786	0	0
T45	0	5957	0	0
T47	0	3813	0	0
T48	362346	0	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T57	258306	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6109145	5236922	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	2013	0	0
T4	135708	11	0	0
T6	260047	7	0	0
T7	513558	8	0	0
T9	0	8	0	0
T10	0	12	0	0
T11	0	3	0	0
T24	59788	0	0	0
T25	237750	0	0	0
T26	128275	0	0	0
T29	0	1	0	0
T33	0	6	0	0
T45	0	13	0	0
T47	0	6	0	0
T48	362346	0	0	0
T55	221254	0	0	0
T56	207267	0	0	0
T57	258306	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1164631351	0	0
T1	513276	512990	0	0
T2	110326	110228	0	0
T3	198545	197843	0	0
T5	201266	201207	0	0
T12	195243	195147	0	0
T13	164028	163961	0	0
T14	202183	202128	0	0
T15	110191	110121	0	0
T16	492251	492160	0	0
T17	103549	103449	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T8,T21,T22

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T8,T21,T22
1	1	Covered	T8,T21,T22

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T8,T21,T22
1	-	Covered	T8,T21,T22

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T8,T21,T22

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T21,T22
1	1	Covered	T8,T21,T22

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T8,T21,T22
0	0	1	Covered	T8,T21,T22
0	0	0	Covered	T1,T5,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T2
0	1	-	Covered	T8,T21,T22
0	0	1	Covered	T8,T21,T22
0	0	0	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1166373877	1236383	0	0
DstReqKnown_A	6109145	5236922	0	0
SrcAckBusyChk_A	1166373877	1152	0	0
SrcBusyKnown_A	1166373877	1164631351	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1236383	0	0
T8	57922	830	0	0
T9	102721	0	0	0
T10	418073	0	0	0
T11	593192	0	0	0
T21	0	1179	0	0
T22	0	3782	0	0
T29	369913	0	0	0
T36	0	166	0	0
T45	484680	0	0	0
T60	315554	0	0	0
T61	0	3454	0	0
T69	121047	0	0	0
T76	0	3494	0	0
T77	0	1719	0	0
T78	0	795	0	0
T79	0	269	0	0
T80	0	7190	0	0
T81	272186	0	0	0
T82	118968	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6109145	5236922	0	0
T1	2226	626	0	0
T2	534	134	0	0
T3	4462	981	0	0
T5	402	2	0	0
T12	402	2	0	0
T13	683	283	0	0
T14	1128	728	0	0
T15	423	23	0	0
T16	984	584	0	0
T17	422	22	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1152	0	0
T8	57922	2	0	0
T9	102721	0	0	0
T10	418073	0	0	0
T11	593192	0	0	0
T21	0	4	0	0
T22	0	2	0	0
T29	369913	0	0	0
T36	0	2	0	0
T45	484680	0	0	0
T60	315554	0	0	0
T61	0	2	0	0
T69	121047	0	0	0
T76	0	2	0	0
T77	0	2	0	0
T78	0	2	0	0
T79	0	2	0	0
T80	0	4	0	0
T81	272186	0	0	0
T82	118968	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1166373877	1164631351	0	0
T1	513276	512990	0	0
T2	110326	110228	0	0
T3	198545	197843	0	0
T5	201266	201207	0	0
T12	195243	195147	0	0
T13	164028	163961	0	0
T14	202183	202128	0	0
T15	110191	110121	0	0
T16	492251	492160	0	0
T17	103549	103449	0	0