Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
90.24	90.24	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	90.24	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.24	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	8	54	87.10

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	8	23	74.19	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1947

1

T2

24

T3

23

T6

7

auto[1]

710

1

T2

8

T6

1

T8

2

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1912

1

T2

24

T3

10

T6

7

auto[1]

745

1

T2

8

T3

13

T6

1

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1933

1

T2

26

T3

13

T6

8

auto[1]

724

1

T2

6

T3

10

T8

3

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2075

1

T2

32

T3

22

T6

7

auto[1]

582

1

T3

1

T6

1

T8

2

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2440

1

T2

32

T3

23

T6

8

auto[1]

217

1

T8

2

T10

2

T57

3

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2403

1

T2

26

T3

23

T6

8

auto[1]

254

1

T2

6

T8

2

T10

5

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2476

1

T2

32

T3

23

T6

5

auto[1]

181

1

T6

3

T10

7

T37

4

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2403

1

T2

18

T3

23

T6

8

auto[1]

254

1

T2

14

T8

4

T10

3

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2440

1

T2

18

T3

23

T6

7

auto[1]

217

1

T2

14

T6

1

T8

2

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1945

1

T2

32

T3

22

T6

6

auto[1]

712

1

T3

1

T6

2

T8

4

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	8	23	74.19	8
Automatically Generated Cross Bins	31	8	23	74.19	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	*	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

967

1

T3

23

T34

14

T35

12

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

80

1

T229

4

T345

1

T351

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

73

1

T93

1

T250

3

T342

30

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

19

1

T228

1

T229

2

T300

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

75

1

T8

2

T97

1

T301

12

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

35

1

T8

2

T57

3

T250

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

35

1

T2

8

T57

4

T344

12

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

4

1

T358

2

T359

2

-

-

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

76

1

T6

2

T10

3

T37

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

21

1

T10

2

T82

5

T237

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

15

1

T6

1

T82

10

T360

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2

1

T361

2

-

-

-

-

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

17

1

T93

1

T229

4

T250

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

84

1

T37

2

T82

4

T228

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

27

1

T37

1

T300

8

T301

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

28

1

T8

2

T342

11

T300

9

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

1

1

T345

1

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

44

1

T10

3

T342

8

T300

7

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

3

1

T353

3

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

7

1

T2

6

T345

1

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

21

1

T10

2

T228

4

T351

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

9

1

T362

2

T363

1

T364

6

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

2

1

T365

2

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

112

1

T108

8

T342

11

T153

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

185

1

T6

2

T8

2

T228

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

52

1

T10

3

T34

4

T234

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

64

1

T10

2

T228

1

T239

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

29

1

T10

2

T250

2

T366

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

53

1

T34

6

T107

3

T239

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

35

1

T228

6

T180

3

T234

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

82

1

T2

6

T3

10

T39

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

77

1

T34

3

T39

1

T342

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

70

1

T37

1

T82

4

T367

10

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

35

1

T238

2

T251

3

T122

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

79

1

T37

2

T342

15

T301

8

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

31

1

T8

2

T35

2

T180

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

37

1

T300

8

T235

3

T233

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

20

1

T251

2

T290

2

T368

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

146

1

T3

12

T35

10

T250

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

83

1

T2

8

T36

6

T57

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

67

1

T8

1

T242

10

T237

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

41

1

T10

3

T37

4

T240

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

74

1

T82

5

T234

4

T300

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

24

1

T6

1

T229

8

T102

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

25

1

T3

1

T82

5

T229

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

4

1

T180

2

T369

2

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

97

1

T36

5

T239

2

T342

15

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

47

1

T34

1

T39

1

T122

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

23

1

T8

1

T57

3

T366

5

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

7

1

T97

1

T346

2

T369

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

27

1

T109

2

T230

2

T343

8

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

4

1

T36

2

T313

1

T370

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

8

1

T345

1

T122

4

T371

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

7

1

T180

2

T369

1

T341

2

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded