Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1245

1

T4

30

T75

11

T76

11

auto[1]

1273

1

T4

30

T75

9

T76

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

608

1

T4

15

T75

4

T76

6

from_0to1

593

1

T4

15

T75

5

T76

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1236

1

T4

30

T75

10

T76

12

auto[1]

1282

1

T4

30

T75

10

T76

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1287

1

T4

34

T75

8

T76

13

auto[1]

1231

1

T4

26

T75

12

T76

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

79

1

T4

4

T76

1

T39

2

auto[0]

from_1to0

auto[0]

auto[1]

82

1

T4

2

T76

1

T78

1

auto[0]

from_1to0

auto[1]

auto[0]

71

1

T4

1

T76

1

T78

1

auto[0]

from_1to0

auto[1]

auto[1]

70

1

T4

2

T75

1

T78

1

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T4

3

T76

1

T78

1

auto[0]

from_0to1

auto[0]

auto[1]

70

1

T75

1

T76

1

T78

1

auto[0]

from_0to1

auto[1]

auto[0]

93

1

T4

3

T75

1

T78

1

auto[0]

from_0to1

auto[1]

auto[1]

77

1

T4

1

T75

1

T91

1

auto[1]

from_1to0

auto[0]

auto[0]

79

1

T4

1

T76

2

T81

1

auto[1]

from_1to0

auto[0]

auto[1]

72

1

T4

1

T75

2

T76

1

auto[1]

from_1to0

auto[1]

auto[0]

76

1

T4

3

T78

2

T39

1

auto[1]

from_1to0

auto[1]

auto[1]

79

1

T4

1

T75

1

T78

1

auto[1]

from_0to1

auto[0]

auto[0]

70

1

T4

1

T76

2

T69

2

auto[1]

from_0to1

auto[0]

auto[1]

67

1

T4

3

T75

1

T39

1

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T4

2

T76

1

T39

2

auto[1]

from_0to1

auto[1]

auto[1]

77

1

T4

2

T75

1

T76

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1230

1

T4

35

T75

10

T76

7

auto[1]

1288

1

T4

25

T75

10

T76

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

592

1

T4

12

T75

5

T76

5

from_0to1

588

1

T4

13

T75

5

T76

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1251

1

T4

34

T75

11

T76

9

auto[1]

1267

1

T4

26

T75

9

T76

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1225

1

T4

30

T75

13

T76

7

auto[1]

1293

1

T4

30

T75

7

T76

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

68

1

T4

2

T75

1

T78

1

auto[0]

from_1to0

auto[0]

auto[1]

72

1

T4

2

T76

1

T81

2

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T4

3

T75

1

T39

1

auto[0]

from_1to0

auto[1]

auto[1]

82

1

T76

1

T39

1

T81

3

auto[0]

from_0to1

auto[0]

auto[0]

74

1

T4

2

T75

1

T387

1

auto[0]

from_0to1

auto[0]

auto[1]

78

1

T4

1

T76

1

T78

1

auto[0]

from_0to1

auto[1]

auto[0]

78

1

T4

3

T75

1

T76

1

auto[0]

from_0to1

auto[1]

auto[1]

69

1

T4

2

T78

1

T69

1

auto[1]

from_1to0

auto[0]

auto[0]

76

1

T4

4

T78

1

T69

2

auto[1]

from_1to0

auto[0]

auto[1]

72

1

T4

1

T75

2

T81

1

auto[1]

from_1to0

auto[1]

auto[0]

74

1

T78

1

T39

1

T69

1

auto[1]

from_1to0

auto[1]

auto[1]

82

1

T75

1

T76

3

T95

2

auto[1]

from_0to1

auto[0]

auto[0]

69

1

T4

1

T75

1

T81

2

auto[1]

from_0to1

auto[0]

auto[1]

76

1

T4

2

T75

1

T39

2

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T76

1

T91

2

T95

1

auto[1]

from_0to1

auto[1]

auto[1]

79

1

T4

2

T75

1

T76

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1280

1

T4

26

T75

8

T76

13

auto[1]

1238

1

T4

34

T75

12

T76

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

607

1

T4

13

T75

5

T76

8

from_0to1

619

1

T4

13

T75

6

T76

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1307

1

T4

37

T75

6

T76

12

auto[1]

1211

1

T4

23

T75

14

T76

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1237

1

T4

25

T75

12

T76

9

auto[1]

1281

1

T4

35

T75

8

T76

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

83

1

T4

2

T75

2

T76

1

auto[0]

from_1to0

auto[0]

auto[1]

79

1

T4

1

T76

2

T81

3

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T4

1

T75

1

T76

1

auto[0]

from_1to0

auto[1]

auto[1]

75

1

T4

1

T76

3

T78

1

auto[0]

from_0to1

auto[0]

auto[0]

66

1

T75

1

T76

2

T78

1

auto[0]

from_0to1

auto[0]

auto[1]

101

1

T4

5

T78

2

T81

2

auto[0]

from_0to1

auto[1]

auto[0]

71

1

T75

1

T76

1

T69

1

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T78

1

T81

3

T95

1

auto[1]

from_1to0

auto[0]

auto[0]

74

1

T4

1

T76

1

T78

1

auto[1]

from_1to0

auto[0]

auto[1]

76

1

T4

5

T69

1

T81

2

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T4

1

T39

2

T91

2

auto[1]

from_1to0

auto[1]

auto[1]

85

1

T4

1

T75

2

T78

2

auto[1]

from_0to1

auto[0]

auto[0]

90

1

T4

2

T75

1

T76

2

auto[1]

from_0to1

auto[0]

auto[1]

74

1

T4

3

T81

2

T91

1

auto[1]

from_0to1

auto[1]

auto[0]

74

1

T4

3

T75

2

T76

1

auto[1]

from_0to1

auto[1]

auto[1]

77

1

T75

1

T76

1

T39

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1244

1

T4

34

T75

9

T76

12

auto[1]

1274

1

T4

26

T75

11

T76

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

624

1

T4

15

T75

4

T76

5

from_0to1

605

1

T4

15

T75

3

T76

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1259

1

T4

30

T75

4

T76

9

auto[1]

1259

1

T4

30

T75

16

T76

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1285

1

T4

35

T75

10

T76

10

auto[1]

1233

1

T4

25

T75

10

T76

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

84

1

T4

5

T76

1

T69

1

auto[0]

from_1to0

auto[0]

auto[1]

83

1

T4

2

T78

1

T39

2

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T4

1

T75

1

T76

1

auto[0]

from_1to0

auto[1]

auto[1]

73

1

T4

1

T75

1

T78

1

auto[0]

from_0to1

auto[0]

auto[0]

85

1

T4

2

T76

1

T39

1

auto[0]

from_0to1

auto[0]

auto[1]

74

1

T4

1

T76

2

T81

2

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T4

3

T78

2

T95

1

auto[0]

from_0to1

auto[1]

auto[1]

83

1

T4

3

T75

2

T39

1

auto[1]

from_1to0

auto[0]

auto[0]

69

1

T4

1

T81

1

T95

1

auto[1]

from_1to0

auto[0]

auto[1]

84

1

T4

2

T75

1

T76

1

auto[1]

from_1to0

auto[1]

auto[0]

84

1

T4

1

T75

1

T76

1

auto[1]

from_1to0

auto[1]

auto[1]

83

1

T4

2

T76

1

T39

1

auto[1]

from_0to1

auto[0]

auto[0]

79

1

T4

2

T76

1

T91

1

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T4

1

T69

1

T95

1

auto[1]

from_0to1

auto[1]

auto[0]

95

1

T4

3

T75

1

T39

1

auto[1]

from_0to1

auto[1]

auto[1]

61

1

T76

1

T78

1

T39

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1237

1

T4

31

T75

8

T76

13

auto[1]

1281

1

T4

29

T75

12

T76

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

626

1

T4

15

T75

4

T76

4

from_0to1

618

1

T4

15

T75

5

T76

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1268

1

T4

29

T75

8

T76

13

auto[1]

1250

1

T4

31

T75

12

T76

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1242

1

T4

29

T75

13

T76

14

auto[1]

1276

1

T4

31

T75

7

T76

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

84

1

T4

3

T76

2

T69

1

auto[0]

from_1to0

auto[0]

auto[1]

69

1

T4

2

T78

1

T39

1

auto[0]

from_1to0

auto[1]

auto[0]

67

1

T75

1

T76

1

T78

1

auto[0]

from_1to0

auto[1]

auto[1]

89

1

T4

3

T76

1

T81

2

auto[0]

from_0to1

auto[0]

auto[0]

79

1

T4

2

T76

1

T78

1

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T4

2

T75

1

T76

1

auto[0]

from_0to1

auto[1]

auto[0]

71

1

T75

1

T81

2

T91

1

auto[0]

from_0to1

auto[1]

auto[1]

80

1

T4

1

T75

1

T81

2

auto[1]

from_1to0

auto[0]

auto[0]

83

1

T4

2

T75

1

T78

1

auto[1]

from_1to0

auto[0]

auto[1]

81

1

T4

1

T39

1

T69

2

auto[1]

from_1to0

auto[1]

auto[0]

73

1

T4

2

T75

1

T78

1

auto[1]

from_1to0

auto[1]

auto[1]

80

1

T4

2

T75

1

T69

1

auto[1]

from_0to1

auto[0]

auto[0]

74

1

T4

2

T39

1

T69

1

auto[1]

from_0to1

auto[0]

auto[1]

93

1

T4

1

T76

1

T78

2

auto[1]

from_0to1

auto[1]

auto[0]

77

1

T4

7

T75

2

T69

1

auto[1]

from_0to1

auto[1]

auto[1]

76

1

T81

1

T95

2

T388

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1266

1

T4

30

T75

14

T76

8

auto[1]

1252

1

T4

30

T75

6

T76

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

606

1

T4

15

T75

5

T76

4

from_0to1

604

1

T4

15

T75

5

T76

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1267

1

T4

38

T75

8

T76

10

auto[1]

1251

1

T4

22

T75

12

T76

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1243

1

T4

26

T75

10

T76

11

auto[1]

1275

1

T4

34

T75

10

T76

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

83

1

T4

3

T75

1

T76

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T78

1

T39

2

T69

1

auto[0]

from_1to0

auto[1]

auto[0]

75

1

T4

3

T75

1

T78

1

auto[0]

from_1to0

auto[1]

auto[1]

85

1

T4

1

T75

1

T76

1

auto[0]

from_0to1

auto[0]

auto[0]

74

1

T4

5

T39

1

T95

2

auto[0]

from_0to1

auto[0]

auto[1]

82

1

T4

2

T78

1

T81

2

auto[0]

from_0to1

auto[1]

auto[0]

55

1

T76

2

T69

1

T81

1

auto[0]

from_0to1

auto[1]

auto[1]

85

1

T4

4

T75

3

T76

1

auto[1]

from_1to0

auto[0]

auto[0]

71

1

T4

1

T75

1

T78

1

auto[1]

from_1to0

auto[0]

auto[1]

85

1

T4

4

T39

1

T69

1

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T4

1

T75

1

T39

1

auto[1]

from_1to0

auto[1]

auto[1]

75

1

T4

2

T76

2

T81

3

auto[1]

from_0to1

auto[0]

auto[0]

86

1

T39

1

T69

2

T81

4

auto[1]

from_0to1

auto[0]

auto[1]

71

1

T4

3

T78

1

T81

1

auto[1]

from_0to1

auto[1]

auto[0]

73

1

T4

1

T75

1

T76

1

auto[1]

from_0to1

auto[1]

auto[1]

78

1

T75

1

T76

1

T78

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1262

1

T4

30

T75

11

T76

10

auto[1]

1256

1

T4

30

T75

9

T76

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

593

1

T4

16

T75

7

T76

5

from_0to1

593

1

T4

16

T75

6

T76

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1298

1

T4

29

T75

9

T76

11

auto[1]

1220

1

T4

31

T75

11

T76

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1269

1

T4

39

T75

13

T76

7

auto[1]

1249

1

T4

21

T75

7

T76

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

62

1

T4

1

T75

1

T76

1

auto[0]

from_1to0

auto[0]

auto[1]

65

1

T4

3

T75

1

T69

1

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T4

2

T75

1

T81

2

auto[0]

from_1to0

auto[1]

auto[1]

85

1

T4

1

T75

1

T76

2

auto[0]

from_0to1

auto[0]

auto[0]

91

1

T4

3

T75

1

T76

1

auto[0]

from_0to1

auto[0]

auto[1]

85

1

T4

2

T78

1

T81

4

auto[0]

from_0to1

auto[1]

auto[0]

79

1

T4

4

T75

2

T78

1

auto[0]

from_0to1

auto[1]

auto[1]

55

1

T76

1

T388

1

T255

1

auto[1]

from_1to0

auto[0]

auto[0]

80

1

T4

3

T75

2

T76

1

auto[1]

from_1to0

auto[0]

auto[1]

85

1

T4

2

T78

1

T39

1

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T4

2

T75

1

T78

1

auto[1]

from_1to0

auto[1]

auto[1]

85

1

T4

2

T76

1

T78

1

auto[1]

from_0to1

auto[0]

auto[0]

77

1

T4

3

T69

2

T91

1

auto[1]

from_0to1

auto[0]

auto[1]

59

1

T4

1

T75

1

T76

2

auto[1]

from_0to1

auto[1]

auto[0]

79

1

T4

3

T75

1

T39

2

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T75

1

T78

1

T39

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1272

1

T4

37

T75

11

T76

9

auto[1]

1246

1

T4

23

T75

9

T76

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

601

1

T4

16

T75

3

T76

4

from_0to1

609

1

T4

15

T75

3

T76

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1190

1

T4

27

T75

10

T76

11

auto[1]

1328

1

T4

33

T75

10

T76

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1221

1

T4

36

T75

10

T76

9

auto[1]

1297

1

T4

24

T75

10

T76

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

90

1

T4

4

T76

1

T39

1

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T4

2

T76

1

T39

1

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T4

1

T78

2

T81

1

auto[0]

from_1to0

auto[1]

auto[1]

92

1

T4

1

T76

1

T39

1

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T4

4

T75

1

T81

2

auto[0]

from_0to1

auto[0]

auto[1]

86

1

T4

4

T39

1

T69

1

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T4

2

T75

2

T76

1

auto[0]

from_0to1

auto[1]

auto[1]

86

1

T4

2

T78

2

T39

2

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T4

3

T75

2

T76

1

auto[1]

from_1to0

auto[0]

auto[1]

75

1

T75

1

T78

1

T81

1

auto[1]

from_1to0

auto[1]

auto[0]

69

1

T4

2

T39

1

T69

1

auto[1]

from_1to0

auto[1]

auto[1]

77

1

T4

3

T39

1

T306

2

auto[1]

from_0to1

auto[0]

auto[0]

55

1

T4

1

T76

2

T91

1

auto[1]

from_0to1

auto[0]

auto[1]

72

1

T78

1

T39

1

T95

2

auto[1]

from_0to1

auto[1]

auto[0]

84

1

T76

1

T69

1

T81

3

auto[1]

from_0to1

auto[1]

auto[1]

92

1

T4

2

T76

1

T78

1