Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	160074	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

119597

1

T4

168

T1

7

T5

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	143940	1			T4	190		T1	10		T5	4
values[0x0]	67221	1			T4	125		T1	3		T14	230
values[0x1]	68510	1			T4	117		T1	2		T14	193

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	129563	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

150108

1

T4

212

T1

7

T5

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1421	1			T2	5		T6	4		T8	4
valid_sources[0x01]	1123	1			T14	5		T2	8		T3	1
valid_sources[0x02]	1078	1			T14	5		T2	10		T3	3
valid_sources[0x03]	1051	1			T14	5		T6	2		T8	4
valid_sources[0x04]	1164	1			T14	1		T2	1		T3	2
valid_sources[0x05]	817	1			T14	10		T2	1		T6	3
valid_sources[0x06]	890	1			T2	1		T3	1		T6	3
valid_sources[0x07]	867	1			T14	3		T2	3		T3	7
valid_sources[0x08]	1018	1			T2	4		T3	3		T6	2
valid_sources[0x09]	1026	1			T2	7		T6	1		T8	3
valid_sources[0x0a]	1977	1			T2	3		T6	2		T8	1
valid_sources[0x0b]	769	1			T2	1		T3	1		T6	1
valid_sources[0x0c]	1077	1			T14	4		T2	5		T3	5
valid_sources[0x0d]	1114	1			T2	4		T3	5		T6	2
valid_sources[0x0e]	1762	1			T14	4		T2	3		T6	3
valid_sources[0x0f]	809	1			T3	6		T6	3		T11	2
valid_sources[0x10]	834	1			T14	1		T2	2		T6	4
valid_sources[0x11]	1408	1			T2	2		T3	1		T6	3
valid_sources[0x12]	1019	1			T14	6		T2	1		T3	1
valid_sources[0x13]	1139	1			T3	1		T6	3		T8	3
valid_sources[0x14]	1002	1			T6	1		T8	5		T10	34
valid_sources[0x15]	945	1			T14	6		T2	12		T6	4
valid_sources[0x16]	1085	1			T14	1		T2	3		T3	7
valid_sources[0x17]	1580	1			T2	2		T6	4		T8	4
valid_sources[0x18]	1125	1			T14	1		T2	5		T6	3
valid_sources[0x19]	1814	1			T14	1		T2	1		T6	2
valid_sources[0x1a]	918	1			T2	3		T6	3		T8	7
valid_sources[0x1b]	2134	1			T14	1		T3	1		T6	2
valid_sources[0x1c]	1070	1			T2	10		T6	5		T8	2
valid_sources[0x1d]	901	1			T14	2		T2	3		T6	4
valid_sources[0x1e]	1129	1			T3	2		T6	4		T8	2
valid_sources[0x1f]	846	1			T14	2		T2	5		T3	3
valid_sources[0x20]	935	1			T1	3		T14	1		T2	3
valid_sources[0x21]	935	1			T14	3		T6	6		T8	4
valid_sources[0x22]	1395	1			T14	9		T2	8		T3	1
valid_sources[0x23]	912	1			T2	3		T3	12		T6	1
valid_sources[0x24]	1065	1			T2	1		T6	1		T7	1
valid_sources[0x25]	943	1			T2	3		T3	7		T6	2
valid_sources[0x26]	1604	1			T2	7		T6	1		T8	5
valid_sources[0x27]	893	1			T2	5		T3	5		T6	1
valid_sources[0x28]	883	1			T14	3		T2	8		T3	3
valid_sources[0x29]	802	1			T2	1		T6	3		T8	7
valid_sources[0x2a]	1489	1			T2	6		T3	4		T6	4
valid_sources[0x2b]	1465	1			T3	1		T6	4		T8	2
valid_sources[0x2c]	2031	1			T14	4		T2	3		T3	2
valid_sources[0x2d]	818	1			T5	1		T3	1		T6	2
valid_sources[0x2e]	824	1			T2	4		T6	2		T8	2
valid_sources[0x2f]	1080	1			T14	2		T6	5		T7	2
valid_sources[0x30]	2258	1			T2	1		T6	6		T8	4
valid_sources[0x31]	931	1			T14	5		T2	1		T3	6
valid_sources[0x32]	1257	1			T2	5		T3	2		T6	3
valid_sources[0x33]	1353	1			T2	3		T6	8		T8	6
valid_sources[0x34]	1890	1			T14	2		T2	2		T6	2
valid_sources[0x35]	1307	1			T14	2		T2	9		T6	2
valid_sources[0x36]	884	1			T14	1		T2	8		T6	1
valid_sources[0x37]	904	1			T2	1		T6	3		T8	4
valid_sources[0x38]	1004	1			T14	3		T2	5		T6	2
valid_sources[0x39]	1443	1			T14	11		T2	3		T6	2
valid_sources[0x3a]	982	1			T2	1		T3	2		T6	2
valid_sources[0x3b]	1008	1			T6	4		T8	2		T11	3
valid_sources[0x3c]	802	1			T2	2		T6	7		T8	6
valid_sources[0x3d]	985	1			T2	5		T3	3		T6	2
valid_sources[0x3e]	1072	1			T2	3		T3	2		T6	2
valid_sources[0x3f]	902	1			T2	4		T3	4		T6	5
valid_sources[0x40]	1190	1			T14	1		T2	3		T3	4
valid_sources[0x41]	1010	1			T2	9		T15	18		T6	4
valid_sources[0x42]	934	1			T2	10		T3	5		T6	2
valid_sources[0x43]	977	1			T2	6		T6	4		T8	3
valid_sources[0x44]	909	1			T14	8		T2	2		T3	3
valid_sources[0x45]	1076	1			T6	4		T7	1		T8	3
valid_sources[0x46]	706	1			T14	1		T2	6		T3	4
valid_sources[0x47]	1258	1			T14	4		T2	1		T6	3
valid_sources[0x48]	1063	1			T14	8		T2	5		T6	4
valid_sources[0x49]	1027	1			T14	1		T2	4		T6	1
valid_sources[0x4a]	857	1			T14	4		T2	4		T6	4
valid_sources[0x4b]	778	1			T2	4		T6	6		T7	2
valid_sources[0x4c]	763	1			T14	1		T2	1		T6	1
valid_sources[0x4d]	1864	1			T2	3		T6	1		T8	3
valid_sources[0x4e]	725	1			T14	4		T2	6		T3	3
valid_sources[0x4f]	1537	1			T14	3		T2	2		T3	2
valid_sources[0x50]	827	1			T14	1		T3	1		T6	4
valid_sources[0x51]	883	1			T2	5		T3	1		T6	1
valid_sources[0x52]	1030	1			T14	3		T2	1		T3	10
valid_sources[0x53]	891	1			T2	2		T6	3		T28	1
valid_sources[0x54]	823	1			T14	3		T2	1		T6	4
valid_sources[0x55]	1086	1			T2	5		T3	12		T6	1
valid_sources[0x56]	829	1			T2	13		T3	4		T6	2
valid_sources[0x57]	1158	1			T14	1		T2	2		T3	1
valid_sources[0x58]	797	1			T14	2		T2	5		T6	4
valid_sources[0x59]	832	1			T14	2		T2	5		T3	9
valid_sources[0x5a]	764	1			T3	6		T6	3		T8	3
valid_sources[0x5b]	917	1			T1	1		T2	4		T6	2
valid_sources[0x5c]	948	1			T2	3		T3	2		T6	5
valid_sources[0x5d]	967	1			T1	1		T2	4		T6	4
valid_sources[0x5e]	1167	1			T14	3		T2	8		T3	3
valid_sources[0x5f]	1091	1			T2	6		T3	1		T6	1
valid_sources[0x60]	1089	1			T14	1		T6	5		T54	1
valid_sources[0x61]	827	1			T14	4		T3	1		T6	2
valid_sources[0x62]	706	1			T14	1		T2	3		T6	2
valid_sources[0x63]	1077	1			T14	1		T3	1		T6	6
valid_sources[0x64]	1004	1			T13	2		T14	3		T2	1
valid_sources[0x65]	1064	1			T2	9		T6	4		T8	2
valid_sources[0x66]	816	1			T1	1		T3	6		T6	2
valid_sources[0x67]	1618	1			T14	1		T6	7		T8	6
valid_sources[0x68]	923	1			T2	1		T3	3		T6	2
valid_sources[0x69]	932	1			T2	2		T6	6		T8	4
valid_sources[0x6a]	812	1			T1	1		T2	3		T3	3
valid_sources[0x6b]	1215	1			T2	2		T6	3		T8	5
valid_sources[0x6c]	1776	1			T2	7		T3	1		T6	3
valid_sources[0x6d]	846	1			T2	3		T6	4		T8	2
valid_sources[0x6e]	938	1			T14	3		T2	7		T6	5
valid_sources[0x6f]	978	1			T14	10		T2	7		T3	5
valid_sources[0x70]	990	1			T2	2		T3	3		T6	4
valid_sources[0x71]	1154	1			T1	1		T14	5		T2	6
valid_sources[0x72]	1093	1			T1	1		T14	1		T2	7
valid_sources[0x73]	870	1			T14	8		T2	3		T3	3
valid_sources[0x74]	1535	1			T2	2		T3	4		T6	3
valid_sources[0x75]	1703	1			T1	2		T14	5		T2	4
valid_sources[0x76]	820	1			T14	5		T2	1		T3	1
valid_sources[0x77]	886	1			T14	2		T2	3		T6	4
valid_sources[0x78]	2248	1			T2	7		T6	4		T8	6
valid_sources[0x79]	868	1			T14	3		T2	5		T3	7
valid_sources[0x7a]	1589	1			T2	4		T3	6		T6	3
valid_sources[0x7b]	1329	1			T14	1		T2	4		T6	4
valid_sources[0x7c]	1253	1			T14	1		T2	2		T3	2
valid_sources[0x7d]	900	1			T2	8		T6	2		T8	2
valid_sources[0x7e]	1058	1			T2	1		T6	4		T8	4
valid_sources[0x7f]	1348	1			T2	3		T3	7		T6	1
valid_sources[0x80]	878	1			T2	10		T3	1		T6	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

64449

1

T4

101

T1

6

T5

1

values[0x0]

all_enables

biggest_size

32449

1

T4

46

T1

1

T14

77

values[0x1]

all_enables

biggest_size

22699

1

T4

21

T14

26

T2

71