Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T27,T12,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T27,T12,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T27,T12,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T12,T46
1	0	Covered	T4,T1,T13
1	1	Covered	T27,T12,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T12,T46
0	1	Covered	T96
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T27,T12,T46
0	1	Covered	T27,T12,T46
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T27,T12,T46
1	-	Covered	T27,T12,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T27,T12,T46
DetectSt	168	Covered	T27,T12,T46
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T27,T12,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T27,T12,T46
DebounceSt->IdleSt	163	Covered	T27,T105,T135
DetectSt->IdleSt	186	Covered	T96
DetectSt->StableSt	191	Covered	T27,T12,T46
IdleSt->DebounceSt	148	Covered	T27,T12,T46
StableSt->IdleSt	206	Covered	T27,T12,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T27,T12,T46
0	1	Covered	T27,T12,T46
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T12,T46
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T27,T12,T46
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T56
DebounceSt	-	0	1	1	-	-	-	Covered	T27,T12,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T27,T105,T135
DebounceSt	-	0	0	-	-	-	-	Covered	T27,T12,T46
DetectSt	-	-	-	-	1	-	-	Covered	T96
DetectSt	-	-	-	-	0	1	-	Covered	T27,T12,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T27,T12,T46
StableSt	-	-	-	-	-	-	0	Covered	T27,T12,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10081786	308	0	0
CntIncr_A	10081786	281108	0	0
CntNoWrap_A	10081786	9352643	0	0
DetectStDropOut_A	10081786	2	0	0
DetectedOut_A	10081786	938	0	0
DetectedPulseOut_A	10081786	143	0	0
DisabledIdleSt_A	10081786	9065018	0	0
DisabledNoDetection_A	10081786	9067569	0	0
EnterDebounceSt_A	10081786	165	0	0
EnterDetectSt_A	10081786	145	0	0
EnterStableSt_A	10081786	143	0	0
PulseIsPulse_A	10081786	143	0	0
StayInStableSt	10081786	795	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	10081786	7390	0	0
gen_low_level_sva.LowLevelEvent_A	10081786	9355557	0	0
gen_not_sticky_sva.StableStDropOut_A	10081786	142	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	308	0	0
T7	810	0	0	0
T8	18502	0	0	0
T9	1492	0	0	0
T10	14723	0	0	0
T11	186745	0	0	0
T12	0	6	0	0
T25	494	0	0	0
T27	20242	5	0	0
T28	676	0	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	4	0	0
T49	0	4	0	0
T50	0	2	0	0
T51	0	6	0	0
T52	0	4	0	0
T53	403	0	0	0
T54	798	0	0	0
T105	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	281108	0	0
T7	810	0	0	0
T8	18502	0	0	0
T9	1492	0	0	0
T10	14723	0	0	0
T11	186745	0	0	0
T12	0	177	0	0
T25	494	0	0	0
T27	20242	17048	0	0
T28	676	0	0	0
T46	0	99	0	0
T47	0	97	0	0
T48	0	100	0	0
T49	0	125	0	0
T50	0	34	0	0
T51	0	232	0	0
T52	0	176	0	0
T53	403	0	0	0
T54	798	0	0	0
T105	0	19	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9352643	0	0
T1	540	139	0	0
T2	17755	17322	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	2	0	0
T96	40533	2	0	0
T122	20153	0	0	0
T123	503	0	0	0
T124	32669	0	0	0
T125	523	0	0	0
T126	502	0	0	0
T127	526	0	0	0
T128	501	0	0	0
T129	630	0	0	0
T130	620	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	938	0	0
T7	810	0	0	0
T8	18502	0	0	0
T9	1492	0	0	0
T10	14723	0	0	0
T11	186745	0	0	0
T12	0	17	0	0
T25	494	0	0	0
T27	20242	13	0	0
T28	676	0	0	0
T46	0	11	0	0
T47	0	11	0	0
T48	0	18	0	0
T49	0	11	0	0
T50	0	3	0	0
T51	0	21	0	0
T52	0	15	0	0
T53	403	0	0	0
T54	798	0	0	0
T131	0	11	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	143	0	0
T7	810	0	0	0
T8	18502	0	0	0
T9	1492	0	0	0
T10	14723	0	0	0
T11	186745	0	0	0
T12	0	3	0	0
T25	494	0	0	0
T27	20242	2	0	0
T28	676	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	3	0	0
T52	0	2	0	0
T53	403	0	0	0
T54	798	0	0	0
T131	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9065018	0	0
T1	540	139	0	0
T2	17755	17322	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9067569	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	165	0	0
T7	810	0	0	0
T8	18502	0	0	0
T9	1492	0	0	0
T10	14723	0	0	0
T11	186745	0	0	0
T12	0	3	0	0
T25	494	0	0	0
T27	20242	3	0	0
T28	676	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	3	0	0
T52	0	2	0	0
T53	403	0	0	0
T54	798	0	0	0
T105	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	145	0	0
T7	810	0	0	0
T8	18502	0	0	0
T9	1492	0	0	0
T10	14723	0	0	0
T11	186745	0	0	0
T12	0	3	0	0
T25	494	0	0	0
T27	20242	2	0	0
T28	676	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	3	0	0
T52	0	2	0	0
T53	403	0	0	0
T54	798	0	0	0
T131	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	143	0	0
T7	810	0	0	0
T8	18502	0	0	0
T9	1492	0	0	0
T10	14723	0	0	0
T11	186745	0	0	0
T12	0	3	0	0
T25	494	0	0	0
T27	20242	2	0	0
T28	676	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	3	0	0
T52	0	2	0	0
T53	403	0	0	0
T54	798	0	0	0
T131	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	143	0	0
T7	810	0	0	0
T8	18502	0	0	0
T9	1492	0	0	0
T10	14723	0	0	0
T11	186745	0	0	0
T12	0	3	0	0
T25	494	0	0	0
T27	20242	2	0	0
T28	676	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	3	0	0
T52	0	2	0	0
T53	403	0	0	0
T54	798	0	0	0
T131	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	795	0	0
T7	810	0	0	0
T8	18502	0	0	0
T9	1492	0	0	0
T10	14723	0	0	0
T11	186745	0	0	0
T12	0	14	0	0
T25	494	0	0	0
T27	20242	11	0	0
T28	676	0	0	0
T46	0	10	0	0
T47	0	10	0	0
T48	0	16	0	0
T49	0	9	0	0
T50	0	2	0	0
T51	0	18	0	0
T52	0	13	0	0
T53	403	0	0	0
T54	798	0	0	0
T131	0	9	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	7390	0	0
T1	540	1	0	0
T2	17755	29	0	0
T3	9207	13	0	0
T4	2426	19	0	0
T5	405	0	0	0
T6	9065	26	0	0
T13	423	3	0	0
T14	5416	23	0	0
T15	418	2	0	0
T16	425	2	0	0
T17	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9355557	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	142	0	0
T7	810	0	0	0
T8	18502	0	0	0
T9	1492	0	0	0
T10	14723	0	0	0
T11	186745	0	0	0
T12	0	3	0	0
T25	494	0	0	0
T27	20242	2	0	0
T28	676	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	3	0	0
T52	0	2	0	0
T53	403	0	0	0
T54	798	0	0	0
T131	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T22,T23,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T22,T23,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T22,T23,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Covered	T4,T1,T13
1	1	Covered	T22,T23,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T24
0	1	Covered	T24,T89,T104
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T24
0	1	Unreachable
1	0	Covered	T22,T23,T24

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T22,T23,T24
DetectSt	168	Covered	T22,T23,T24
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T22,T23,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T22,T23,T24
DebounceSt->IdleSt	163	Covered	T87,T90,T132
DetectSt->IdleSt	186	Covered	T24,T89,T104
DetectSt->StableSt	191	Covered	T22,T23,T24
IdleSt->DebounceSt	148	Covered	T22,T23,T24
StableSt->IdleSt	206	Covered	T22,T23,T24

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T22,T23,T24
0	1	Covered	T22,T23,T24
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T22,T23,T24
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T56
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T23,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T87,T90,T132
DebounceSt	-	0	0	-	-	-	-	Covered	T22,T23,T24
DetectSt	-	-	-	-	1	-	-	Covered	T24,T89,T104
DetectSt	-	-	-	-	0	1	-	Covered	T22,T23,T24
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T22,T23,T24
StableSt	-	-	-	-	-	-	0	Covered	T22,T23,T24
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10081786	202	0	0
CntIncr_A	10081786	424146	0	0
CntNoWrap_A	10081786	9352749	0	0
DetectStDropOut_A	10081786	18	0	0
DetectedOut_A	10081786	106750	0	0
DetectedPulseOut_A	10081786	57	0	0
DisabledIdleSt_A	10081786	7869380	0	0
DisabledNoDetection_A	10081786	7871985	0	0
EnterDebounceSt_A	10081786	128	0	0
EnterDetectSt_A	10081786	75	0	0
EnterStableSt_A	10081786	57	0	0
PulseIsPulse_A	10081786	57	0	0
StayInStableSt	10081786	106693	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	10081786	7390	0	0
gen_low_level_sva.LowLevelEvent_A	10081786	9355557	0	0
gen_sticky_sva.StableStDropOut_A	10081786	945906	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	202	0	0
T22	817	2	0	0
T23	1382	4	0	0
T24	0	4	0	0
T47	698	0	0	0
T58	1928	0	0	0
T63	0	2	0	0
T84	4816	0	0	0
T85	0	2	0	0
T86	0	2	0	0
T87	0	3	0	0
T88	0	2	0	0
T89	0	8	0	0
T90	0	2	0	0
T91	502	0	0	0
T92	581	0	0	0
T93	12729	0	0	0
T94	768	0	0	0
T95	507	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	424146	0	0
T22	817	35	0	0
T23	1382	36	0	0
T24	0	60	0	0
T47	698	0	0	0
T58	1928	0	0	0
T63	0	42	0	0
T84	4816	0	0	0
T85	0	43	0	0
T86	0	81	0	0
T87	0	246	0	0
T88	0	45	0	0
T89	0	203	0	0
T90	0	104	0	0
T91	502	0	0	0
T92	581	0	0	0
T93	12729	0	0	0
T94	768	0	0	0
T95	507	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9352749	0	0
T1	540	139	0	0
T2	17755	17322	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	18	0	0
T24	1258	1	0	0
T45	1731	0	0	0
T48	2074	0	0	0
T62	665259	0	0	0
T89	0	2	0	0
T104	0	2	0	0
T136	0	2	0	0
T137	0	3	0	0
T138	0	3	0	0
T139	0	2	0	0
T140	0	1	0	0
T141	0	2	0	0
T142	492	0	0	0
T143	404	0	0	0
T144	527	0	0	0
T145	598	0	0	0
T146	404	0	0	0
T147	1081	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	106750	0	0
T22	817	165	0	0
T23	1382	64	0	0
T24	0	63	0	0
T47	698	0	0	0
T58	1928	0	0	0
T63	0	125	0	0
T84	4816	0	0	0
T85	0	210	0	0
T86	0	20	0	0
T88	0	130	0	0
T89	0	247	0	0
T91	502	0	0	0
T92	581	0	0	0
T93	12729	0	0	0
T94	768	0	0	0
T95	507	0	0	0
T133	0	95559	0	0
T134	0	283	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	57	0	0
T22	817	1	0	0
T23	1382	2	0	0
T24	0	1	0	0
T47	698	0	0	0
T58	1928	0	0	0
T63	0	1	0	0
T84	4816	0	0	0
T85	0	1	0	0
T86	0	1	0	0
T88	0	1	0	0
T89	0	2	0	0
T91	502	0	0	0
T92	581	0	0	0
T93	12729	0	0	0
T94	768	0	0	0
T95	507	0	0	0
T133	0	1	0	0
T134	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	7869380	0	0
T1	540	139	0	0
T2	17755	17322	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	7871985	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	128	0	0
T22	817	1	0	0
T23	1382	2	0	0
T24	0	2	0	0
T47	698	0	0	0
T58	1928	0	0	0
T63	0	1	0	0
T84	4816	0	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	3	0	0
T88	0	1	0	0
T89	0	4	0	0
T90	0	2	0	0
T91	502	0	0	0
T92	581	0	0	0
T93	12729	0	0	0
T94	768	0	0	0
T95	507	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	75	0	0
T22	817	1	0	0
T23	1382	2	0	0
T24	0	2	0	0
T47	698	0	0	0
T58	1928	0	0	0
T63	0	1	0	0
T84	4816	0	0	0
T85	0	1	0	0
T86	0	1	0	0
T88	0	1	0	0
T89	0	4	0	0
T91	502	0	0	0
T92	581	0	0	0
T93	12729	0	0	0
T94	768	0	0	0
T95	507	0	0	0
T133	0	1	0	0
T134	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	57	0	0
T22	817	1	0	0
T23	1382	2	0	0
T24	0	1	0	0
T47	698	0	0	0
T58	1928	0	0	0
T63	0	1	0	0
T84	4816	0	0	0
T85	0	1	0	0
T86	0	1	0	0
T88	0	1	0	0
T89	0	2	0	0
T91	502	0	0	0
T92	581	0	0	0
T93	12729	0	0	0
T94	768	0	0	0
T95	507	0	0	0
T133	0	1	0	0
T134	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	57	0	0
T22	817	1	0	0
T23	1382	2	0	0
T24	0	1	0	0
T47	698	0	0	0
T58	1928	0	0	0
T63	0	1	0	0
T84	4816	0	0	0
T85	0	1	0	0
T86	0	1	0	0
T88	0	1	0	0
T89	0	2	0	0
T91	502	0	0	0
T92	581	0	0	0
T93	12729	0	0	0
T94	768	0	0	0
T95	507	0	0	0
T133	0	1	0	0
T134	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	106693	0	0
T22	817	164	0	0
T23	1382	62	0	0
T24	0	62	0	0
T47	698	0	0	0
T58	1928	0	0	0
T63	0	124	0	0
T84	4816	0	0	0
T85	0	209	0	0
T86	0	19	0	0
T88	0	129	0	0
T89	0	245	0	0
T91	502	0	0	0
T92	581	0	0	0
T93	12729	0	0	0
T94	768	0	0	0
T95	507	0	0	0
T133	0	95558	0	0
T134	0	281	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	7390	0	0
T1	540	1	0	0
T2	17755	29	0	0
T3	9207	13	0	0
T4	2426	19	0	0
T5	405	0	0	0
T6	9065	26	0	0
T13	423	3	0	0
T14	5416	23	0	0
T15	418	2	0	0
T16	425	2	0	0
T17	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9355557	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	945906	0	0
T22	817	167	0	0
T23	1382	284	0	0
T24	0	307	0	0
T47	698	0	0	0
T58	1928	0	0	0
T63	0	90548	0	0
T84	4816	0	0	0
T85	0	115	0	0
T86	0	112	0	0
T88	0	155	0	0
T89	0	201	0	0
T91	502	0	0	0
T92	581	0	0	0
T93	12729	0	0	0
T94	768	0	0	0
T95	507	0	0	0
T133	0	38	0	0
T134	0	71	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T22,T23,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T22,T23,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T22,T24,T85

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Covered	T4,T1,T5
1	1	Covered	T22,T23,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T24,T85
0	1	Covered	T87,T102,T103
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T24,T85
0	1	Unreachable
1	0	Covered	T22,T24,T85

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T22,T23,T24
DetectSt	168	Covered	T22,T24,T85
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T22,T24,T85

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T22,T24,T85
DebounceSt->IdleSt	163	Covered	T23,T63,T86
DetectSt->IdleSt	186	Covered	T87,T102,T103
DetectSt->StableSt	191	Covered	T22,T24,T85
IdleSt->DebounceSt	148	Covered	T22,T23,T24
StableSt->IdleSt	206	Covered	T22,T24,T85

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T22,T23,T24
0	1	Covered	T22,T23,T24
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T24,T85
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T22,T23,T24
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T56
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T24,T85
DebounceSt	-	0	1	0	-	-	-	Covered	T23,T63,T86
DebounceSt	-	0	0	-	-	-	-	Covered	T22,T23,T24
DetectSt	-	-	-	-	1	-	-	Covered	T87,T102,T103
DetectSt	-	-	-	-	0	1	-	Covered	T22,T24,T85
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T22,T24,T85
StableSt	-	-	-	-	-	-	0	Covered	T22,T24,T85
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10081786	183	0	0
CntIncr_A	10081786	383567	0	0
CntNoWrap_A	10081786	9352768	0	0
DetectStDropOut_A	10081786	7	0	0
DetectedOut_A	10081786	449077	0	0
DetectedPulseOut_A	10081786	55	0	0
DisabledIdleSt_A	10081786	7869380	0	0
DisabledNoDetection_A	10081786	7871985	0	0
EnterDebounceSt_A	10081786	122	0	0
EnterDetectSt_A	10081786	62	0	0
EnterStableSt_A	10081786	55	0	0
PulseIsPulse_A	10081786	55	0	0
StayInStableSt	10081786	449022	0	0
gen_high_level_sva.HighLevelEvent_A	10081786	9355557	0	0
gen_sticky_sva.StableStDropOut_A	10081786	552464	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	183	0	0
T22	817	2	0	0
T23	1382	3	0	0
T24	0	2	0	0
T47	698	0	0	0
T58	1928	0	0	0
T63	0	2	0	0
T84	4816	0	0	0
T85	0	2	0	0
T86	0	1	0	0
T87	0	5	0	0
T88	0	2	0	0
T89	0	4	0	0
T90	0	2	0	0
T91	502	0	0	0
T92	581	0	0	0
T93	12729	0	0	0
T94	768	0	0	0
T95	507	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	383567	0	0
T22	817	60	0	0
T23	1382	159	0	0
T24	0	62	0	0
T47	698	0	0	0
T58	1928	0	0	0
T63	0	90660	0	0
T84	4816	0	0	0
T85	0	47	0	0
T86	0	100	0	0
T87	0	96	0	0
T88	0	57	0	0
T89	0	58	0	0
T90	0	84	0	0
T91	502	0	0	0
T92	581	0	0	0
T93	12729	0	0	0
T94	768	0	0	0
T95	507	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9352768	0	0
T1	540	139	0	0
T2	17755	17322	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	7	0	0
T87	7365	2	0	0
T102	0	2	0	0
T103	0	1	0	0
T139	0	1	0	0
T148	0	1	0	0
T149	815	0	0	0
T150	493	0	0	0
T151	502	0	0	0
T152	8349	0	0	0
T153	12882	0	0	0
T154	697	0	0	0
T155	445	0	0	0
T156	426	0	0	0
T157	423	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	449077	0	0
T22	817	249	0	0
T23	1382	0	0	0
T24	0	280	0	0
T47	698	0	0	0
T58	1928	0	0	0
T84	4816	0	0	0
T85	0	228	0	0
T88	0	217	0	0
T89	0	260	0	0
T90	0	107	0	0
T91	502	0	0	0
T92	581	0	0	0
T93	12729	0	0	0
T94	768	0	0	0
T95	507	0	0	0
T100	0	210	0	0
T132	0	133	0	0
T133	0	267	0	0
T134	0	91	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	55	0	0
T22	817	1	0	0
T23	1382	0	0	0
T24	0	1	0	0
T47	698	0	0	0
T58	1928	0	0	0
T84	4816	0	0	0
T85	0	1	0	0
T88	0	1	0	0
T89	0	2	0	0
T90	0	1	0	0
T91	502	0	0	0
T92	581	0	0	0
T93	12729	0	0	0
T94	768	0	0	0
T95	507	0	0	0
T100	0	1	0	0
T132	0	2	0	0
T133	0	1	0	0
T134	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	7869380	0	0
T1	540	139	0	0
T2	17755	17322	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	7871985	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	122	0	0
T22	817	1	0	0
T23	1382	3	0	0
T24	0	1	0	0
T47	698	0	0	0
T58	1928	0	0	0
T63	0	2	0	0
T84	4816	0	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	3	0	0
T88	0	1	0	0
T89	0	2	0	0
T90	0	1	0	0
T91	502	0	0	0
T92	581	0	0	0
T93	12729	0	0	0
T94	768	0	0	0
T95	507	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	62	0	0
T22	817	1	0	0
T23	1382	0	0	0
T24	0	1	0	0
T47	698	0	0	0
T58	1928	0	0	0
T84	4816	0	0	0
T85	0	1	0	0
T87	0	2	0	0
T88	0	1	0	0
T89	0	2	0	0
T90	0	1	0	0
T91	502	0	0	0
T92	581	0	0	0
T93	12729	0	0	0
T94	768	0	0	0
T95	507	0	0	0
T132	0	2	0	0
T133	0	1	0	0
T134	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	55	0	0
T22	817	1	0	0
T23	1382	0	0	0
T24	0	1	0	0
T47	698	0	0	0
T58	1928	0	0	0
T84	4816	0	0	0
T85	0	1	0	0
T88	0	1	0	0
T89	0	2	0	0
T90	0	1	0	0
T91	502	0	0	0
T92	581	0	0	0
T93	12729	0	0	0
T94	768	0	0	0
T95	507	0	0	0
T100	0	1	0	0
T132	0	2	0	0
T133	0	1	0	0
T134	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	55	0	0
T22	817	1	0	0
T23	1382	0	0	0
T24	0	1	0	0
T47	698	0	0	0
T58	1928	0	0	0
T84	4816	0	0	0
T85	0	1	0	0
T88	0	1	0	0
T89	0	2	0	0
T90	0	1	0	0
T91	502	0	0	0
T92	581	0	0	0
T93	12729	0	0	0
T94	768	0	0	0
T95	507	0	0	0
T100	0	1	0	0
T132	0	2	0	0
T133	0	1	0	0
T134	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	449022	0	0
T22	817	248	0	0
T23	1382	0	0	0
T24	0	279	0	0
T47	698	0	0	0
T58	1928	0	0	0
T84	4816	0	0	0
T85	0	227	0	0
T88	0	216	0	0
T89	0	258	0	0
T90	0	106	0	0
T91	502	0	0	0
T92	581	0	0	0
T93	12729	0	0	0
T94	768	0	0	0
T95	507	0	0	0
T100	0	209	0	0
T132	0	131	0	0
T133	0	266	0	0
T134	0	89	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9355557	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	552464	0	0
T22	817	73	0	0
T23	1382	0	0	0
T24	0	197	0	0
T47	698	0	0	0
T58	1928	0	0	0
T84	4816	0	0	0
T85	0	96	0	0
T88	0	55	0	0
T89	0	412	0	0
T90	0	266	0	0
T91	502	0	0	0
T92	581	0	0	0
T93	12729	0	0	0
T94	768	0	0	0
T95	507	0	0	0
T100	0	52493	0	0
T132	0	688	0	0
T133	0	132962	0	0
T134	0	378	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T22,T23,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T22,T23,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T22,T23,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Covered	T4,T1,T13
1	1	Covered	T22,T23,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T24
0	1	Covered	T23,T89,T100
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T24
0	1	Unreachable
1	0	Covered	T22,T23,T24

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T22,T23,T24
DetectSt	168	Covered	T22,T23,T24
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T22,T23,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T22,T23,T24
DebounceSt->IdleSt	163	Covered	T63,T106,T158
DetectSt->IdleSt	186	Covered	T23,T89,T100
DetectSt->StableSt	191	Covered	T22,T23,T24
IdleSt->DebounceSt	148	Covered	T22,T23,T24
StableSt->IdleSt	206	Covered	T22,T23,T24

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T22,T23,T24
0	1	Covered	T22,T23,T24
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T22,T23,T24
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T56
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T23,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T63,T106,T158
DebounceSt	-	0	0	-	-	-	-	Covered	T22,T23,T24
DetectSt	-	-	-	-	1	-	-	Covered	T23,T89,T100
DetectSt	-	-	-	-	0	1	-	Covered	T22,T23,T24
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T22,T23,T24
StableSt	-	-	-	-	-	-	0	Covered	T22,T23,T24
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10081786	191	0	0
CntIncr_A	10081786	73869	0	0
CntNoWrap_A	10081786	9352760	0	0
DetectStDropOut_A	10081786	19	0	0
DetectedOut_A	10081786	67884	0	0
DetectedPulseOut_A	10081786	61	0	0
DisabledIdleSt_A	10081786	7869380	0	0
DisabledNoDetection_A	10081786	7871985	0	0
EnterDebounceSt_A	10081786	112	0	0
EnterDetectSt_A	10081786	80	0	0
EnterStableSt_A	10081786	61	0	0
PulseIsPulse_A	10081786	61	0	0
StayInStableSt	10081786	67823	0	0
gen_high_event_sva.HighLevelEvent_A	10081786	9355557	0	0
gen_high_level_sva.HighLevelEvent_A	10081786	9355557	0	0
gen_sticky_sva.StableStDropOut_A	10081786	1245828	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	191	0	0
T22	817	2	0	0
T23	1382	6	0	0
T24	0	2	0	0
T47	698	0	0	0
T58	1928	0	0	0
T63	0	2	0	0
T84	4816	0	0	0
T85	0	2	0	0
T86	0	2	0	0
T87	0	2	0	0
T88	0	2	0	0
T89	0	8	0	0
T90	0	2	0	0
T91	502	0	0	0
T92	581	0	0	0
T93	12729	0	0	0
T94	768	0	0	0
T95	507	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	73869	0	0
T22	817	63	0	0
T23	1382	267	0	0
T24	0	78	0	0
T47	698	0	0	0
T58	1928	0	0	0
T63	0	158	0	0
T84	4816	0	0	0
T85	0	24	0	0
T86	0	82	0	0
T87	0	61	0	0
T88	0	80	0	0
T89	0	332	0	0
T90	0	98	0	0
T91	502	0	0	0
T92	581	0	0	0
T93	12729	0	0	0
T94	768	0	0	0
T95	507	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9352760	0	0
T1	540	139	0	0
T2	17755	17322	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	19	0	0
T23	1382	2	0	0
T47	698	0	0	0
T58	1928	0	0	0
T84	4816	0	0	0
T89	0	2	0	0
T91	502	0	0	0
T92	581	0	0	0
T93	12729	0	0	0
T94	768	0	0	0
T95	507	0	0	0
T100	0	4	0	0
T103	0	1	0	0
T106	0	3	0	0
T159	0	5	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	518	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	67884	0	0
T22	817	270	0	0
T23	1382	1	0	0
T24	0	419	0	0
T47	698	0	0	0
T58	1928	0	0	0
T84	4816	0	0	0
T85	0	90	0	0
T86	0	21	0	0
T87	0	192	0	0
T88	0	192	0	0
T89	0	314	0	0
T90	0	260	0	0
T91	502	0	0	0
T92	581	0	0	0
T93	12729	0	0	0
T94	768	0	0	0
T95	507	0	0	0
T132	0	369	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	61	0	0
T22	817	1	0	0
T23	1382	1	0	0
T24	0	1	0	0
T47	698	0	0	0
T58	1928	0	0	0
T84	4816	0	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	2	0	0
T90	0	1	0	0
T91	502	0	0	0
T92	581	0	0	0
T93	12729	0	0	0
T94	768	0	0	0
T95	507	0	0	0
T132	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	7869380	0	0
T1	540	139	0	0
T2	17755	17322	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	7871985	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	112	0	0
T22	817	1	0	0
T23	1382	3	0	0
T24	0	1	0	0
T47	698	0	0	0
T58	1928	0	0	0
T63	0	2	0	0
T84	4816	0	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	4	0	0
T90	0	1	0	0
T91	502	0	0	0
T92	581	0	0	0
T93	12729	0	0	0
T94	768	0	0	0
T95	507	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	80	0	0
T22	817	1	0	0
T23	1382	3	0	0
T24	0	1	0	0
T47	698	0	0	0
T58	1928	0	0	0
T84	4816	0	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	4	0	0
T90	0	1	0	0
T91	502	0	0	0
T92	581	0	0	0
T93	12729	0	0	0
T94	768	0	0	0
T95	507	0	0	0
T132	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	61	0	0
T22	817	1	0	0
T23	1382	1	0	0
T24	0	1	0	0
T47	698	0	0	0
T58	1928	0	0	0
T84	4816	0	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	2	0	0
T90	0	1	0	0
T91	502	0	0	0
T92	581	0	0	0
T93	12729	0	0	0
T94	768	0	0	0
T95	507	0	0	0
T132	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	61	0	0
T22	817	1	0	0
T23	1382	1	0	0
T24	0	1	0	0
T47	698	0	0	0
T58	1928	0	0	0
T84	4816	0	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	2	0	0
T90	0	1	0	0
T91	502	0	0	0
T92	581	0	0	0
T93	12729	0	0	0
T94	768	0	0	0
T95	507	0	0	0
T132	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	67823	0	0
T22	817	269	0	0
T23	1382	0	0	0
T24	0	418	0	0
T47	698	0	0	0
T58	1928	0	0	0
T84	4816	0	0	0
T85	0	89	0	0
T86	0	20	0	0
T87	0	191	0	0
T88	0	191	0	0
T89	0	312	0	0
T90	0	259	0	0
T91	502	0	0	0
T92	581	0	0	0
T93	12729	0	0	0
T94	768	0	0	0
T95	507	0	0	0
T132	0	367	0	0
T133	0	44	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9355557	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9355557	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	1245828	0	0
T22	817	51	0	0
T23	1382	57	0	0
T24	0	47	0	0
T47	698	0	0	0
T58	1928	0	0	0
T84	4816	0	0	0
T85	0	263	0	0
T86	0	117	0	0
T87	0	94	0	0
T88	0	65	0	0
T89	0	84	0	0
T90	0	118	0	0
T91	502	0	0	0
T92	581	0	0	0
T93	12729	0	0	0
T94	768	0	0	0
T95	507	0	0	0
T132	0	446	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T11,T45,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T11,T45,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T11,T45,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T11,T38
1	0	Covered	T4,T1,T5
1	1	Covered	T11,T45,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T45,T44
0	1	Covered	T163
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T45,T44
0	1	Covered	T45,T51,T164
1	0	Covered	T55,T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T45,T44
1	-	Covered	T45,T51,T164

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T45,T44
DetectSt	168	Covered	T11,T45,T44
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T11,T45,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T45,T44
DebounceSt->IdleSt	163	Covered	T164,T163,T141
DetectSt->IdleSt	186	Covered	T163
DetectSt->StableSt	191	Covered	T11,T45,T44
IdleSt->DebounceSt	148	Covered	T11,T45,T44
StableSt->IdleSt	206	Covered	T11,T45,T51

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T45,T44
0	1	Covered	T11,T45,T44
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T45,T44
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T45,T44
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T45,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T164,T163,T141
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T45,T44
DetectSt	-	-	-	-	1	-	-	Covered	T163
DetectSt	-	-	-	-	0	1	-	Covered	T11,T45,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T45,T51,T164
StableSt	-	-	-	-	-	-	0	Covered	T11,T45,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10081786	103	0	0
CntIncr_A	10081786	85237	0	0
CntNoWrap_A	10081786	9352848	0	0
DetectStDropOut_A	10081786	1	0	0
DetectedOut_A	10081786	28256	0	0
DetectedPulseOut_A	10081786	49	0	0
DisabledIdleSt_A	10081786	8986859	0	0
DisabledNoDetection_A	10081786	8989404	0	0
EnterDebounceSt_A	10081786	53	0	0
EnterDetectSt_A	10081786	50	0	0
EnterStableSt_A	10081786	49	0	0
PulseIsPulse_A	10081786	49	0	0
StayInStableSt	10081786	28186	0	0
gen_high_level_sva.HighLevelEvent_A	10081786	9355557	0	0
gen_not_sticky_sva.StableStDropOut_A	10081786	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	103	0	0
T11	186745	2	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T35	27601	0	0	0
T38	898	0	0	0
T44	0	2	0	0
T45	0	2	0	0
T51	0	4	0	0
T74	422	0	0	0
T75	502	0	0	0
T76	502	0	0	0
T89	0	2	0	0
T101	0	4	0	0
T149	0	2	0	0
T164	0	3	0	0
T165	0	2	0	0
T166	0	4	0	0
T167	403	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	85237	0	0
T11	186745	40220	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T35	27601	0	0	0
T38	898	0	0	0
T44	0	28	0	0
T45	0	29	0	0
T51	0	118	0	0
T74	422	0	0	0
T75	502	0	0	0
T76	502	0	0	0
T89	0	57	0	0
T101	0	156	0	0
T149	0	73	0	0
T164	0	132	0	0
T165	0	45	0	0
T166	0	50	0	0
T167	403	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9352848	0	0
T1	540	139	0	0
T2	17755	17322	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	1	0	0
T163	21485	1	0	0
T168	9954	0	0	0
T169	503	0	0	0
T170	422	0	0	0
T171	728	0	0	0
T172	526	0	0	0
T173	924	0	0	0
T174	414	0	0	0
T175	544	0	0	0
T176	675	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	28256	0	0
T11	186745	38	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T35	27601	0	0	0
T38	898	0	0	0
T44	0	45	0	0
T45	0	11	0	0
T51	0	84	0	0
T74	422	0	0	0
T75	502	0	0	0
T76	502	0	0	0
T89	0	43	0	0
T101	0	94	0	0
T149	0	114	0	0
T164	0	65	0	0
T165	0	42	0	0
T166	0	83	0	0
T167	403	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	49	0	0
T11	186745	1	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T35	27601	0	0	0
T38	898	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T51	0	2	0	0
T74	422	0	0	0
T75	502	0	0	0
T76	502	0	0	0
T89	0	1	0	0
T101	0	2	0	0
T149	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	2	0	0
T167	403	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	8986859	0	0
T1	540	139	0	0
T2	17755	17322	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	8989404	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	53	0	0
T11	186745	1	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T35	27601	0	0	0
T38	898	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T51	0	2	0	0
T74	422	0	0	0
T75	502	0	0	0
T76	502	0	0	0
T89	0	1	0	0
T101	0	2	0	0
T149	0	1	0	0
T164	0	2	0	0
T165	0	1	0	0
T166	0	2	0	0
T167	403	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	50	0	0
T11	186745	1	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T35	27601	0	0	0
T38	898	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T51	0	2	0	0
T74	422	0	0	0
T75	502	0	0	0
T76	502	0	0	0
T89	0	1	0	0
T101	0	2	0	0
T149	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	2	0	0
T167	403	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	49	0	0
T11	186745	1	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T35	27601	0	0	0
T38	898	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T51	0	2	0	0
T74	422	0	0	0
T75	502	0	0	0
T76	502	0	0	0
T89	0	1	0	0
T101	0	2	0	0
T149	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	2	0	0
T167	403	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	49	0	0
T11	186745	1	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T35	27601	0	0	0
T38	898	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T51	0	2	0	0
T74	422	0	0	0
T75	502	0	0	0
T76	502	0	0	0
T89	0	1	0	0
T101	0	2	0	0
T149	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	2	0	0
T167	403	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	28186	0	0
T11	186745	36	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T35	27601	0	0	0
T38	898	0	0	0
T44	0	43	0	0
T45	0	10	0	0
T51	0	81	0	0
T74	422	0	0	0
T75	502	0	0	0
T76	502	0	0	0
T89	0	41	0	0
T101	0	91	0	0
T149	0	113	0	0
T164	0	64	0	0
T165	0	40	0	0
T166	0	80	0	0
T167	403	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9355557	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	26	0	0
T45	1731	1	0	0
T48	2074	0	0	0
T51	0	1	0	0
T63	136521	0	0	0
T101	0	1	0	0
T106	0	1	0	0
T143	404	0	0	0
T144	527	0	0	0
T145	598	0	0	0
T146	404	0	0	0
T147	1081	0	0	0
T149	0	1	0	0
T164	0	1	0	0
T166	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T180	13088	0	0	0
T181	839	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T7,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T7,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T7,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T9,T11
1	0	Covered	T4,T13,T2
1	1	Covered	T7,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T11
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T11
0	1	Covered	T9,T11,T40
1	0	Covered	T55,T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T9,T11
1	-	Covered	T9,T11,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T9,T11
DetectSt	168	Covered	T7,T9,T11
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T7,T9,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T9,T11
DebounceSt->IdleSt	163	Covered	T101,T160,T182
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T7,T9,T11
IdleSt->DebounceSt	148	Covered	T7,T9,T11
StableSt->IdleSt	206	Covered	T9,T11,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T9,T11
0	1	Covered	T7,T9,T11
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T11
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T101,T182,T183
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T9,T11
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T7,T9,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T11,T40
StableSt	-	-	-	-	-	-	0	Covered	T7,T9,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10081786	185	0	0
CntIncr_A	10081786	109187	0	0
CntNoWrap_A	10081786	9352766	0	0
DetectStDropOut_A	10081786	0	0	0
DetectedOut_A	10081786	112025	0	0
DetectedPulseOut_A	10081786	91	0	0
DisabledIdleSt_A	10081786	8760643	0	0
DisabledNoDetection_A	10081786	8763182	0	0
EnterDebounceSt_A	10081786	95	0	0
EnterDetectSt_A	10081786	91	0	0
EnterStableSt_A	10081786	91	0	0
PulseIsPulse_A	10081786	91	0	0
StayInStableSt	10081786	111896	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	10081786	3027	0	0
gen_low_level_sva.LowLevelEvent_A	10081786	9355557	0	0
gen_not_sticky_sva.StableStDropOut_A	10081786	51	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	185	0	0
T7	810	2	0	0
T8	18502	0	0	0
T9	1492	4	0	0
T10	14723	0	0	0
T11	186745	2	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	2	0	0
T40	0	4	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	4	0	0
T51	0	4	0	0
T74	422	0	0	0
T81	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	109187	0	0
T7	810	59	0	0
T8	18502	0	0	0
T9	1492	52	0	0
T10	14723	0	0	0
T11	186745	40220	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	97	0	0
T40	0	146	0	0
T43	0	62	0	0
T44	0	28	0	0
T45	0	58	0	0
T51	0	140	0	0
T74	422	0	0	0
T81	0	62	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9352766	0	0
T1	540	139	0	0
T2	17755	17322	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	112025	0	0
T7	810	158	0	0
T8	18502	0	0	0
T9	1492	82	0	0
T10	14723	0	0	0
T11	186745	40264	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	42	0	0
T40	0	90	0	0
T43	0	204	0	0
T44	0	141	0	0
T45	0	202	0	0
T51	0	330	0	0
T74	422	0	0	0
T81	0	102	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	91	0	0
T7	810	1	0	0
T8	18502	0	0	0
T9	1492	2	0	0
T10	14723	0	0	0
T11	186745	1	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	1	0	0
T40	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T51	0	2	0	0
T74	422	0	0	0
T81	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	8760643	0	0
T1	540	139	0	0
T2	17755	17322	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	8763182	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	95	0	0
T7	810	1	0	0
T8	18502	0	0	0
T9	1492	2	0	0
T10	14723	0	0	0
T11	186745	1	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	1	0	0
T40	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T51	0	2	0	0
T74	422	0	0	0
T81	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	91	0	0
T7	810	1	0	0
T8	18502	0	0	0
T9	1492	2	0	0
T10	14723	0	0	0
T11	186745	1	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	1	0	0
T40	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T51	0	2	0	0
T74	422	0	0	0
T81	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	91	0	0
T7	810	1	0	0
T8	18502	0	0	0
T9	1492	2	0	0
T10	14723	0	0	0
T11	186745	1	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	1	0	0
T40	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T51	0	2	0	0
T74	422	0	0	0
T81	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	91	0	0
T7	810	1	0	0
T8	18502	0	0	0
T9	1492	2	0	0
T10	14723	0	0	0
T11	186745	1	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	1	0	0
T40	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T51	0	2	0	0
T74	422	0	0	0
T81	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	111896	0	0
T7	810	156	0	0
T8	18502	0	0	0
T9	1492	80	0	0
T10	14723	0	0	0
T11	186745	40263	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	40	0	0
T40	0	87	0	0
T43	0	202	0	0
T44	0	140	0	0
T45	0	199	0	0
T51	0	327	0	0
T74	422	0	0	0
T81	0	99	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	3027	0	0
T1	540	0	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T4	2426	21	0	0
T5	405	0	0	0
T6	9065	0	0	0
T7	0	1	0	0
T9	0	5	0	0
T11	0	12	0	0
T13	423	1	0	0
T14	5416	0	0	0
T15	418	1	0	0
T16	425	3	0	0
T17	0	6	0	0
T25	0	5	0	0
T27	0	16	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9355557	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	51	0	0
T9	1492	2	0	0
T10	14723	0	0	0
T11	186745	1	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	0	0	0
T40	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T51	0	1	0	0
T74	422	0	0	0
T75	502	0	0	0
T81	0	1	0	0
T87	0	1	0	0
T101	0	1	0	0
T164	0	2	0	0
T167	403	0	0	0