Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.16	93.48	95.24		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.16	93.48	95.24		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T38,T43,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T38,T43,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T38,T43,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T38,T43,T80
1	0	Covered	T4,T1,T5
1	1	Covered	T38,T43,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T38,T43,T44
0	1	Covered	T51
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T38,T43,T44
0	1	Covered	T38,T43,T87
1	0	Covered	T55,T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T38,T43,T44
1	-	Covered	T38,T43,T87

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T38,T43,T44
DetectSt	168	Covered	T38,T43,T44
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T38,T43,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T38,T43,T44
DebounceSt->IdleSt	163	Covered	T89,T184
DetectSt->IdleSt	186	Covered	T51
DetectSt->StableSt	191	Covered	T38,T43,T44
IdleSt->DebounceSt	148	Covered	T38,T43,T44
StableSt->IdleSt	206	Covered	T38,T43,T86

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T38,T43,T44
0	1	Covered	T38,T43,T44
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T38,T43,T44
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T38,T43,T44
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T38,T43,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T89,T184
DebounceSt	-	0	0	-	-	-	-	Covered	T38,T43,T44
DetectSt	-	-	-	-	1	-	-	Covered	T51
DetectSt	-	-	-	-	0	1	-	Covered	T38,T43,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T38,T43,T87
StableSt	-	-	-	-	-	-	0	Covered	T38,T43,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10081786	86	0	0
CntIncr_A	10081786	109500	0	0
CntNoWrap_A	10081786	9352865	0	0
DetectStDropOut_A	10081786	1	0	0
DetectedOut_A	10081786	2748	0	0
DetectedPulseOut_A	10081786	41	0	0
DisabledIdleSt_A	10081786	9044297	0	0
DisabledNoDetection_A	10081786	9046848	0	0
EnterDebounceSt_A	10081786	44	0	0
EnterDetectSt_A	10081786	42	0	0
EnterStableSt_A	10081786	41	0	0
PulseIsPulse_A	10081786	41	0	0
StayInStableSt	10081786	2687	0	0
gen_high_level_sva.HighLevelEvent_A	10081786	9355557	0	0
gen_not_sticky_sva.StableStDropOut_A	10081786	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	86	0	0
T26	497	0	0	0
T34	22223	0	0	0
T35	27601	0	0	0
T38	898	2	0	0
T43	0	4	0	0
T44	0	2	0	0
T51	0	2	0	0
T71	492	0	0	0
T74	422	0	0	0
T75	502	0	0	0
T76	502	0	0	0
T77	526	0	0	0
T86	0	2	0	0
T87	0	4	0	0
T89	0	3	0	0
T104	0	2	0	0
T106	0	2	0	0
T167	403	0	0	0
T185	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	109500	0	0
T26	497	0	0	0
T34	22223	0	0	0
T35	27601	0	0	0
T38	898	97	0	0
T43	0	124	0	0
T44	0	28	0	0
T51	0	70	0	0
T71	492	0	0	0
T74	422	0	0	0
T75	502	0	0	0
T76	502	0	0	0
T77	526	0	0	0
T86	0	87	0	0
T87	0	38	0	0
T89	0	65022	0	0
T104	0	53	0	0
T106	0	46	0	0
T167	403	0	0	0
T185	0	73	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9352865	0	0
T1	540	139	0	0
T2	17755	17322	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	1	0	0
T51	9387	1	0	0
T52	777	0	0	0
T108	22972	0	0	0
T186	13430	0	0	0
T187	675	0	0	0
T188	429	0	0	0
T189	1058	0	0	0
T190	419	0	0	0
T191	490	0	0	0
T192	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	2748	0	0
T26	497	0	0	0
T34	22223	0	0	0
T35	27601	0	0	0
T38	898	152	0	0
T43	0	246	0	0
T44	0	44	0	0
T55	0	1	0	0
T71	492	0	0	0
T74	422	0	0	0
T75	502	0	0	0
T76	502	0	0	0
T77	526	0	0	0
T86	0	40	0	0
T87	0	61	0	0
T89	0	43	0	0
T104	0	50	0	0
T106	0	45	0	0
T167	403	0	0	0
T185	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	41	0	0
T26	497	0	0	0
T34	22223	0	0	0
T35	27601	0	0	0
T38	898	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T55	0	1	0	0
T71	492	0	0	0
T74	422	0	0	0
T75	502	0	0	0
T76	502	0	0	0
T77	526	0	0	0
T86	0	1	0	0
T87	0	2	0	0
T89	0	1	0	0
T104	0	1	0	0
T106	0	1	0	0
T167	403	0	0	0
T185	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9044297	0	0
T1	540	139	0	0
T2	17755	17322	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9046848	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	44	0	0
T26	497	0	0	0
T34	22223	0	0	0
T35	27601	0	0	0
T38	898	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T51	0	1	0	0
T71	492	0	0	0
T74	422	0	0	0
T75	502	0	0	0
T76	502	0	0	0
T77	526	0	0	0
T86	0	1	0	0
T87	0	2	0	0
T89	0	2	0	0
T104	0	1	0	0
T106	0	1	0	0
T167	403	0	0	0
T185	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	42	0	0
T26	497	0	0	0
T34	22223	0	0	0
T35	27601	0	0	0
T38	898	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T51	0	1	0	0
T71	492	0	0	0
T74	422	0	0	0
T75	502	0	0	0
T76	502	0	0	0
T77	526	0	0	0
T86	0	1	0	0
T87	0	2	0	0
T89	0	1	0	0
T104	0	1	0	0
T106	0	1	0	0
T167	403	0	0	0
T185	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	41	0	0
T26	497	0	0	0
T34	22223	0	0	0
T35	27601	0	0	0
T38	898	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T55	0	1	0	0
T71	492	0	0	0
T74	422	0	0	0
T75	502	0	0	0
T76	502	0	0	0
T77	526	0	0	0
T86	0	1	0	0
T87	0	2	0	0
T89	0	1	0	0
T104	0	1	0	0
T106	0	1	0	0
T167	403	0	0	0
T185	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	41	0	0
T26	497	0	0	0
T34	22223	0	0	0
T35	27601	0	0	0
T38	898	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T55	0	1	0	0
T71	492	0	0	0
T74	422	0	0	0
T75	502	0	0	0
T76	502	0	0	0
T77	526	0	0	0
T86	0	1	0	0
T87	0	2	0	0
T89	0	1	0	0
T104	0	1	0	0
T106	0	1	0	0
T167	403	0	0	0
T185	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	2687	0	0
T26	497	0	0	0
T34	22223	0	0	0
T35	27601	0	0	0
T38	898	151	0	0
T43	0	243	0	0
T44	0	42	0	0
T71	492	0	0	0
T74	422	0	0	0
T75	502	0	0	0
T76	502	0	0	0
T77	526	0	0	0
T86	0	38	0	0
T87	0	59	0	0
T89	0	41	0	0
T104	0	48	0	0
T106	0	43	0	0
T120	0	203	0	0
T167	403	0	0	0
T185	0	40	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9355557	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	19	0	0
T26	497	0	0	0
T34	22223	0	0	0
T35	27601	0	0	0
T38	898	1	0	0
T43	0	1	0	0
T71	492	0	0	0
T74	422	0	0	0
T75	502	0	0	0
T76	502	0	0	0
T77	526	0	0	0
T87	0	2	0	0
T163	0	1	0	0
T167	403	0	0	0
T193	0	1	0	0
T194	0	1	0	0
T195	0	2	0	0
T196	0	4	0	0
T197	0	1	0	0
T198	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T7,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T7,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T7,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T39
1	0	Covered	T4,T13,T2
1	1	Covered	T1,T7,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T39
0	1	Covered	T81,T199,T200
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T39
0	1	Covered	T1,T7,T44
1	0	Covered	T55,T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T39
1	-	Covered	T1,T7,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T39
DetectSt	168	Covered	T1,T7,T39
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T7,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T39
DebounceSt->IdleSt	163	Covered	T163,T199,T201
DetectSt->IdleSt	186	Covered	T81,T199,T200
DetectSt->StableSt	191	Covered	T1,T7,T39
IdleSt->DebounceSt	148	Covered	T1,T7,T39
StableSt->IdleSt	206	Covered	T1,T7,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T39
0	1	Covered	T1,T7,T39
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T39
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T163,T199,T201
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T39
DetectSt	-	-	-	-	1	-	-	Covered	T81,T199,T200
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T44
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10081786	161	0	0
CntIncr_A	10081786	46754	0	0
CntNoWrap_A	10081786	9352790	0	0
DetectStDropOut_A	10081786	4	0	0
DetectedOut_A	10081786	31839	0	0
DetectedPulseOut_A	10081786	75	0	0
DisabledIdleSt_A	10081786	9170882	0	0
DisabledNoDetection_A	10081786	9173428	0	0
EnterDebounceSt_A	10081786	82	0	0
EnterDetectSt_A	10081786	79	0	0
EnterStableSt_A	10081786	75	0	0
PulseIsPulse_A	10081786	75	0	0
StayInStableSt	10081786	31731	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	10081786	3597	0	0
gen_low_level_sva.LowLevelEvent_A	10081786	9355557	0	0
gen_not_sticky_sva.StableStDropOut_A	10081786	40	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	161	0	0
T1	540	2	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T7	0	2	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T39	0	2	0	0
T41	0	2	0	0
T44	0	2	0	0
T51	0	6	0	0
T80	0	2	0	0
T81	0	2	0	0
T86	0	4	0	0
T101	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	46754	0	0
T1	540	10	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T7	0	59	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T39	0	83	0	0
T41	0	42	0	0
T44	0	28	0	0
T51	0	199	0	0
T80	0	30	0	0
T81	0	31	0	0
T86	0	131	0	0
T101	0	78	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9352790	0	0
T1	540	137	0	0
T2	17755	17322	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	4	0	0
T22	817	0	0	0
T23	1382	0	0	0
T41	494	0	0	0
T58	1928	0	0	0
T81	3040	1	0	0
T83	5019	0	0	0
T91	502	0	0	0
T107	12085	0	0	0
T199	0	1	0	0
T200	0	1	0	0
T201	0	1	0	0
T202	634	0	0	0
T203	1897	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	31839	0	0
T1	540	71	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T7	0	23	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T39	0	40	0	0
T41	0	43	0	0
T44	0	20	0	0
T51	0	525	0	0
T80	0	71	0	0
T86	0	194	0	0
T87	0	105	0	0
T101	0	482	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	75	0	0
T1	540	1	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T7	0	1	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T44	0	1	0	0
T51	0	3	0	0
T80	0	1	0	0
T86	0	2	0	0
T87	0	3	0	0
T101	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9170882	0	0
T1	540	3	0	0
T2	17755	17322	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9173428	0	0
T1	540	3	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	82	0	0
T1	540	1	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T7	0	1	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T44	0	1	0	0
T51	0	3	0	0
T80	0	1	0	0
T81	0	1	0	0
T86	0	2	0	0
T101	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	79	0	0
T1	540	1	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T7	0	1	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T44	0	1	0	0
T51	0	3	0	0
T80	0	1	0	0
T81	0	1	0	0
T86	0	2	0	0
T101	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	75	0	0
T1	540	1	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T7	0	1	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T44	0	1	0	0
T51	0	3	0	0
T80	0	1	0	0
T86	0	2	0	0
T87	0	3	0	0
T101	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	75	0	0
T1	540	1	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T7	0	1	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T44	0	1	0	0
T51	0	3	0	0
T80	0	1	0	0
T86	0	2	0	0
T87	0	3	0	0
T101	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	31731	0	0
T1	540	70	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T7	0	22	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T39	0	38	0	0
T41	0	41	0	0
T44	0	19	0	0
T51	0	520	0	0
T80	0	69	0	0
T86	0	192	0	0
T87	0	101	0	0
T101	0	480	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	3597	0	0
T1	540	1	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T4	2426	17	0	0
T5	405	0	0	0
T6	9065	0	0	0
T7	0	1	0	0
T13	423	3	0	0
T14	5416	0	0	0
T15	418	1	0	0
T16	425	4	0	0
T17	0	5	0	0
T25	0	3	0	0
T27	0	20	0	0
T54	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9355557	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	40	0	0
T1	540	1	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T7	0	1	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T44	0	1	0	0
T51	0	1	0	0
T86	0	2	0	0
T87	0	2	0	0
T120	0	1	0	0
T178	0	2	0	0
T185	0	1	0	0
T204	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T13
1	1	Covered	T4,T1,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T11
1	0	Covered	T4,T13,T14
1	1	Covered	T1,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T11
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T11
0	1	Covered	T1,T9,T11
1	0	Covered	T55,T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T9,T11
1	-	Covered	T1,T9,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T9,T11
DetectSt	168	Covered	T1,T9,T11
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T9,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T9,T11
DebounceSt->IdleSt	163	Covered	T41,T165,T194
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T9,T11
IdleSt->DebounceSt	148	Covered	T1,T9,T11
StableSt->IdleSt	206	Covered	T1,T9,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T9,T11
0	1	Covered	T1,T9,T11
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T11
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T13
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T41,T165,T205
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T9,T11
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T9,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T9,T11
StableSt	-	-	-	-	-	-	0	Covered	T1,T9,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10081786	140	0	0
CntIncr_A	10081786	107470	0	0
CntNoWrap_A	10081786	9352811	0	0
DetectStDropOut_A	10081786	0	0	0
DetectedOut_A	10081786	6321	0	0
DetectedPulseOut_A	10081786	67	0	0
DisabledIdleSt_A	10081786	8894986	0	0
DisabledNoDetection_A	10081786	8897536	0	0
EnterDebounceSt_A	10081786	74	0	0
EnterDetectSt_A	10081786	67	0	0
EnterStableSt_A	10081786	67	0	0
PulseIsPulse_A	10081786	67	0	0
StayInStableSt	10081786	6229	0	0
gen_high_level_sva.HighLevelEvent_A	10081786	9355557	0	0
gen_not_sticky_sva.StableStDropOut_A	10081786	40	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	140	0	0
T1	540	2	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T9	0	2	0	0
T11	0	2	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T40	0	4	0	0
T41	0	1	0	0
T42	0	2	0	0
T44	0	2	0	0
T81	0	4	0	0
T92	0	2	0	0
T202	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	107470	0	0
T1	540	10	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T9	0	26	0	0
T11	0	40220	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T40	0	146	0	0
T41	0	42	0	0
T42	0	72	0	0
T44	0	28	0	0
T81	0	62	0	0
T92	0	46	0	0
T202	0	38	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9352811	0	0
T1	540	137	0	0
T2	17755	17322	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	6321	0	0
T1	540	59	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T9	0	40	0	0
T11	0	44	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T40	0	91	0	0
T42	0	17	0	0
T44	0	24	0	0
T81	0	225	0	0
T92	0	126	0	0
T165	0	119	0	0
T202	0	169	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	67	0	0
T1	540	1	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T40	0	2	0	0
T42	0	1	0	0
T44	0	1	0	0
T81	0	2	0	0
T92	0	1	0	0
T165	0	1	0	0
T202	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	8894986	0	0
T1	540	3	0	0
T2	17755	17322	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	8897536	0	0
T1	540	3	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	74	0	0
T1	540	1	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T40	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T81	0	2	0	0
T92	0	1	0	0
T202	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	67	0	0
T1	540	1	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T40	0	2	0	0
T42	0	1	0	0
T44	0	1	0	0
T81	0	2	0	0
T92	0	1	0	0
T165	0	1	0	0
T202	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	67	0	0
T1	540	1	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T40	0	2	0	0
T42	0	1	0	0
T44	0	1	0	0
T81	0	2	0	0
T92	0	1	0	0
T165	0	1	0	0
T202	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	67	0	0
T1	540	1	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T40	0	2	0	0
T42	0	1	0	0
T44	0	1	0	0
T81	0	2	0	0
T92	0	1	0	0
T165	0	1	0	0
T202	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	6229	0	0
T1	540	58	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T9	0	39	0	0
T11	0	43	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T40	0	88	0	0
T42	0	16	0	0
T44	0	23	0	0
T81	0	222	0	0
T92	0	124	0	0
T165	0	118	0	0
T202	0	167	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9355557	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	40	0	0
T1	540	1	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T81	0	1	0	0
T86	0	3	0	0
T89	0	1	0	0
T165	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T13
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T13
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T40,T41,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T40,T41,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T40,T41,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T38,T40,T41
1	0	Covered	T4,T1,T13
1	1	Covered	T40,T41,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T40,T41,T42
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T40,T41,T42
0	1	Covered	T40,T101,T149
1	0	Covered	T55,T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T40,T41,T42
1	-	Covered	T40,T101,T149

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T40,T41,T42
DetectSt	168	Covered	T40,T41,T42
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T40,T41,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T40,T41,T42
DebounceSt->IdleSt	163	Covered	T206
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T40,T41,T42
IdleSt->DebounceSt	148	Covered	T40,T41,T42
StableSt->IdleSt	206	Covered	T40,T101,T149

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T40,T41,T42
0	1	Covered	T40,T41,T42
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T42
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T40,T41,T42
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T40,T41,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T206
DebounceSt	-	0	0	-	-	-	-	Covered	T40,T41,T42
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T40,T41,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T101,T149
StableSt	-	-	-	-	-	-	0	Covered	T40,T41,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10081786	77	0	0
CntIncr_A	10081786	65336	0	0
CntNoWrap_A	10081786	9352874	0	0
DetectStDropOut_A	10081786	0	0	0
DetectedOut_A	10081786	130927	0	0
DetectedPulseOut_A	10081786	38	0	0
DisabledIdleSt_A	10081786	9080665	0	0
DisabledNoDetection_A	10081786	9083218	0	0
EnterDebounceSt_A	10081786	39	0	0
EnterDetectSt_A	10081786	38	0	0
EnterStableSt_A	10081786	38	0	0
PulseIsPulse_A	10081786	38	0	0
StayInStableSt	10081786	130866	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	10081786	7107	0	0
gen_low_level_sva.LowLevelEvent_A	10081786	9355557	0	0
gen_not_sticky_sva.StableStDropOut_A	10081786	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	77	0	0
T39	14685	0	0	0
T40	856	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T46	2524	0	0	0
T55	0	2	0	0
T72	498	0	0	0
T78	501	0	0	0
T79	522	0	0	0
T89	0	4	0	0
T101	0	2	0	0
T106	0	2	0	0
T149	0	2	0	0
T178	0	2	0	0
T185	0	2	0	0
T207	402	0	0	0
T208	613	0	0	0
T209	422	0	0	0
T210	525	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	65336	0	0
T39	14685	0	0	0
T40	856	73	0	0
T41	0	42	0	0
T42	0	72	0	0
T46	2524	0	0	0
T55	0	15	0	0
T72	498	0	0	0
T78	501	0	0	0
T79	522	0	0	0
T89	0	100	0	0
T101	0	78	0	0
T106	0	83	0	0
T149	0	73	0	0
T178	0	66	0	0
T185	0	73	0	0
T207	402	0	0	0
T208	613	0	0	0
T209	422	0	0	0
T210	525	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9352874	0	0
T1	540	139	0	0
T2	17755	17322	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	130927	0	0
T39	14685	0	0	0
T40	856	54	0	0
T41	0	41	0	0
T42	0	295	0	0
T46	2524	0	0	0
T55	0	1	0	0
T72	498	0	0	0
T78	501	0	0	0
T79	522	0	0	0
T89	0	90	0	0
T101	0	60	0	0
T106	0	41	0	0
T149	0	115	0	0
T178	0	275	0	0
T185	0	39	0	0
T207	402	0	0	0
T208	613	0	0	0
T209	422	0	0	0
T210	525	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	38	0	0
T39	14685	0	0	0
T40	856	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T46	2524	0	0	0
T55	0	1	0	0
T72	498	0	0	0
T78	501	0	0	0
T79	522	0	0	0
T89	0	2	0	0
T101	0	1	0	0
T106	0	1	0	0
T149	0	1	0	0
T178	0	1	0	0
T185	0	1	0	0
T207	402	0	0	0
T208	613	0	0	0
T209	422	0	0	0
T210	525	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9080665	0	0
T1	540	139	0	0
T2	17755	17322	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9083218	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	39	0	0
T39	14685	0	0	0
T40	856	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T46	2524	0	0	0
T55	0	1	0	0
T72	498	0	0	0
T78	501	0	0	0
T79	522	0	0	0
T89	0	2	0	0
T101	0	1	0	0
T106	0	1	0	0
T149	0	1	0	0
T178	0	1	0	0
T185	0	1	0	0
T207	402	0	0	0
T208	613	0	0	0
T209	422	0	0	0
T210	525	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	38	0	0
T39	14685	0	0	0
T40	856	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T46	2524	0	0	0
T55	0	1	0	0
T72	498	0	0	0
T78	501	0	0	0
T79	522	0	0	0
T89	0	2	0	0
T101	0	1	0	0
T106	0	1	0	0
T149	0	1	0	0
T178	0	1	0	0
T185	0	1	0	0
T207	402	0	0	0
T208	613	0	0	0
T209	422	0	0	0
T210	525	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	38	0	0
T39	14685	0	0	0
T40	856	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T46	2524	0	0	0
T55	0	1	0	0
T72	498	0	0	0
T78	501	0	0	0
T79	522	0	0	0
T89	0	2	0	0
T101	0	1	0	0
T106	0	1	0	0
T149	0	1	0	0
T178	0	1	0	0
T185	0	1	0	0
T207	402	0	0	0
T208	613	0	0	0
T209	422	0	0	0
T210	525	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	38	0	0
T39	14685	0	0	0
T40	856	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T46	2524	0	0	0
T55	0	1	0	0
T72	498	0	0	0
T78	501	0	0	0
T79	522	0	0	0
T89	0	2	0	0
T101	0	1	0	0
T106	0	1	0	0
T149	0	1	0	0
T178	0	1	0	0
T185	0	1	0	0
T207	402	0	0	0
T208	613	0	0	0
T209	422	0	0	0
T210	525	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	130866	0	0
T39	14685	0	0	0
T40	856	53	0	0
T41	0	39	0	0
T42	0	293	0	0
T46	2524	0	0	0
T72	498	0	0	0
T78	501	0	0	0
T79	522	0	0	0
T89	0	86	0	0
T101	0	59	0	0
T106	0	39	0	0
T120	0	79	0	0
T149	0	114	0	0
T178	0	273	0	0
T185	0	38	0	0
T207	402	0	0	0
T208	613	0	0	0
T209	422	0	0	0
T210	525	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	7107	0	0
T1	540	1	0	0
T2	17755	32	0	0
T3	9207	14	0	0
T4	2426	19	0	0
T5	405	0	0	0
T6	9065	25	0	0
T13	423	2	0	0
T14	5416	28	0	0
T15	418	1	0	0
T16	425	2	0	0
T17	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9355557	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	13	0	0
T39	14685	0	0	0
T40	856	1	0	0
T46	2524	0	0	0
T72	498	0	0	0
T78	501	0	0	0
T79	522	0	0	0
T101	0	1	0	0
T120	0	1	0	0
T149	0	1	0	0
T163	0	2	0	0
T185	0	1	0	0
T194	0	1	0	0
T196	0	1	0	0
T199	0	1	0	0
T207	402	0	0	0
T208	613	0	0	0
T209	422	0	0	0
T210	525	0	0	0
T211	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T13
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T11,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T11,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T11,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T43
1	0	Covered	T4,T5,T13
1	1	Covered	T1,T11,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T43
0	1	Covered	T81,T101,T104
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T43
0	1	Covered	T1,T11,T43
1	0	Covered	T55,T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T11,T43
1	-	Covered	T1,T11,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T11,T43
DetectSt	168	Covered	T1,T11,T43
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T11,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T11,T43
DebounceSt->IdleSt	163	Covered	T81,T194
DetectSt->IdleSt	186	Covered	T81,T101,T104
DetectSt->StableSt	191	Covered	T1,T11,T43
IdleSt->DebounceSt	148	Covered	T1,T11,T43
StableSt->IdleSt	206	Covered	T1,T11,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T11,T43
0	1	Covered	T1,T11,T43
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T11,T43
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T11,T43
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T11,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T81
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T11,T43
DetectSt	-	-	-	-	1	-	-	Covered	T81,T101,T104
DetectSt	-	-	-	-	0	1	-	Covered	T1,T11,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T11,T43
StableSt	-	-	-	-	-	-	0	Covered	T1,T11,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10081786	137	0	0
CntIncr_A	10081786	236057	0	0
CntNoWrap_A	10081786	9352814	0	0
DetectStDropOut_A	10081786	4	0	0
DetectedOut_A	10081786	93513	0	0
DetectedPulseOut_A	10081786	64	0	0
DisabledIdleSt_A	10081786	8601785	0	0
DisabledNoDetection_A	10081786	8604334	0	0
EnterDebounceSt_A	10081786	70	0	0
EnterDetectSt_A	10081786	68	0	0
EnterStableSt_A	10081786	64	0	0
PulseIsPulse_A	10081786	64	0	0
StayInStableSt	10081786	93428	0	0
gen_high_level_sva.HighLevelEvent_A	10081786	9355557	0	0
gen_not_sticky_sva.StableStDropOut_A	10081786	41	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	137	0	0
T1	540	2	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T11	0	2	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T42	0	2	0	0
T43	0	4	0	0
T44	0	4	0	0
T51	0	4	0	0
T80	0	2	0	0
T81	0	5	0	0
T101	0	6	0	0
T212	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	236057	0	0
T1	540	10	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T11	0	40220	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T42	0	72	0	0
T43	0	124	0	0
T44	0	56	0	0
T51	0	118	0	0
T80	0	30	0	0
T81	0	93	0	0
T101	0	234	0	0
T212	0	51	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9352814	0	0
T1	540	137	0	0
T2	17755	17322	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	4	0	0
T22	817	0	0	0
T23	1382	0	0	0
T41	494	0	0	0
T58	1928	0	0	0
T81	3040	1	0	0
T83	5019	0	0	0
T91	502	0	0	0
T101	0	1	0	0
T104	0	1	0	0
T107	12085	0	0	0
T200	0	1	0	0
T202	634	0	0	0
T203	1897	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	93513	0	0
T1	540	6	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T11	0	23505	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T42	0	38	0	0
T43	0	341	0	0
T44	0	69	0	0
T51	0	198	0	0
T80	0	71	0	0
T81	0	73	0	0
T101	0	67	0	0
T212	0	20	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	64	0	0
T1	540	1	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T11	0	1	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T51	0	2	0	0
T80	0	1	0	0
T81	0	1	0	0
T101	0	2	0	0
T212	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	8601785	0	0
T1	540	3	0	0
T2	17755	17322	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	8604334	0	0
T1	540	3	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	70	0	0
T1	540	1	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T11	0	1	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T51	0	2	0	0
T80	0	1	0	0
T81	0	3	0	0
T101	0	3	0	0
T212	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	68	0	0
T1	540	1	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T11	0	1	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T51	0	2	0	0
T80	0	1	0	0
T81	0	2	0	0
T101	0	3	0	0
T212	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	64	0	0
T1	540	1	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T11	0	1	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T51	0	2	0	0
T80	0	1	0	0
T81	0	1	0	0
T101	0	2	0	0
T212	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	64	0	0
T1	540	1	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T11	0	1	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T51	0	2	0	0
T80	0	1	0	0
T81	0	1	0	0
T101	0	2	0	0
T212	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	93428	0	0
T1	540	5	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T11	0	23504	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T42	0	36	0	0
T43	0	338	0	0
T44	0	66	0	0
T51	0	195	0	0
T80	0	69	0	0
T81	0	71	0	0
T101	0	64	0	0
T212	0	19	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9355557	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	41	0	0
T1	540	1	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T11	0	1	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T51	0	1	0	0
T86	0	3	0	0
T101	0	1	0	0
T129	0	1	0	0
T149	0	1	0	0
T212	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T13
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T11,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T11,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T11,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T38
1	0	Covered	T4,T5,T13
1	1	Covered	T1,T11,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T40
0	1	Not Covered
1	0	Covered	T55

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T40
0	1	Covered	T39,T43,T81
1	0	Covered	T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T11,T40
1	-	Covered	T39,T43,T81

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T11,T40
DetectSt	168	Covered	T1,T11,T40
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T11,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T11,T40
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Covered	T55
DetectSt->StableSt	191	Covered	T1,T11,T40
IdleSt->DebounceSt	148	Covered	T1,T11,T40
StableSt->IdleSt	206	Covered	T11,T39,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T11,T40
0	1	Covered	T1,T11,T40
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T11,T40
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T11,T40
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T11,T40
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T11,T40
DetectSt	-	-	-	-	1	-	-	Covered	T55
DetectSt	-	-	-	-	0	1	-	Covered	T1,T11,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T39,T43,T81
StableSt	-	-	-	-	-	-	0	Covered	T1,T11,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10081786	86	0	0
CntIncr_A	10081786	42184	0	0
CntNoWrap_A	10081786	9352865	0	0
DetectStDropOut_A	10081786	0	0	0
DetectedOut_A	10081786	83417	0	0
DetectedPulseOut_A	10081786	42	0	0
DisabledIdleSt_A	10081786	8857846	0	0
DisabledNoDetection_A	10081786	8860392	0	0
EnterDebounceSt_A	10081786	43	0	0
EnterDetectSt_A	10081786	43	0	0
EnterStableSt_A	10081786	42	0	0
PulseIsPulse_A	10081786	42	0	0
StayInStableSt	10081786	83354	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	10081786	6761	0	0
gen_low_level_sva.LowLevelEvent_A	10081786	9355557	0	0
gen_not_sticky_sva.StableStDropOut_A	10081786	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	86	0	0
T1	540	2	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T11	0	2	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T39	0	2	0	0
T40	0	2	0	0
T43	0	2	0	0
T44	0	2	0	0
T51	0	2	0	0
T81	0	4	0	0
T101	0	4	0	0
T202	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	42184	0	0
T1	540	10	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T11	0	40220	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T39	0	83	0	0
T40	0	73	0	0
T43	0	62	0	0
T44	0	28	0	0
T51	0	59	0	0
T81	0	62	0	0
T101	0	156	0	0
T202	0	38	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9352865	0	0
T1	540	137	0	0
T2	17755	17322	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	83417	0	0
T1	540	104	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T11	0	80523	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T39	0	66	0	0
T40	0	47	0	0
T43	0	39	0	0
T44	0	87	0	0
T51	0	130	0	0
T81	0	88	0	0
T101	0	100	0	0
T202	0	11	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	42	0	0
T1	540	1	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T11	0	1	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T51	0	1	0	0
T81	0	2	0	0
T101	0	2	0	0
T202	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	8857846	0	0
T1	540	3	0	0
T2	17755	17322	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	8860392	0	0
T1	540	3	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	43	0	0
T1	540	1	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T11	0	1	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T51	0	1	0	0
T81	0	2	0	0
T101	0	2	0	0
T202	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	43	0	0
T1	540	1	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T11	0	1	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T51	0	1	0	0
T81	0	2	0	0
T101	0	2	0	0
T202	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	42	0	0
T1	540	1	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T11	0	1	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T51	0	1	0	0
T81	0	2	0	0
T101	0	2	0	0
T202	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	42	0	0
T1	540	1	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T11	0	1	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T51	0	1	0	0
T81	0	2	0	0
T101	0	2	0	0
T202	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	83354	0	0
T1	540	102	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T11	0	80521	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T39	0	65	0	0
T40	0	45	0	0
T43	0	38	0	0
T44	0	86	0	0
T51	0	129	0	0
T81	0	86	0	0
T101	0	98	0	0
T202	0	10	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	6761	0	0
T1	540	1	0	0
T2	17755	22	0	0
T3	9207	11	0	0
T4	2426	16	0	0
T5	405	1	0	0
T6	9065	26	0	0
T13	423	2	0	0
T14	5416	32	0	0
T15	418	1	0	0
T16	425	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9355557	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	20	0	0
T33	565	0	0	0
T36	18651	0	0	0
T39	14685	1	0	0
T43	978	1	0	0
T44	0	1	0	0
T46	2524	0	0	0
T51	0	1	0	0
T57	16330	0	0	0
T64	422	0	0	0
T65	658	0	0	0
T66	491	0	0	0
T67	524	0	0	0
T81	0	2	0	0
T86	0	2	0	0
T87	0	1	0	0
T101	0	2	0	0
T196	0	1	0	0
T202	0	1	0	0