Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T13
1	1	Covered	T4,T1,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T7,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T7,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T7,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T38
1	0	Covered	T4,T13,T14
1	1	Covered	T1,T7,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T38
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T38
0	1	Covered	T1,T38,T40
1	0	Covered	T55,T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T38
1	-	Covered	T1,T38,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T38
DetectSt	168	Covered	T1,T7,T38
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T7,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T38
DebounceSt->IdleSt	163	Covered	T41,T101,T204
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T7,T38
IdleSt->DebounceSt	148	Covered	T1,T7,T38
StableSt->IdleSt	206	Covered	T1,T38,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T38
0	1	Covered	T1,T7,T38
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T38
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T13
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T41,T101,T204
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T38
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T38,T40
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10081786	159	0	0
CntIncr_A	10081786	154281	0	0
CntNoWrap_A	10081786	9352792	0	0
DetectStDropOut_A	10081786	0	0	0
DetectedOut_A	10081786	57724	0	0
DetectedPulseOut_A	10081786	78	0	0
DisabledIdleSt_A	10081786	9039929	0	0
DisabledNoDetection_A	10081786	9042470	0	0
EnterDebounceSt_A	10081786	81	0	0
EnterDetectSt_A	10081786	78	0	0
EnterStableSt_A	10081786	78	0	0
PulseIsPulse_A	10081786	78	0	0
StayInStableSt	10081786	57610	0	0
gen_high_level_sva.HighLevelEvent_A	10081786	9355557	0	0
gen_not_sticky_sva.StableStDropOut_A	10081786	40	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	159	0	0
T1	540	2	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T7	0	2	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	4	0	0
T41	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0
T145	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	154281	0	0
T1	540	10	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T7	0	59	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T38	0	97	0	0
T39	0	83	0	0
T40	0	146	0	0
T41	0	42	0	0
T43	0	62	0	0
T44	0	28	0	0
T45	0	29	0	0
T145	0	73	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9352792	0	0
T1	540	137	0	0
T2	17755	17322	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	57724	0	0
T1	540	5	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T7	0	158	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T38	0	154	0	0
T39	0	44	0	0
T40	0	184	0	0
T43	0	43	0	0
T44	0	162	0	0
T45	0	186	0	0
T51	0	171	0	0
T145	0	1	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	78	0	0
T1	540	1	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T7	0	1	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T51	0	2	0	0
T145	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9039929	0	0
T1	540	3	0	0
T2	17755	17322	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9042470	0	0
T1	540	3	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	81	0	0
T1	540	1	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T7	0	1	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T145	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	78	0	0
T1	540	1	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T7	0	1	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T51	0	2	0	0
T145	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	78	0	0
T1	540	1	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T7	0	1	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T51	0	2	0	0
T145	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	78	0	0
T1	540	1	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T7	0	1	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T51	0	2	0	0
T145	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	57610	0	0
T1	540	4	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T7	0	156	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T38	0	153	0	0
T39	0	43	0	0
T40	0	181	0	0
T43	0	42	0	0
T44	0	160	0	0
T45	0	184	0	0
T51	0	169	0	0
T101	0	212	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9355557	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	40	0	0
T1	540	1	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T5	405	0	0	0
T6	9065	0	0	0
T13	423	0	0	0
T14	5416	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T51	0	2	0	0
T89	0	1	0	0
T101	0	1	0	0
T145	0	1	0	0
T149	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T13
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T13
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T9,T11,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T9,T11,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T9,T11,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T39
1	0	Covered	T4,T1,T13
1	1	Covered	T9,T11,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T39
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T39
0	1	Covered	T9,T42,T51
1	0	Covered	T55,T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T11,T39
1	-	Covered	T9,T42,T51

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T11,T39
DetectSt	168	Covered	T9,T11,T39
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T9,T11,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T11,T39
DebounceSt->IdleSt	163	Covered	T87,T89
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T9,T11,T39
IdleSt->DebounceSt	148	Covered	T9,T11,T39
StableSt->IdleSt	206	Covered	T9,T11,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T11,T39
0	1	Covered	T9,T11,T39
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T39
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T11,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T11,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T87,T89
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T11,T39
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T9,T11,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T42,T51
StableSt	-	-	-	-	-	-	0	Covered	T9,T11,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10081786	80	0	0
CntIncr_A	10081786	42224	0	0
CntNoWrap_A	10081786	9352871	0	0
DetectStDropOut_A	10081786	0	0	0
DetectedOut_A	10081786	83282	0	0
DetectedPulseOut_A	10081786	39	0	0
DisabledIdleSt_A	10081786	9022511	0	0
DisabledNoDetection_A	10081786	9025065	0	0
EnterDebounceSt_A	10081786	41	0	0
EnterDetectSt_A	10081786	39	0	0
EnterStableSt_A	10081786	39	0	0
PulseIsPulse_A	10081786	39	0	0
StayInStableSt	10081786	83223	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	10081786	6666	0	0
gen_low_level_sva.LowLevelEvent_A	10081786	9355557	0	0
gen_not_sticky_sva.StableStDropOut_A	10081786	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	80	0	0
T9	1492	2	0	0
T10	14723	0	0	0
T11	186745	2	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	0	0	0
T39	0	2	0	0
T41	0	2	0	0
T42	0	4	0	0
T43	0	2	0	0
T51	0	2	0	0
T74	422	0	0	0
T75	502	0	0	0
T86	0	2	0	0
T87	0	1	0	0
T145	0	2	0	0
T167	403	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	42224	0	0
T9	1492	26	0	0
T10	14723	0	0	0
T11	186745	40220	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	0	0	0
T39	0	83	0	0
T41	0	42	0	0
T42	0	144	0	0
T43	0	62	0	0
T51	0	70	0	0
T74	422	0	0	0
T75	502	0	0	0
T86	0	87	0	0
T87	0	19	0	0
T145	0	73	0	0
T167	403	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9352871	0	0
T1	540	139	0	0
T2	17755	17322	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	83282	0	0
T9	1492	69	0	0
T10	14723	0	0	0
T11	186745	80524	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	0	0	0
T39	0	314	0	0
T41	0	41	0	0
T42	0	82	0	0
T43	0	284	0	0
T51	0	236	0	0
T74	422	0	0	0
T75	502	0	0	0
T86	0	41	0	0
T145	0	41	0	0
T149	0	40	0	0
T167	403	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	39	0	0
T9	1492	1	0	0
T10	14723	0	0	0
T11	186745	1	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T51	0	1	0	0
T74	422	0	0	0
T75	502	0	0	0
T86	0	1	0	0
T145	0	1	0	0
T149	0	1	0	0
T167	403	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9022511	0	0
T1	540	139	0	0
T2	17755	17322	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9025065	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	41	0	0
T9	1492	1	0	0
T10	14723	0	0	0
T11	186745	1	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T51	0	1	0	0
T74	422	0	0	0
T75	502	0	0	0
T86	0	1	0	0
T87	0	1	0	0
T145	0	1	0	0
T167	403	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	39	0	0
T9	1492	1	0	0
T10	14723	0	0	0
T11	186745	1	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T51	0	1	0	0
T74	422	0	0	0
T75	502	0	0	0
T86	0	1	0	0
T145	0	1	0	0
T149	0	1	0	0
T167	403	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	39	0	0
T9	1492	1	0	0
T10	14723	0	0	0
T11	186745	1	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T51	0	1	0	0
T74	422	0	0	0
T75	502	0	0	0
T86	0	1	0	0
T145	0	1	0	0
T149	0	1	0	0
T167	403	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	39	0	0
T9	1492	1	0	0
T10	14723	0	0	0
T11	186745	1	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T51	0	1	0	0
T74	422	0	0	0
T75	502	0	0	0
T86	0	1	0	0
T145	0	1	0	0
T149	0	1	0	0
T167	403	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	83223	0	0
T9	1492	68	0	0
T10	14723	0	0	0
T11	186745	80522	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	0	0	0
T39	0	312	0	0
T41	0	39	0	0
T42	0	79	0	0
T43	0	282	0	0
T51	0	235	0	0
T74	422	0	0	0
T75	502	0	0	0
T86	0	39	0	0
T145	0	39	0	0
T149	0	39	0	0
T167	403	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	6666	0	0
T1	540	1	0	0
T2	17755	32	0	0
T3	9207	11	0	0
T4	2426	16	0	0
T5	405	0	0	0
T6	9065	26	0	0
T13	423	3	0	0
T14	5416	24	0	0
T15	418	3	0	0
T16	425	2	0	0
T17	0	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9355557	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	17	0	0
T9	1492	1	0	0
T10	14723	0	0	0
T11	186745	0	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	0	0	0
T42	0	1	0	0
T51	0	1	0	0
T74	422	0	0	0
T75	502	0	0	0
T106	0	1	0	0
T149	0	1	0	0
T167	403	0	0	0
T194	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T211	0	1	0	0
T213	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T11,T39,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T11,T39,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T11,T39,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T39,T41
1	0	Covered	T4,T1,T5
1	1	Covered	T11,T39,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T39,T41
0	1	Covered	T163,T196
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T39,T41
0	1	Covered	T11,T39,T45
1	0	Covered	T55,T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T39,T41
1	-	Covered	T11,T39,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T39,T41
DetectSt	168	Covered	T11,T39,T41
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T11,T39,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T39,T41
DebounceSt->IdleSt	163	Covered	T45,T164,T194
DetectSt->IdleSt	186	Covered	T163,T196
DetectSt->StableSt	191	Covered	T11,T39,T41
IdleSt->DebounceSt	148	Covered	T11,T39,T41
StableSt->IdleSt	206	Covered	T11,T39,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T39,T41
0	1	Covered	T11,T39,T41
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T39,T41
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T39,T41
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T39,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T45,T164,T163
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T39,T41
DetectSt	-	-	-	-	1	-	-	Covered	T163,T196
DetectSt	-	-	-	-	0	1	-	Covered	T11,T39,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T39,T45
StableSt	-	-	-	-	-	-	0	Covered	T11,T39,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10081786	127	0	0
CntIncr_A	10081786	83939	0	0
CntNoWrap_A	10081786	9352824	0	0
DetectStDropOut_A	10081786	2	0	0
DetectedOut_A	10081786	4426	0	0
DetectedPulseOut_A	10081786	59	0	0
DisabledIdleSt_A	10081786	9151590	0	0
DisabledNoDetection_A	10081786	9154141	0	0
EnterDebounceSt_A	10081786	67	0	0
EnterDetectSt_A	10081786	61	0	0
EnterStableSt_A	10081786	59	0	0
PulseIsPulse_A	10081786	59	0	0
StayInStableSt	10081786	4342	0	0
gen_high_level_sva.HighLevelEvent_A	10081786	9355557	0	0
gen_not_sticky_sva.StableStDropOut_A	10081786	32	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	127	0	0
T11	186745	4	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T35	27601	0	0	0
T38	898	0	0	0
T39	0	2	0	0
T41	0	2	0	0
T45	0	5	0	0
T51	0	2	0	0
T74	422	0	0	0
T75	502	0	0	0
T76	502	0	0	0
T86	0	4	0	0
T87	0	4	0	0
T89	0	2	0	0
T101	0	4	0	0
T164	0	5	0	0
T167	403	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	83939	0	0
T11	186745	80440	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T35	27601	0	0	0
T38	898	0	0	0
T39	0	83	0	0
T41	0	42	0	0
T45	0	87	0	0
T51	0	70	0	0
T74	422	0	0	0
T75	502	0	0	0
T76	502	0	0	0
T86	0	88	0	0
T87	0	38	0	0
T89	0	57	0	0
T101	0	156	0	0
T164	0	198	0	0
T167	403	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9352824	0	0
T1	540	139	0	0
T2	17755	17322	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	2	0	0
T163	21485	1	0	0
T168	9954	0	0	0
T169	503	0	0	0
T170	422	0	0	0
T171	728	0	0	0
T172	526	0	0	0
T173	924	0	0	0
T174	414	0	0	0
T175	544	0	0	0
T176	675	0	0	0
T196	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	4426	0	0
T11	186745	82	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T35	27601	0	0	0
T38	898	0	0	0
T39	0	66	0	0
T41	0	43	0	0
T45	0	80	0	0
T51	0	39	0	0
T74	422	0	0	0
T75	502	0	0	0
T76	502	0	0	0
T86	0	99	0	0
T87	0	220	0	0
T89	0	43	0	0
T101	0	187	0	0
T164	0	85	0	0
T167	403	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	59	0	0
T11	186745	2	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T35	27601	0	0	0
T38	898	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T45	0	2	0	0
T51	0	1	0	0
T74	422	0	0	0
T75	502	0	0	0
T76	502	0	0	0
T86	0	2	0	0
T87	0	2	0	0
T89	0	1	0	0
T101	0	2	0	0
T164	0	2	0	0
T167	403	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9151590	0	0
T1	540	139	0	0
T2	17755	17322	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9154141	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	67	0	0
T11	186745	2	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T35	27601	0	0	0
T38	898	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T45	0	3	0	0
T51	0	1	0	0
T74	422	0	0	0
T75	502	0	0	0
T76	502	0	0	0
T86	0	2	0	0
T87	0	2	0	0
T89	0	1	0	0
T101	0	2	0	0
T164	0	3	0	0
T167	403	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	61	0	0
T11	186745	2	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T35	27601	0	0	0
T38	898	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T45	0	2	0	0
T51	0	1	0	0
T74	422	0	0	0
T75	502	0	0	0
T76	502	0	0	0
T86	0	2	0	0
T87	0	2	0	0
T89	0	1	0	0
T101	0	2	0	0
T164	0	2	0	0
T167	403	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	59	0	0
T11	186745	2	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T35	27601	0	0	0
T38	898	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T45	0	2	0	0
T51	0	1	0	0
T74	422	0	0	0
T75	502	0	0	0
T76	502	0	0	0
T86	0	2	0	0
T87	0	2	0	0
T89	0	1	0	0
T101	0	2	0	0
T164	0	2	0	0
T167	403	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	59	0	0
T11	186745	2	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T35	27601	0	0	0
T38	898	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T45	0	2	0	0
T51	0	1	0	0
T74	422	0	0	0
T75	502	0	0	0
T76	502	0	0	0
T86	0	2	0	0
T87	0	2	0	0
T89	0	1	0	0
T101	0	2	0	0
T164	0	2	0	0
T167	403	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	4342	0	0
T11	186745	79	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T35	27601	0	0	0
T38	898	0	0	0
T39	0	65	0	0
T41	0	41	0	0
T45	0	77	0	0
T51	0	38	0	0
T74	422	0	0	0
T75	502	0	0	0
T76	502	0	0	0
T86	0	96	0	0
T87	0	217	0	0
T89	0	41	0	0
T101	0	184	0	0
T164	0	82	0	0
T167	403	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9355557	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	32	0	0
T11	186745	1	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T35	27601	0	0	0
T38	898	0	0	0
T39	0	1	0	0
T45	0	1	0	0
T51	0	1	0	0
T74	422	0	0	0
T75	502	0	0	0
T76	502	0	0	0
T86	0	1	0	0
T87	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0
T129	0	1	0	0
T164	0	1	0	0
T167	403	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T7,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T7,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T7,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T9,T11
1	0	Covered	T4,T1,T5
1	1	Covered	T7,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T38
0	1	Covered	T11
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T38
0	1	Covered	T51,T106,T204
1	0	Covered	T55,T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T9,T38
1	-	Covered	T51,T106,T204

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T9,T11
DetectSt	168	Covered	T7,T9,T11
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T7,T9,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T9,T11
DebounceSt->IdleSt	163	Covered	T101,T149
DetectSt->IdleSt	186	Covered	T11
DetectSt->StableSt	191	Covered	T7,T9,T38
IdleSt->DebounceSt	148	Covered	T7,T9,T11
StableSt->IdleSt	206	Covered	T9,T39,T51

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T9,T11
0	1	Covered	T7,T9,T11
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T11
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T101,T149
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T9,T11
DetectSt	-	-	-	-	1	-	-	Covered	T11
DetectSt	-	-	-	-	0	1	-	Covered	T7,T9,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T51,T106,T55
StableSt	-	-	-	-	-	-	0	Covered	T7,T9,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10081786	76	0	0
CntIncr_A	10081786	84743	0	0
CntNoWrap_A	10081786	9352875	0	0
DetectStDropOut_A	10081786	1	0	0
DetectedOut_A	10081786	28030	0	0
DetectedPulseOut_A	10081786	36	0	0
DisabledIdleSt_A	10081786	8991750	0	0
DisabledNoDetection_A	10081786	8994309	0	0
EnterDebounceSt_A	10081786	39	0	0
EnterDetectSt_A	10081786	37	0	0
EnterStableSt_A	10081786	36	0	0
PulseIsPulse_A	10081786	36	0	0
StayInStableSt	10081786	27973	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	10081786	6660	0	0
gen_low_level_sva.LowLevelEvent_A	10081786	9355557	0	0
gen_not_sticky_sva.StableStDropOut_A	10081786	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	76	0	0
T7	810	2	0	0
T8	18502	0	0	0
T9	1492	2	0	0
T10	14723	0	0	0
T11	186745	2	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	2	0	0
T39	0	2	0	0
T44	0	2	0	0
T51	0	4	0	0
T74	422	0	0	0
T80	0	2	0	0
T101	0	1	0	0
T149	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	84743	0	0
T7	810	59	0	0
T8	18502	0	0	0
T9	1492	26	0	0
T10	14723	0	0	0
T11	186745	40220	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	97	0	0
T39	0	83	0	0
T44	0	28	0	0
T51	0	118	0	0
T74	422	0	0	0
T80	0	30	0	0
T101	0	78	0	0
T149	0	73	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9352875	0	0
T1	540	139	0	0
T2	17755	17322	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	1	0	0
T11	186745	1	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T35	27601	0	0	0
T38	898	0	0	0
T74	422	0	0	0
T75	502	0	0	0
T76	502	0	0	0
T167	403	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	28030	0	0
T7	810	158	0	0
T8	18502	0	0	0
T9	1492	150	0	0
T10	14723	0	0	0
T11	186745	0	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	42	0	0
T39	0	41	0	0
T44	0	92	0	0
T51	0	86	0	0
T74	422	0	0	0
T80	0	40	0	0
T100	0	63	0	0
T106	0	23	0	0
T129	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	36	0	0
T7	810	1	0	0
T8	18502	0	0	0
T9	1492	1	0	0
T10	14723	0	0	0
T11	186745	0	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	1	0	0
T39	0	1	0	0
T44	0	1	0	0
T51	0	2	0	0
T74	422	0	0	0
T80	0	1	0	0
T100	0	1	0	0
T106	0	1	0	0
T129	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	8991750	0	0
T1	540	139	0	0
T2	17755	17322	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	8994309	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	39	0	0
T7	810	1	0	0
T8	18502	0	0	0
T9	1492	1	0	0
T10	14723	0	0	0
T11	186745	1	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	1	0	0
T39	0	1	0	0
T44	0	1	0	0
T51	0	2	0	0
T74	422	0	0	0
T80	0	1	0	0
T101	0	1	0	0
T149	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	37	0	0
T7	810	1	0	0
T8	18502	0	0	0
T9	1492	1	0	0
T10	14723	0	0	0
T11	186745	1	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	1	0	0
T39	0	1	0	0
T44	0	1	0	0
T51	0	2	0	0
T74	422	0	0	0
T80	0	1	0	0
T100	0	1	0	0
T129	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	36	0	0
T7	810	1	0	0
T8	18502	0	0	0
T9	1492	1	0	0
T10	14723	0	0	0
T11	186745	0	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	1	0	0
T39	0	1	0	0
T44	0	1	0	0
T51	0	2	0	0
T74	422	0	0	0
T80	0	1	0	0
T100	0	1	0	0
T106	0	1	0	0
T129	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	36	0	0
T7	810	1	0	0
T8	18502	0	0	0
T9	1492	1	0	0
T10	14723	0	0	0
T11	186745	0	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	1	0	0
T39	0	1	0	0
T44	0	1	0	0
T51	0	2	0	0
T74	422	0	0	0
T80	0	1	0	0
T100	0	1	0	0
T106	0	1	0	0
T129	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	27973	0	0
T7	810	156	0	0
T8	18502	0	0	0
T9	1492	148	0	0
T10	14723	0	0	0
T11	186745	0	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	40	0	0
T39	0	39	0	0
T44	0	90	0	0
T51	0	83	0	0
T74	422	0	0	0
T80	0	38	0	0
T100	0	61	0	0
T106	0	22	0	0
T129	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	6660	0	0
T1	540	1	0	0
T2	17755	28	0	0
T3	9207	13	0	0
T4	2426	19	0	0
T5	405	1	0	0
T6	9065	26	0	0
T13	423	3	0	0
T14	5416	28	0	0
T15	418	2	0	0
T16	425	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9355557	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	13	0	0
T51	9387	1	0	0
T52	777	0	0	0
T106	0	1	0	0
T108	22972	0	0	0
T148	0	1	0	0
T186	13430	0	0	0
T187	675	0	0	0
T188	429	0	0	0
T189	1058	0	0	0
T190	419	0	0	0
T191	490	0	0	0
T192	402	0	0	0
T196	0	1	0	0
T197	0	1	0	0
T199	0	1	0	0
T204	0	2	0	0
T205	0	2	0	0
T214	0	1	0	0
T215	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T7,T38,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T7,T38,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T7,T38,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T38,T40
1	0	Covered	T4,T1,T5
1	1	Covered	T7,T38,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T38,T40
0	1	Covered	T199
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T38,T40
0	1	Covered	T7,T38,T40
1	0	Covered	T55,T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T38,T40
1	-	Covered	T7,T38,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T38,T40
DetectSt	168	Covered	T7,T38,T40
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T7,T38,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T38,T40
DebounceSt->IdleSt	163	Covered	T41,T100,T103
DetectSt->IdleSt	186	Covered	T199
DetectSt->StableSt	191	Covered	T7,T38,T40
IdleSt->DebounceSt	148	Covered	T7,T38,T40
StableSt->IdleSt	206	Covered	T7,T38,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T38,T40
0	1	Covered	T7,T38,T40
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T38,T40
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T38,T40
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T38,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T41,T100,T103
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T38,T40
DetectSt	-	-	-	-	1	-	-	Covered	T199
DetectSt	-	-	-	-	0	1	-	Covered	T7,T38,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T38,T40
StableSt	-	-	-	-	-	-	0	Covered	T7,T38,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10081786	130	0	0
CntIncr_A	10081786	46166	0	0
CntNoWrap_A	10081786	9352821	0	0
DetectStDropOut_A	10081786	1	0	0
DetectedOut_A	10081786	12738	0	0
DetectedPulseOut_A	10081786	61	0	0
DisabledIdleSt_A	10081786	9173900	0	0
DisabledNoDetection_A	10081786	9176450	0	0
EnterDebounceSt_A	10081786	68	0	0
EnterDetectSt_A	10081786	62	0	0
EnterStableSt_A	10081786	61	0	0
PulseIsPulse_A	10081786	61	0	0
StayInStableSt	10081786	12648	0	0
gen_high_level_sva.HighLevelEvent_A	10081786	9355557	0	0
gen_not_sticky_sva.StableStDropOut_A	10081786	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	130	0	0
T7	810	4	0	0
T8	18502	0	0	0
T9	1492	0	0	0
T10	14723	0	0	0
T11	186745	0	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	4	0	0
T39	0	2	0	0
T40	0	4	0	0
T41	0	1	0	0
T42	0	2	0	0
T51	0	4	0	0
T74	422	0	0	0
T86	0	2	0	0
T145	0	2	0	0
T212	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	46166	0	0
T7	810	118	0	0
T8	18502	0	0	0
T9	1492	0	0	0
T10	14723	0	0	0
T11	186745	0	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	194	0	0
T39	0	83	0	0
T40	0	146	0	0
T41	0	42	0	0
T42	0	72	0	0
T51	0	140	0	0
T74	422	0	0	0
T86	0	87	0	0
T145	0	73	0	0
T212	0	51	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9352821	0	0
T1	540	139	0	0
T2	17755	17322	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	1	0	0
T199	672	1	0	0
T216	502	0	0	0
T217	1731	0	0	0
T218	603	0	0	0
T219	745	0	0	0
T220	526	0	0	0
T221	503	0	0	0
T222	422	0	0	0
T223	521	0	0	0
T224	922	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	12738	0	0
T7	810	69	0	0
T8	18502	0	0	0
T9	1492	0	0	0
T10	14723	0	0	0
T11	186745	0	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	14	0	0
T39	0	315	0	0
T40	0	90	0	0
T42	0	179	0	0
T51	0	209	0	0
T74	422	0	0	0
T86	0	37	0	0
T89	0	99	0	0
T145	0	1	0	0
T212	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	61	0	0
T7	810	2	0	0
T8	18502	0	0	0
T9	1492	0	0	0
T10	14723	0	0	0
T11	186745	0	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	0	1	0	0
T51	0	2	0	0
T74	422	0	0	0
T86	0	1	0	0
T89	0	2	0	0
T145	0	1	0	0
T212	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9173900	0	0
T1	540	139	0	0
T2	17755	17322	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9176450	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	68	0	0
T7	810	2	0	0
T8	18502	0	0	0
T9	1492	0	0	0
T10	14723	0	0	0
T11	186745	0	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T51	0	2	0	0
T74	422	0	0	0
T86	0	1	0	0
T145	0	1	0	0
T212	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	62	0	0
T7	810	2	0	0
T8	18502	0	0	0
T9	1492	0	0	0
T10	14723	0	0	0
T11	186745	0	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	0	1	0	0
T51	0	2	0	0
T74	422	0	0	0
T86	0	1	0	0
T89	0	2	0	0
T145	0	1	0	0
T212	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	61	0	0
T7	810	2	0	0
T8	18502	0	0	0
T9	1492	0	0	0
T10	14723	0	0	0
T11	186745	0	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	0	1	0	0
T51	0	2	0	0
T74	422	0	0	0
T86	0	1	0	0
T89	0	2	0	0
T145	0	1	0	0
T212	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	61	0	0
T7	810	2	0	0
T8	18502	0	0	0
T9	1492	0	0	0
T10	14723	0	0	0
T11	186745	0	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	0	1	0	0
T51	0	2	0	0
T74	422	0	0	0
T86	0	1	0	0
T89	0	2	0	0
T145	0	1	0	0
T212	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	12648	0	0
T7	810	66	0	0
T8	18502	0	0	0
T9	1492	0	0	0
T10	14723	0	0	0
T11	186745	0	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	12	0	0
T39	0	313	0	0
T40	0	87	0	0
T42	0	177	0	0
T51	0	207	0	0
T74	422	0	0	0
T86	0	36	0	0
T89	0	95	0	0
T129	0	53	0	0
T212	0	38	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9355557	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	30	0	0
T7	810	1	0	0
T8	18502	0	0	0
T9	1492	0	0	0
T10	14723	0	0	0
T11	186745	0	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	2	0	0
T40	0	1	0	0
T51	0	2	0	0
T74	422	0	0	0
T86	0	1	0	0
T129	0	1	0	0
T145	0	1	0	0
T177	0	1	0	0
T225	0	2	0	0
T226	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T9,T11,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T9,T11,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T9,T11,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T38
1	0	Covered	T4,T1,T13
1	1	Covered	T9,T11,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T38
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T38
0	1	Covered	T11,T38,T43
1	0	Covered	T55,T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T11,T38
1	-	Covered	T11,T38,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T11,T38
DetectSt	168	Covered	T9,T11,T38
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T9,T11,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T11,T38
DebounceSt->IdleSt	163	Covered	T104,T205
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T9,T11,T38
IdleSt->DebounceSt	148	Covered	T9,T11,T38
StableSt->IdleSt	206	Covered	T9,T11,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T11,T38
0	1	Covered	T9,T11,T38
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T38
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T11,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T11,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T104,T205
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T11,T38
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T9,T11,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T38,T43
StableSt	-	-	-	-	-	-	0	Covered	T9,T11,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10081786	106	0	0
CntIncr_A	10081786	42885	0	0
CntNoWrap_A	10081786	9352845	0	0
DetectStDropOut_A	10081786	0	0	0
DetectedOut_A	10081786	4087	0	0
DetectedPulseOut_A	10081786	52	0	0
DisabledIdleSt_A	10081786	9146915	0	0
DisabledNoDetection_A	10081786	9149453	0	0
EnterDebounceSt_A	10081786	54	0	0
EnterDetectSt_A	10081786	52	0	0
EnterStableSt_A	10081786	52	0	0
PulseIsPulse_A	10081786	52	0	0
StayInStableSt	10081786	4005	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	10081786	7390	0	0
gen_low_level_sva.LowLevelEvent_A	10081786	9355557	0	0
gen_not_sticky_sva.StableStDropOut_A	10081786	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	106	0	0
T9	1492	2	0	0
T10	14723	0	0	0
T11	186745	2	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	4	0	0
T41	0	2	0	0
T43	0	4	0	0
T45	0	4	0	0
T74	422	0	0	0
T75	502	0	0	0
T81	0	2	0	0
T101	0	4	0	0
T145	0	2	0	0
T167	403	0	0	0
T202	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	42885	0	0
T9	1492	26	0	0
T10	14723	0	0	0
T11	186745	40220	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	194	0	0
T41	0	42	0	0
T43	0	124	0	0
T45	0	58	0	0
T74	422	0	0	0
T75	502	0	0	0
T81	0	31	0	0
T101	0	156	0	0
T145	0	73	0	0
T167	403	0	0	0
T202	0	38	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9352845	0	0
T1	540	139	0	0
T2	17755	17322	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	4087	0	0
T9	1492	42	0	0
T10	14723	0	0	0
T11	186745	43	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	84	0	0
T41	0	41	0	0
T43	0	78	0	0
T45	0	16	0	0
T74	422	0	0	0
T75	502	0	0	0
T81	0	41	0	0
T101	0	307	0	0
T145	0	41	0	0
T167	403	0	0	0
T202	0	90	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	52	0	0
T9	1492	1	0	0
T10	14723	0	0	0
T11	186745	1	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	2	0	0
T41	0	1	0	0
T43	0	2	0	0
T45	0	2	0	0
T74	422	0	0	0
T75	502	0	0	0
T81	0	1	0	0
T101	0	2	0	0
T145	0	1	0	0
T167	403	0	0	0
T202	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9146915	0	0
T1	540	139	0	0
T2	17755	17322	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9149453	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	54	0	0
T9	1492	1	0	0
T10	14723	0	0	0
T11	186745	1	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	2	0	0
T41	0	1	0	0
T43	0	2	0	0
T45	0	2	0	0
T74	422	0	0	0
T75	502	0	0	0
T81	0	1	0	0
T101	0	2	0	0
T145	0	1	0	0
T167	403	0	0	0
T202	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	52	0	0
T9	1492	1	0	0
T10	14723	0	0	0
T11	186745	1	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	2	0	0
T41	0	1	0	0
T43	0	2	0	0
T45	0	2	0	0
T74	422	0	0	0
T75	502	0	0	0
T81	0	1	0	0
T101	0	2	0	0
T145	0	1	0	0
T167	403	0	0	0
T202	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	52	0	0
T9	1492	1	0	0
T10	14723	0	0	0
T11	186745	1	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	2	0	0
T41	0	1	0	0
T43	0	2	0	0
T45	0	2	0	0
T74	422	0	0	0
T75	502	0	0	0
T81	0	1	0	0
T101	0	2	0	0
T145	0	1	0	0
T167	403	0	0	0
T202	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	52	0	0
T9	1492	1	0	0
T10	14723	0	0	0
T11	186745	1	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	2	0	0
T41	0	1	0	0
T43	0	2	0	0
T45	0	2	0	0
T74	422	0	0	0
T75	502	0	0	0
T81	0	1	0	0
T101	0	2	0	0
T145	0	1	0	0
T167	403	0	0	0
T202	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	4005	0	0
T9	1492	40	0	0
T10	14723	0	0	0
T11	186745	42	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T38	898	81	0	0
T41	0	39	0	0
T43	0	75	0	0
T45	0	14	0	0
T74	422	0	0	0
T75	502	0	0	0
T81	0	39	0	0
T101	0	304	0	0
T145	0	39	0	0
T167	403	0	0	0
T202	0	88	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	7390	0	0
T1	540	1	0	0
T2	17755	29	0	0
T3	9207	13	0	0
T4	2426	19	0	0
T5	405	0	0	0
T6	9065	26	0	0
T13	423	3	0	0
T14	5416	23	0	0
T15	418	2	0	0
T16	425	2	0	0
T17	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9355557	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	20	0	0
T11	186745	1	0	0
T12	6218	0	0	0
T26	497	0	0	0
T34	22223	0	0	0
T35	27601	0	0	0
T38	898	1	0	0
T43	0	1	0	0
T45	0	2	0	0
T74	422	0	0	0
T75	502	0	0	0
T76	502	0	0	0
T87	0	1	0	0
T101	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	403	0	0	0
T185	0	1	0	0
T204	0	1	0	0