Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T2,T6
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T14,T2,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T14,T2,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T14,T2,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T2,T6
1	0	Covered	T2,T6,T8
1	1	Covered	T14,T2,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T2,T6
0	1	Covered	T14,T83,T84
1	0	Covered	T97,T98,T153

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T8
0	1	Covered	T2,T6,T8
1	0	Covered	T55,T56,T227

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T6,T8
1	-	Covered	T2,T6,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T2,T6
DetectSt	168	Covered	T14,T2,T6
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T2,T6,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T2,T6
DebounceSt->IdleSt	163	Covered	T83,T118,T55
DetectSt->IdleSt	186	Covered	T14,T83,T84
DetectSt->StableSt	191	Covered	T2,T6,T8
IdleSt->DebounceSt	148	Covered	T14,T2,T6
StableSt->IdleSt	206	Covered	T2,T6,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T2,T6
0	1	Covered	T14,T2,T6
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T2,T6
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T14,T2,T6
IdleSt	0	-	-	-	-	-	-	Covered	T14,T2,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T56
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T2,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T83,T118,T55
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T2,T6
DetectSt	-	-	-	-	1	-	-	Covered	T14,T83,T84
DetectSt	-	-	-	-	0	1	-	Covered	T2,T6,T8
DetectSt	-	-	-	-	0	0	-	Covered	T14,T2,T6
StableSt	-	-	-	-	-	-	1	Covered	T2,T6,T8
StableSt	-	-	-	-	-	-	0	Covered	T2,T6,T8
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10081786	2782	0	0
CntIncr_A	10081786	93636	0	0
CntNoWrap_A	10081786	9350169	0	0
DetectStDropOut_A	10081786	283	0	0
DetectedOut_A	10081786	79902	0	0
DetectedPulseOut_A	10081786	955	0	0
DisabledIdleSt_A	10081786	8876110	0	0
DisabledNoDetection_A	10081786	8878528	0	0
EnterDebounceSt_A	10081786	1405	0	0
EnterDetectSt_A	10081786	1377	0	0
EnterStableSt_A	10081786	955	0	0
PulseIsPulse_A	10081786	955	0	0
StayInStableSt	10081786	78850	0	0
gen_high_event_sva.HighLevelEvent_A	10081786	9355557	0	0
gen_high_level_sva.HighLevelEvent_A	10081786	9355557	0	0
gen_not_sticky_sva.StableStDropOut_A	10081786	827	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	2782	0	0
T2	17755	24	0	0
T3	9207	0	0	0
T6	9065	52	0	0
T8	0	28	0	0
T10	0	16	0	0
T14	5416	24	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	8	0	0
T53	403	0	0	0
T57	0	20	0	0
T82	0	34	0	0
T83	0	13	0	0
T84	0	24	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	93636	0	0
T2	17755	684	0	0
T3	9207	0	0	0
T6	9065	1352	0	0
T8	0	1064	0	0
T10	0	376	0	0
T14	5416	667	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	208	0	0
T53	403	0	0	0
T57	0	800	0	0
T82	0	1037	0	0
T83	0	588	0	0
T84	0	522	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9350169	0	0
T1	540	139	0	0
T2	17755	17298	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8604	0	0
T13	423	22	0	0
T14	5416	4991	0	0
T15	418	17	0	0
T16	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	283	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T6	9065	0	0	0
T14	5416	12	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T53	403	0	0	0
T83	0	1	0	0
T84	0	12	0	0
T110	0	7	0	0
T111	0	29	0	0
T112	0	23	0	0
T113	0	12	0	0
T114	0	4	0	0
T116	0	9	0	0
T118	0	15	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	79902	0	0
T2	17755	2124	0	0
T3	9207	0	0	0
T6	9065	1661	0	0
T8	0	1906	0	0
T10	0	596	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	69	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	662	0	0
T82	0	1319	0	0
T93	0	953	0	0
T228	0	560	0	0
T229	0	6842	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	955	0	0
T2	17755	12	0	0
T3	9207	0	0	0
T6	9065	26	0	0
T8	0	14	0	0
T10	0	8	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	4	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	10	0	0
T82	0	17	0	0
T93	0	15	0	0
T228	0	11	0	0
T229	0	17	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	8876110	0	0
T1	540	139	0	0
T2	17755	12086	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	4031	0	0
T13	423	22	0	0
T14	5416	2014	0	0
T15	418	17	0	0
T16	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	8878528	0	0
T1	540	140	0	0
T2	17755	12086	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	4031	0	0
T13	423	23	0	0
T14	5416	2014	0	0
T15	418	18	0	0
T16	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	1405	0	0
T2	17755	12	0	0
T3	9207	0	0	0
T6	9065	26	0	0
T8	0	14	0	0
T10	0	8	0	0
T14	5416	12	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	4	0	0
T53	403	0	0	0
T57	0	10	0	0
T82	0	17	0	0
T83	0	12	0	0
T84	0	12	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	1377	0	0
T2	17755	12	0	0
T3	9207	0	0	0
T6	9065	26	0	0
T8	0	14	0	0
T10	0	8	0	0
T14	5416	12	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	4	0	0
T53	403	0	0	0
T57	0	10	0	0
T82	0	17	0	0
T83	0	1	0	0
T84	0	12	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	955	0	0
T2	17755	12	0	0
T3	9207	0	0	0
T6	9065	26	0	0
T8	0	14	0	0
T10	0	8	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	4	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	10	0	0
T82	0	17	0	0
T93	0	15	0	0
T228	0	11	0	0
T229	0	17	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	955	0	0
T2	17755	12	0	0
T3	9207	0	0	0
T6	9065	26	0	0
T8	0	14	0	0
T10	0	8	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	4	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	10	0	0
T82	0	17	0	0
T93	0	15	0	0
T228	0	11	0	0
T229	0	17	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	78850	0	0
T2	17755	2107	0	0
T3	9207	0	0	0
T6	9065	1634	0	0
T8	0	1890	0	0
T10	0	586	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	65	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	650	0	0
T82	0	1300	0	0
T93	0	938	0	0
T228	0	548	0	0
T229	0	6824	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9355557	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9355557	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	827	0	0
T2	17755	7	0	0
T3	9207	0	0	0
T6	9065	25	0	0
T8	0	12	0	0
T10	0	6	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	4	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	8	0	0
T82	0	15	0	0
T93	0	15	0	0
T228	0	10	0	0
T229	0	16	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T2,T3
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T2,T3
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T3,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T2,T3,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T3,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T4,T14,T2
1	1	Covered	T2,T3,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T3,T107,T108
1	0	Covered	T55,T56

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T8
0	1	Covered	T2,T6,T8
1	0	Covered	T55,T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T6,T8
1	-	Covered	T2,T6,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T6
DetectSt	168	Covered	T2,T3,T6
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T2,T6,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T6
DebounceSt->IdleSt	163	Covered	T2,T3,T12
DetectSt->IdleSt	186	Covered	T3,T107,T108
DetectSt->StableSt	191	Covered	T2,T6,T8
IdleSt->DebounceSt	148	Covered	T2,T3,T6
StableSt->IdleSt	206	Covered	T2,T6,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T6
0	1	Covered	T2,T3,T6
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T6
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T56
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T3,T12
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T6
DetectSt	-	-	-	-	1	-	-	Covered	T3,T107,T108
DetectSt	-	-	-	-	0	1	-	Covered	T2,T6,T8
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T6
StableSt	-	-	-	-	-	-	1	Covered	T2,T6,T8
StableSt	-	-	-	-	-	-	0	Covered	T2,T6,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10081786	1074	0	0
CntIncr_A	10081786	54066	0	0
CntNoWrap_A	10081786	9351877	0	0
DetectStDropOut_A	10081786	77	0	0
DetectedOut_A	10081786	14755	0	0
DetectedPulseOut_A	10081786	410	0	0
DisabledIdleSt_A	10081786	8952273	0	0
DisabledNoDetection_A	10081786	8954101	0	0
EnterDebounceSt_A	10081786	584	0	0
EnterDetectSt_A	10081786	493	0	0
EnterStableSt_A	10081786	410	0	0
PulseIsPulse_A	10081786	410	0	0
StayInStableSt	10081786	14337	0	0
gen_high_level_sva.HighLevelEvent_A	10081786	9355557	0	0
gen_not_sticky_sva.StableStDropOut_A	10081786	400	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	1074	0	0
T2	17755	7	0	0
T3	9207	27	0	0
T6	9065	2	0	0
T8	0	4	0	0
T10	0	4	0	0
T11	0	2	0	0
T12	0	4	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	6	0	0
T36	0	12	0	0
T39	0	5	0	0
T53	403	0	0	0
T54	798	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	54066	0	0
T2	17755	270	0	0
T3	9207	2391	0	0
T6	9065	41	0	0
T8	0	142	0	0
T10	0	82	0	0
T11	0	25	0	0
T12	0	65	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	273	0	0
T36	0	246	0	0
T39	0	157	0	0
T53	403	0	0	0
T54	798	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9351877	0	0
T1	540	139	0	0
T2	17755	17315	0	0
T3	9207	8769	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8654	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	77	0	0
T3	9207	13	0	0
T6	9065	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T25	494	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T53	403	0	0	0
T54	798	0	0	0
T88	0	3	0	0
T107	0	6	0	0
T108	0	2	0	0
T109	0	5	0	0
T115	0	4	0	0
T117	0	5	0	0
T119	0	3	0	0
T120	0	3	0	0
T121	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	14755	0	0
T2	17755	175	0	0
T3	9207	0	0	0
T6	9065	85	0	0
T8	0	109	0	0
T10	0	139	0	0
T11	0	4	0	0
T12	0	3	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	213	0	0
T36	0	64	0	0
T39	0	21	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	124	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	410	0	0
T2	17755	3	0	0
T3	9207	0	0	0
T6	9065	1	0	0
T8	0	2	0	0
T10	0	2	0	0
T11	0	1	0	0
T12	0	1	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	3	0	0
T36	0	6	0	0
T39	0	2	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	8952273	0	0
T1	540	139	0	0
T2	17755	15203	0	0
T3	9207	4030	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	6996	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	8954101	0	0
T1	540	140	0	0
T2	17755	15204	0	0
T3	9207	4030	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	6997	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	584	0	0
T2	17755	4	0	0
T3	9207	14	0	0
T6	9065	1	0	0
T8	0	2	0	0
T10	0	2	0	0
T11	0	1	0	0
T12	0	3	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	3	0	0
T36	0	6	0	0
T39	0	3	0	0
T53	403	0	0	0
T54	798	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	493	0	0
T2	17755	3	0	0
T3	9207	13	0	0
T6	9065	1	0	0
T8	0	2	0	0
T10	0	2	0	0
T11	0	1	0	0
T12	0	1	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	3	0	0
T36	0	6	0	0
T39	0	2	0	0
T53	403	0	0	0
T54	798	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	410	0	0
T2	17755	3	0	0
T3	9207	0	0	0
T6	9065	1	0	0
T8	0	2	0	0
T10	0	2	0	0
T11	0	1	0	0
T12	0	1	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	3	0	0
T36	0	6	0	0
T39	0	2	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	410	0	0
T2	17755	3	0	0
T3	9207	0	0	0
T6	9065	1	0	0
T8	0	2	0	0
T10	0	2	0	0
T11	0	1	0	0
T12	0	1	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	3	0	0
T36	0	6	0	0
T39	0	2	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	14337	0	0
T2	17755	172	0	0
T3	9207	0	0	0
T6	9065	84	0	0
T8	0	107	0	0
T10	0	137	0	0
T11	0	3	0	0
T12	0	2	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	210	0	0
T36	0	58	0	0
T39	0	19	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	122	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9355557	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	400	0	0
T2	17755	3	0	0
T3	9207	0	0	0
T6	9065	1	0	0
T8	0	2	0	0
T10	0	2	0	0
T11	0	1	0	0
T12	0	1	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	3	0	0
T36	0	6	0	0
T39	0	2	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T2,T6
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T14,T2,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T14,T2,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T14,T2,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T2,T6
1	0	Covered	T2,T6,T8
1	1	Covered	T14,T2,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T2,T6
0	1	Covered	T14,T2,T83
1	0	Covered	T2,T98,T55

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T10
0	1	Covered	T6,T8,T10
1	0	Covered	T56,T99

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T8,T10
1	-	Covered	T6,T8,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T2,T6
DetectSt	168	Covered	T14,T2,T6
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T6,T8,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T2,T6
DebounceSt->IdleSt	163	Covered	T83,T118,T55
DetectSt->IdleSt	186	Covered	T14,T2,T83
DetectSt->StableSt	191	Covered	T6,T8,T10
IdleSt->DebounceSt	148	Covered	T14,T2,T6
StableSt->IdleSt	206	Covered	T6,T8,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T2,T6
0	1	Covered	T14,T2,T6
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T2,T6
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T14,T2,T6
IdleSt	0	-	-	-	-	-	-	Covered	T14,T2,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T56
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T2,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T83,T118,T55
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T2,T6
DetectSt	-	-	-	-	1	-	-	Covered	T14,T2,T83
DetectSt	-	-	-	-	0	1	-	Covered	T6,T8,T10
DetectSt	-	-	-	-	0	0	-	Covered	T14,T2,T6
StableSt	-	-	-	-	-	-	1	Covered	T6,T8,T10
StableSt	-	-	-	-	-	-	0	Covered	T6,T8,T10
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10081786	3032	0	0
CntIncr_A	10081786	104111	0	0
CntNoWrap_A	10081786	9349919	0	0
DetectStDropOut_A	10081786	338	0	0
DetectedOut_A	10081786	97713	0	0
DetectedPulseOut_A	10081786	1090	0	0
DisabledIdleSt_A	10081786	8861537	0	0
DisabledNoDetection_A	10081786	8863927	0	0
EnterDebounceSt_A	10081786	1532	0	0
EnterDetectSt_A	10081786	1500	0	0
EnterStableSt_A	10081786	1090	0	0
PulseIsPulse_A	10081786	1090	0	0
StayInStableSt	10081786	96498	0	0
gen_high_event_sva.HighLevelEvent_A	10081786	9355557	0	0
gen_high_level_sva.HighLevelEvent_A	10081786	9355557	0	0
gen_not_sticky_sva.StableStDropOut_A	10081786	961	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	3032	0	0
T2	17755	52	0	0
T3	9207	0	0	0
T6	9065	26	0	0
T8	0	18	0	0
T10	0	52	0	0
T14	5416	24	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	16	0	0
T53	403	0	0	0
T57	0	22	0	0
T82	0	30	0	0
T83	0	15	0	0
T84	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	104111	0	0
T2	17755	1509	0	0
T3	9207	0	0	0
T6	9065	520	0	0
T8	0	738	0	0
T10	0	1846	0	0
T14	5416	667	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	352	0	0
T53	403	0	0	0
T57	0	913	0	0
T82	0	1095	0	0
T83	0	686	0	0
T84	0	172	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9349919	0	0
T1	540	139	0	0
T2	17755	17270	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8630	0	0
T13	423	22	0	0
T14	5416	4991	0	0
T15	418	17	0	0
T16	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	338	0	0
T2	17755	20	0	0
T3	9207	0	0	0
T6	9065	0	0	0
T14	5416	12	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T53	403	0	0	0
T83	0	1	0	0
T84	0	4	0	0
T98	0	11	0	0
T110	0	11	0	0
T111	0	27	0	0
T112	0	13	0	0
T114	0	3	0	0
T116	0	11	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	97713	0	0
T6	9065	1424	0	0
T7	810	0	0	0
T8	18502	473	0	0
T10	0	1907	0	0
T16	425	0	0	0
T17	522	0	0	0
T25	494	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	344	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	1234	0	0
T82	0	1030	0	0
T93	0	3174	0	0
T97	0	461	0	0
T228	0	639	0	0
T229	0	11673	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	1090	0	0
T6	9065	13	0	0
T7	810	0	0	0
T8	18502	9	0	0
T10	0	26	0	0
T16	425	0	0	0
T17	522	0	0	0
T25	494	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	8	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	11	0	0
T82	0	15	0	0
T93	0	24	0	0
T97	0	19	0	0
T228	0	15	0	0
T229	0	27	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	8861537	0	0
T1	540	139	0	0
T2	17755	14196	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	4346	0	0
T13	423	22	0	0
T14	5416	2014	0	0
T15	418	17	0	0
T16	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	8863927	0	0
T1	540	140	0	0
T2	17755	14201	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	4346	0	0
T13	423	23	0	0
T14	5416	2014	0	0
T15	418	18	0	0
T16	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	1532	0	0
T2	17755	26	0	0
T3	9207	0	0	0
T6	9065	13	0	0
T8	0	9	0	0
T10	0	26	0	0
T14	5416	12	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	8	0	0
T53	403	0	0	0
T57	0	11	0	0
T82	0	15	0	0
T83	0	14	0	0
T84	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	1500	0	0
T2	17755	26	0	0
T3	9207	0	0	0
T6	9065	13	0	0
T8	0	9	0	0
T10	0	26	0	0
T14	5416	12	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	8	0	0
T53	403	0	0	0
T57	0	11	0	0
T82	0	15	0	0
T83	0	1	0	0
T84	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	1090	0	0
T6	9065	13	0	0
T7	810	0	0	0
T8	18502	9	0	0
T10	0	26	0	0
T16	425	0	0	0
T17	522	0	0	0
T25	494	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	8	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	11	0	0
T82	0	15	0	0
T93	0	24	0	0
T97	0	19	0	0
T228	0	15	0	0
T229	0	27	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	1090	0	0
T6	9065	13	0	0
T7	810	0	0	0
T8	18502	9	0	0
T10	0	26	0	0
T16	425	0	0	0
T17	522	0	0	0
T25	494	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	8	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	11	0	0
T82	0	15	0	0
T93	0	24	0	0
T97	0	19	0	0
T228	0	15	0	0
T229	0	27	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	96498	0	0
T6	9065	1410	0	0
T7	810	0	0	0
T8	18502	463	0	0
T10	0	1879	0	0
T16	425	0	0	0
T17	522	0	0	0
T25	494	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	336	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	1220	0	0
T82	0	1013	0	0
T93	0	3149	0	0
T97	0	442	0	0
T228	0	623	0	0
T229	0	11643	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9355557	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9355557	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	961	0	0
T6	9065	12	0	0
T7	810	0	0	0
T8	18502	8	0	0
T10	0	24	0	0
T16	425	0	0	0
T17	522	0	0	0
T25	494	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	8	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	8	0	0
T82	0	13	0	0
T93	0	23	0	0
T97	0	19	0	0
T228	0	14	0	0
T229	0	24	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T2,T3
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T2,T3
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T6,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T3,T6,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T6,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T8
1	0	Covered	T4,T14,T2
1	1	Covered	T3,T6,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T10
0	1	Covered	T35,T36,T107
1	0	Covered	T55,T56

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T10
0	1	Covered	T3,T6,T10
1	0	Covered	T55,T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T6,T10
1	-	Covered	T3,T6,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T6,T10
DetectSt	168	Covered	T3,T6,T10
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T3,T6,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T6,T10
DebounceSt->IdleSt	163	Covered	T39,T36,T107
DetectSt->IdleSt	186	Covered	T35,T36,T107
DetectSt->StableSt	191	Covered	T3,T6,T10
IdleSt->DebounceSt	148	Covered	T3,T6,T10
StableSt->IdleSt	206	Covered	T3,T6,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T6,T10
0	1	Covered	T3,T6,T10
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T10
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T6,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T56
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T6,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T36,T107
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T6,T10
DetectSt	-	-	-	-	1	-	-	Covered	T35,T36,T107
DetectSt	-	-	-	-	0	1	-	Covered	T3,T6,T10
DetectSt	-	-	-	-	0	0	-	Covered	T3,T6,T10
StableSt	-	-	-	-	-	-	1	Covered	T3,T6,T10
StableSt	-	-	-	-	-	-	0	Covered	T3,T6,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10081786	948	0	0
CntIncr_A	10081786	48554	0	0
CntNoWrap_A	10081786	9352003	0	0
DetectStDropOut_A	10081786	79	0	0
DetectedOut_A	10081786	16020	0	0
DetectedPulseOut_A	10081786	368	0	0
DisabledIdleSt_A	10081786	8937823	0	0
DisabledNoDetection_A	10081786	8939688	0	0
EnterDebounceSt_A	10081786	499	0	0
EnterDetectSt_A	10081786	452	0	0
EnterStableSt_A	10081786	368	0	0
PulseIsPulse_A	10081786	368	0	0
StayInStableSt	10081786	15627	0	0
gen_high_level_sva.HighLevelEvent_A	10081786	9355557	0	0
gen_not_sticky_sva.StableStDropOut_A	10081786	341	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	948	0	0
T3	9207	2	0	0
T6	9065	2	0	0
T10	0	4	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T25	494	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	8	0	0
T35	0	6	0	0
T36	0	27	0	0
T39	0	5	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	4	0	0
T82	0	4	0	0
T107	0	9	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	48554	0	0
T3	9207	105	0	0
T6	9065	73	0	0
T10	0	116	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T25	494	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	332	0	0
T35	0	171	0	0
T36	0	695	0	0
T39	0	263	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	174	0	0
T82	0	118	0	0
T107	0	593	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9352003	0	0
T1	540	139	0	0
T2	17755	17322	0	0
T3	9207	8794	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8654	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	79	0	0
T35	27601	3	0	0
T36	0	13	0	0
T40	856	0	0	0
T71	492	0	0	0
T72	498	0	0	0
T76	502	0	0	0
T77	526	0	0	0
T78	501	0	0	0
T96	0	1	0	0
T107	0	3	0	0
T108	0	6	0	0
T120	0	5	0	0
T207	402	0	0	0
T208	613	0	0	0
T209	422	0	0	0
T230	0	6	0	0
T231	0	6	0	0
T232	0	3	0	0
T233	0	12	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	16020	0	0
T3	9207	72	0	0
T6	9065	52	0	0
T10	0	103	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T25	494	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	319	0	0
T39	0	18	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	101	0	0
T82	0	160	0	0
T93	0	88	0	0
T180	0	8	0	0
T234	0	18	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	368	0	0
T3	9207	1	0	0
T6	9065	1	0	0
T10	0	2	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T25	494	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	4	0	0
T39	0	2	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	2	0	0
T82	0	2	0	0
T93	0	1	0	0
T180	0	2	0	0
T234	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	8937823	0	0
T1	540	139	0	0
T2	17755	17322	0	0
T3	9207	4030	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	7233	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	8939688	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	4030	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	7234	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	499	0	0
T3	9207	1	0	0
T6	9065	1	0	0
T10	0	2	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T25	494	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	4	0	0
T35	0	3	0	0
T36	0	14	0	0
T39	0	3	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	2	0	0
T82	0	2	0	0
T107	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	452	0	0
T3	9207	1	0	0
T6	9065	1	0	0
T10	0	2	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T25	494	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	4	0	0
T35	0	3	0	0
T36	0	13	0	0
T39	0	2	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	2	0	0
T82	0	2	0	0
T107	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	368	0	0
T3	9207	1	0	0
T6	9065	1	0	0
T10	0	2	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T25	494	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	4	0	0
T39	0	2	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	2	0	0
T82	0	2	0	0
T93	0	1	0	0
T180	0	2	0	0
T234	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	368	0	0
T3	9207	1	0	0
T6	9065	1	0	0
T10	0	2	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T25	494	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	4	0	0
T39	0	2	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	2	0	0
T82	0	2	0	0
T93	0	1	0	0
T180	0	2	0	0
T234	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	15627	0	0
T3	9207	71	0	0
T6	9065	51	0	0
T10	0	101	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T25	494	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	315	0	0
T39	0	16	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	99	0	0
T82	0	158	0	0
T93	0	87	0	0
T180	0	6	0	0
T234	0	14	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9355557	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	341	0	0
T3	9207	1	0	0
T6	9065	1	0	0
T10	0	2	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T25	494	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	4	0	0
T39	0	2	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	2	0	0
T82	0	2	0	0
T93	0	1	0	0
T180	0	2	0	0
T234	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T2,T6
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T14,T2,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T14,T2,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T14,T2,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T2,T6
1	0	Covered	T2,T6,T8
1	1	Covered	T14,T2,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T2,T6
0	1	Covered	T14,T2,T83
1	0	Covered	T2,T98,T235

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T10
0	1	Covered	T6,T8,T10
1	0	Covered	T55,T236

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T8,T10
1	-	Covered	T6,T8,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T2,T6
DetectSt	168	Covered	T14,T2,T6
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T6,T8,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T2,T6
DebounceSt->IdleSt	163	Covered	T83,T118,T55
DetectSt->IdleSt	186	Covered	T14,T2,T83
DetectSt->StableSt	191	Covered	T6,T8,T10
IdleSt->DebounceSt	148	Covered	T14,T2,T6
StableSt->IdleSt	206	Covered	T6,T8,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T2,T6
0	1	Covered	T14,T2,T6
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T2,T6
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T14,T2,T6
IdleSt	0	-	-	-	-	-	-	Covered	T14,T2,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T56
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T2,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T83,T118,T55
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T2,T6
DetectSt	-	-	-	-	1	-	-	Covered	T14,T2,T83
DetectSt	-	-	-	-	0	1	-	Covered	T6,T8,T10
DetectSt	-	-	-	-	0	0	-	Covered	T14,T2,T6
StableSt	-	-	-	-	-	-	1	Covered	T6,T8,T10
StableSt	-	-	-	-	-	-	0	Covered	T6,T8,T10
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10081786	3071	0	0
CntIncr_A	10081786	106037	0	0
CntNoWrap_A	10081786	9349880	0	0
DetectStDropOut_A	10081786	384	0	0
DetectedOut_A	10081786	88961	0	0
DetectedPulseOut_A	10081786	947	0	0
DisabledIdleSt_A	10081786	8868070	0	0
DisabledNoDetection_A	10081786	8870474	0	0
EnterDebounceSt_A	10081786	1550	0	0
EnterDetectSt_A	10081786	1521	0	0
EnterStableSt_A	10081786	947	0	0
PulseIsPulse_A	10081786	947	0	0
StayInStableSt	10081786	87903	0	0
gen_high_event_sva.HighLevelEvent_A	10081786	9355557	0	0
gen_high_level_sva.HighLevelEvent_A	10081786	9355557	0	0
gen_not_sticky_sva.StableStDropOut_A	10081786	821	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	3071	0	0
T2	17755	8	0	0
T3	9207	0	0	0
T6	9065	4	0	0
T8	0	18	0	0
T10	0	24	0	0
T14	5416	56	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	44	0	0
T53	403	0	0	0
T57	0	4	0	0
T82	0	30	0	0
T83	0	13	0	0
T84	0	42	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	106037	0	0
T2	17755	229	0	0
T3	9207	0	0	0
T6	9065	74	0	0
T8	0	756	0	0
T10	0	612	0	0
T14	5416	1569	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	1056	0	0
T53	403	0	0	0
T57	0	170	0	0
T82	0	1245	0	0
T83	0	588	0	0
T84	0	927	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9349880	0	0
T1	540	139	0	0
T2	17755	17314	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8652	0	0
T13	423	22	0	0
T14	5416	4959	0	0
T15	418	17	0	0
T16	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	384	0	0
T2	17755	3	0	0
T3	9207	0	0	0
T6	9065	0	0	0
T14	5416	28	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T53	403	0	0	0
T83	0	1	0	0
T84	0	21	0	0
T98	0	7	0	0
T110	0	24	0	0
T111	0	8	0	0
T112	0	23	0	0
T235	0	1	0	0
T237	0	7	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	88961	0	0
T6	9065	46	0	0
T7	810	0	0	0
T8	18502	455	0	0
T10	0	950	0	0
T16	425	0	0	0
T17	522	0	0	0
T25	494	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	755	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	64	0	0
T82	0	880	0	0
T93	0	553	0	0
T97	0	824	0	0
T228	0	2102	0	0
T229	0	10007	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	947	0	0
T6	9065	2	0	0
T7	810	0	0	0
T8	18502	9	0	0
T10	0	12	0	0
T16	425	0	0	0
T17	522	0	0	0
T25	494	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	22	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	2	0	0
T82	0	15	0	0
T93	0	14	0	0
T97	0	25	0	0
T228	0	27	0	0
T229	0	27	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	8868070	0	0
T1	540	139	0	0
T2	17755	14196	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	5540	0	0
T13	423	22	0	0
T14	5416	2014	0	0
T15	418	17	0	0
T16	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	8870474	0	0
T1	540	140	0	0
T2	17755	14201	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	5541	0	0
T13	423	23	0	0
T14	5416	2014	0	0
T15	418	18	0	0
T16	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	1550	0	0
T2	17755	4	0	0
T3	9207	0	0	0
T6	9065	2	0	0
T8	0	9	0	0
T10	0	12	0	0
T14	5416	28	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	22	0	0
T53	403	0	0	0
T57	0	2	0	0
T82	0	15	0	0
T83	0	12	0	0
T84	0	21	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	1521	0	0
T2	17755	4	0	0
T3	9207	0	0	0
T6	9065	2	0	0
T8	0	9	0	0
T10	0	12	0	0
T14	5416	28	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	22	0	0
T53	403	0	0	0
T57	0	2	0	0
T82	0	15	0	0
T83	0	1	0	0
T84	0	21	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	947	0	0
T6	9065	2	0	0
T7	810	0	0	0
T8	18502	9	0	0
T10	0	12	0	0
T16	425	0	0	0
T17	522	0	0	0
T25	494	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	22	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	2	0	0
T82	0	15	0	0
T93	0	14	0	0
T97	0	25	0	0
T228	0	27	0	0
T229	0	27	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	947	0	0
T6	9065	2	0	0
T7	810	0	0	0
T8	18502	9	0	0
T10	0	12	0	0
T16	425	0	0	0
T17	522	0	0	0
T25	494	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	22	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	2	0	0
T82	0	15	0	0
T93	0	14	0	0
T97	0	25	0	0
T228	0	27	0	0
T229	0	27	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	87903	0	0
T6	9065	44	0	0
T7	810	0	0	0
T8	18502	445	0	0
T10	0	937	0	0
T16	425	0	0	0
T17	522	0	0	0
T25	494	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	732	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	62	0	0
T82	0	863	0	0
T93	0	539	0	0
T97	0	799	0	0
T228	0	2072	0	0
T229	0	9978	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9355557	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9355557	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	821	0	0
T6	9065	2	0	0
T7	810	0	0	0
T8	18502	8	0	0
T10	0	11	0	0
T16	425	0	0	0
T17	522	0	0	0
T25	494	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	21	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	2	0	0
T82	0	13	0	0
T93	0	14	0	0
T97	0	25	0	0
T228	0	24	0	0
T229	0	25	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T2,T3
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T2,T3
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T34,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T3,T34,T35

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T34,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T8
1	0	Covered	T4,T14,T2
1	1	Covered	T3,T34,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T34,T35
0	1	Covered	T238,T239,T240
1	0	Covered	T55

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T34,T35
0	1	Covered	T3,T34,T35
1	0	Covered	T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T34,T35
1	-	Covered	T3,T34,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T34,T35
DetectSt	168	Covered	T3,T34,T35
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T3,T34,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T34,T35
DebounceSt->IdleSt	163	Covered	T3,T34,T107
DetectSt->IdleSt	186	Covered	T238,T239,T240
DetectSt->StableSt	191	Covered	T3,T34,T35
IdleSt->DebounceSt	148	Covered	T3,T34,T35
StableSt->IdleSt	206	Covered	T3,T34,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T34,T35
0	1	Covered	T3,T34,T35
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T34,T35
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T34,T35
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T56
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T34,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T34,T107
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T34,T35
DetectSt	-	-	-	-	1	-	-	Covered	T238,T239,T240
DetectSt	-	-	-	-	0	1	-	Covered	T3,T34,T35
DetectSt	-	-	-	-	0	0	-	Covered	T3,T34,T35
StableSt	-	-	-	-	-	-	1	Covered	T3,T34,T35
StableSt	-	-	-	-	-	-	0	Covered	T3,T34,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10081786	1020	0	0
CntIncr_A	10081786	52496	0	0
CntNoWrap_A	10081786	9351931	0	0
DetectStDropOut_A	10081786	99	0	0
DetectedOut_A	10081786	19983	0	0
DetectedPulseOut_A	10081786	384	0	0
DisabledIdleSt_A	10081786	8938464	0	0
DisabledNoDetection_A	10081786	8940328	0	0
EnterDebounceSt_A	10081786	538	0	0
EnterDetectSt_A	10081786	484	0	0
EnterStableSt_A	10081786	384	0	0
PulseIsPulse_A	10081786	384	0	0
StayInStableSt	10081786	19571	0	0
gen_high_level_sva.HighLevelEvent_A	10081786	9355557	0	0
gen_not_sticky_sva.StableStDropOut_A	10081786	355	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	1020	0	0
T3	9207	25	0	0
T6	9065	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T25	494	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	13	0	0
T35	0	20	0	0
T36	0	10	0	0
T37	0	2	0	0
T39	0	2	0	0
T53	403	0	0	0
T54	798	0	0	0
T82	0	2	0	0
T97	0	3	0	0
T107	0	5	0	0
T228	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	52496	0	0
T3	9207	1211	0	0
T6	9065	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T25	494	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	1003	0	0
T35	0	530	0	0
T36	0	205	0	0
T37	0	65	0	0
T39	0	120	0	0
T53	403	0	0	0
T54	798	0	0	0
T82	0	86	0	0
T97	0	56	0	0
T107	0	236	0	0
T228	0	111	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9351931	0	0
T1	540	139	0	0
T2	17755	17322	0	0
T3	9207	8771	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	99	0	0
T44	652	0	0	0
T51	9387	0	0	0
T52	777	0	0	0
T124	0	3	0	0
T186	13430	0	0	0
T187	675	0	0	0
T232	0	10	0	0
T238	21638	9	0	0
T239	0	1	0	0
T240	0	9	0	0
T241	0	6	0	0
T242	0	9	0	0
T243	0	5	0	0
T244	0	1	0	0
T245	0	2	0	0
T246	416	0	0	0
T247	522	0	0	0
T248	402	0	0	0
T249	495	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	19983	0	0
T3	9207	998	0	0
T6	9065	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T25	494	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	32	0	0
T35	0	53	0	0
T36	0	51	0	0
T37	0	59	0	0
T39	0	9	0	0
T53	403	0	0	0
T54	798	0	0	0
T82	0	53	0	0
T97	0	54	0	0
T107	0	94	0	0
T228	0	224	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	384	0	0
T3	9207	12	0	0
T6	9065	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T25	494	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	6	0	0
T35	0	10	0	0
T36	0	5	0	0
T37	0	1	0	0
T39	0	1	0	0
T53	403	0	0	0
T54	798	0	0	0
T82	0	1	0	0
T97	0	1	0	0
T107	0	2	0	0
T228	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	8938464	0	0
T1	540	139	0	0
T2	17755	17322	0	0
T3	9207	4030	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8610	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	8940328	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	4030	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8612	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	538	0	0
T3	9207	13	0	0
T6	9065	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T25	494	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	7	0	0
T35	0	10	0	0
T36	0	5	0	0
T37	0	1	0	0
T39	0	1	0	0
T53	403	0	0	0
T54	798	0	0	0
T82	0	1	0	0
T97	0	2	0	0
T107	0	3	0	0
T228	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	484	0	0
T3	9207	12	0	0
T6	9065	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T25	494	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	6	0	0
T35	0	10	0	0
T36	0	5	0	0
T37	0	1	0	0
T39	0	1	0	0
T53	403	0	0	0
T54	798	0	0	0
T82	0	1	0	0
T97	0	1	0	0
T107	0	2	0	0
T228	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	384	0	0
T3	9207	12	0	0
T6	9065	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T25	494	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	6	0	0
T35	0	10	0	0
T36	0	5	0	0
T37	0	1	0	0
T39	0	1	0	0
T53	403	0	0	0
T54	798	0	0	0
T82	0	1	0	0
T97	0	1	0	0
T107	0	2	0	0
T228	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	384	0	0
T3	9207	12	0	0
T6	9065	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T25	494	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	6	0	0
T35	0	10	0	0
T36	0	5	0	0
T37	0	1	0	0
T39	0	1	0	0
T53	403	0	0	0
T54	798	0	0	0
T82	0	1	0	0
T97	0	1	0	0
T107	0	2	0	0
T228	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	19571	0	0
T3	9207	986	0	0
T6	9065	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T25	494	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	26	0	0
T35	0	43	0	0
T36	0	46	0	0
T37	0	58	0	0
T39	0	8	0	0
T53	403	0	0	0
T54	798	0	0	0
T82	0	52	0	0
T97	0	53	0	0
T107	0	92	0	0
T228	0	221	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9355557	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	355	0	0
T3	9207	12	0	0
T6	9065	0	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T25	494	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	6	0	0
T35	0	10	0	0
T36	0	5	0	0
T37	0	1	0	0
T39	0	1	0	0
T53	403	0	0	0
T54	798	0	0	0
T82	0	1	0	0
T97	0	1	0	0
T107	0	2	0	0
T228	0	3	0	0