Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T2,T6
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T14,T2,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T14,T2,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T14,T2,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T2,T6
1	0	Covered	T2,T6,T8
1	1	Covered	T14,T2,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T2,T6
0	1	Covered	T14,T83,T84
1	0	Covered	T97,T235,T237

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T8
0	1	Covered	T6,T8,T10
1	0	Covered	T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T6,T8
1	-	Covered	T6,T8,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T2,T6
DetectSt	168	Covered	T14,T2,T6
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T2,T6,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T2,T6
DebounceSt->IdleSt	163	Covered	T83,T118,T55
DetectSt->IdleSt	186	Covered	T14,T83,T84
DetectSt->StableSt	191	Covered	T2,T6,T8
IdleSt->DebounceSt	148	Covered	T14,T2,T6
StableSt->IdleSt	206	Covered	T2,T6,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T2,T6
0	1	Covered	T14,T2,T6
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T2,T6
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T14,T2,T6
IdleSt	0	-	-	-	-	-	-	Covered	T14,T2,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T56
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T2,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T83,T118,T55
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T2,T6
DetectSt	-	-	-	-	1	-	-	Covered	T14,T83,T84
DetectSt	-	-	-	-	0	1	-	Covered	T2,T6,T8
DetectSt	-	-	-	-	0	0	-	Covered	T14,T2,T6
StableSt	-	-	-	-	-	-	1	Covered	T6,T8,T10
StableSt	-	-	-	-	-	-	0	Covered	T2,T6,T8
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10081786	2880	0	0
CntIncr_A	10081786	99728	0	0
CntNoWrap_A	10081786	9350071	0	0
DetectStDropOut_A	10081786	316	0	0
DetectedOut_A	10081786	88809	0	0
DetectedPulseOut_A	10081786	981	0	0
DisabledIdleSt_A	10081786	8867730	0	0
DisabledNoDetection_A	10081786	8870134	0	0
EnterDebounceSt_A	10081786	1453	0	0
EnterDetectSt_A	10081786	1427	0	0
EnterStableSt_A	10081786	981	0	0
PulseIsPulse_A	10081786	981	0	0
StayInStableSt	10081786	87717	0	0
gen_high_event_sva.HighLevelEvent_A	10081786	9355557	0	0
gen_high_level_sva.HighLevelEvent_A	10081786	9355557	0	0
gen_not_sticky_sva.StableStDropOut_A	10081786	869	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	2880	0	0
T2	17755	10	0	0
T3	9207	0	0	0
T6	9065	32	0	0
T8	0	48	0	0
T10	0	20	0	0
T14	5416	24	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	48	0	0
T53	403	0	0	0
T57	0	14	0	0
T82	0	58	0	0
T83	0	13	0	0
T84	0	24	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	99728	0	0
T2	17755	290	0	0
T3	9207	0	0	0
T6	9065	832	0	0
T8	0	2040	0	0
T10	0	540	0	0
T14	5416	667	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	1296	0	0
T53	403	0	0	0
T57	0	532	0	0
T82	0	2001	0	0
T83	0	588	0	0
T84	0	522	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9350071	0	0
T1	540	139	0	0
T2	17755	17312	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8624	0	0
T13	423	22	0	0
T14	5416	4991	0	0
T15	418	17	0	0
T16	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	316	0	0
T2	17755	0	0	0
T3	9207	0	0	0
T6	9065	0	0	0
T14	5416	12	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T53	403	0	0	0
T83	0	1	0	0
T84	0	12	0	0
T97	0	3	0	0
T110	0	11	0	0
T111	0	18	0	0
T112	0	13	0	0
T114	0	7	0	0
T116	0	24	0	0
T118	0	20	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	88809	0	0
T2	17755	834	0	0
T3	9207	0	0	0
T6	9065	776	0	0
T8	0	1369	0	0
T10	0	608	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	2073	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	1268	0	0
T82	0	3121	0	0
T93	0	374	0	0
T228	0	609	0	0
T229	0	3019	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	981	0	0
T2	17755	5	0	0
T3	9207	0	0	0
T6	9065	16	0	0
T8	0	24	0	0
T10	0	10	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	24	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	7	0	0
T82	0	29	0	0
T93	0	7	0	0
T228	0	15	0	0
T229	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	8867730	0	0
T1	540	139	0	0
T2	17755	13371	0	0
T3	9207	8796	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	4851	0	0
T13	423	22	0	0
T14	5416	2014	0	0
T15	418	17	0	0
T16	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	8870134	0	0
T1	540	140	0	0
T2	17755	13371	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	4852	0	0
T13	423	23	0	0
T14	5416	2014	0	0
T15	418	18	0	0
T16	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	1453	0	0
T2	17755	5	0	0
T3	9207	0	0	0
T6	9065	16	0	0
T8	0	24	0	0
T10	0	10	0	0
T14	5416	12	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	24	0	0
T53	403	0	0	0
T57	0	7	0	0
T82	0	29	0	0
T83	0	12	0	0
T84	0	12	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	1427	0	0
T2	17755	5	0	0
T3	9207	0	0	0
T6	9065	16	0	0
T8	0	24	0	0
T10	0	10	0	0
T14	5416	12	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	24	0	0
T53	403	0	0	0
T57	0	7	0	0
T82	0	29	0	0
T83	0	1	0	0
T84	0	12	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	981	0	0
T2	17755	5	0	0
T3	9207	0	0	0
T6	9065	16	0	0
T8	0	24	0	0
T10	0	10	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	24	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	7	0	0
T82	0	29	0	0
T93	0	7	0	0
T228	0	15	0	0
T229	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	981	0	0
T2	17755	5	0	0
T3	9207	0	0	0
T6	9065	16	0	0
T8	0	24	0	0
T10	0	10	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	24	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	7	0	0
T82	0	29	0	0
T93	0	7	0	0
T228	0	15	0	0
T229	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	87717	0	0
T2	17755	824	0	0
T3	9207	0	0	0
T6	9065	760	0	0
T8	0	1343	0	0
T10	0	597	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	2046	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	1261	0	0
T82	0	3089	0	0
T93	0	367	0	0
T228	0	593	0	0
T229	0	3009	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9355557	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9355557	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	869	0	0
T6	9065	16	0	0
T7	810	0	0	0
T8	18502	22	0	0
T10	0	9	0	0
T16	425	0	0	0
T17	522	0	0	0
T25	494	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T37	0	21	0	0
T53	403	0	0	0
T54	798	0	0	0
T57	0	7	0	0
T82	0	26	0	0
T93	0	7	0	0
T228	0	14	0	0
T229	0	8	0	0
T250	0	29	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T2,T3
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T2,T3
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T3,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T2,T3,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T3,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T4,T14,T2
1	1	Covered	T2,T3,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T8
0	1	Covered	T239,T251,T243
1	0	Covered	T55,T56

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T8
0	1	Covered	T3,T8,T34
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T8
1	-	Covered	T3,T8,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T8
DetectSt	168	Covered	T2,T3,T8
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T2,T3,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T8
DebounceSt->IdleSt	163	Covered	T3,T39,T107
DetectSt->IdleSt	186	Covered	T239,T251,T243
DetectSt->StableSt	191	Covered	T2,T3,T8
IdleSt->DebounceSt	148	Covered	T2,T3,T8
StableSt->IdleSt	206	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T8
0	1	Covered	T2,T3,T8
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T8
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T56
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T39,T107
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T8
DetectSt	-	-	-	-	1	-	-	Covered	T239,T251,T243
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T8
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T8
StableSt	-	-	-	-	-	-	1	Covered	T3,T8,T34
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10081786	842	0	0
CntIncr_A	10081786	45128	0	0
CntNoWrap_A	10081786	9352109	0	0
DetectStDropOut_A	10081786	51	0	0
DetectedOut_A	10081786	14306	0	0
DetectedPulseOut_A	10081786	341	0	0
DisabledIdleSt_A	10081786	8943556	0	0
DisabledNoDetection_A	10081786	8945427	0	0
EnterDebounceSt_A	10081786	448	0	0
EnterDetectSt_A	10081786	395	0	0
EnterStableSt_A	10081786	341	0	0
PulseIsPulse_A	10081786	341	0	0
StayInStableSt	10081786	13929	0	0
gen_high_level_sva.HighLevelEvent_A	10081786	9355557	0	0
gen_not_sticky_sva.StableStDropOut_A	10081786	304	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	842	0	0
T2	17755	10	0	0
T3	9207	21	0	0
T6	9065	0	0	0
T8	0	4	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	2	0	0
T35	0	4	0	0
T36	0	4	0	0
T37	0	6	0	0
T39	0	5	0	0
T53	403	0	0	0
T54	798	0	0	0
T82	0	4	0	0
T107	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	45128	0	0
T2	17755	380	0	0
T3	9207	1401	0	0
T6	9065	0	0	0
T8	0	158	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	98	0	0
T35	0	106	0	0
T36	0	66	0	0
T37	0	156	0	0
T39	0	245	0	0
T53	403	0	0	0
T54	798	0	0	0
T82	0	146	0	0
T107	0	513	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9352109	0	0
T1	540	139	0	0
T2	17755	17312	0	0
T3	9207	8775	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	8656	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	51	0	0
T96	0	7	0	0
T121	0	1	0	0
T232	0	5	0	0
T239	15834	2	0	0
T243	0	6	0	0
T244	0	1	0	0
T250	12776	0	0	0
T251	0	5	0	0
T252	0	6	0	0
T253	0	1	0	0
T254	0	1	0	0
T255	505	0	0	0
T256	431	0	0	0
T257	491	0	0	0
T258	422	0	0	0
T259	492	0	0	0
T260	504	0	0	0
T261	423	0	0	0
T262	437	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	14306	0	0
T2	17755	287	0	0
T3	9207	449	0	0
T6	9065	0	0	0
T8	0	94	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	64	0	0
T35	0	8	0	0
T36	0	36	0	0
T37	0	213	0	0
T39	0	36	0	0
T53	403	0	0	0
T54	798	0	0	0
T82	0	129	0	0
T107	0	14	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	341	0	0
T2	17755	5	0	0
T3	9207	10	0	0
T6	9065	0	0	0
T8	0	2	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	1	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	0	3	0	0
T39	0	2	0	0
T53	403	0	0	0
T54	798	0	0	0
T82	0	2	0	0
T107	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	8943556	0	0
T1	540	139	0	0
T2	17755	16493	0	0
T3	9207	4030	0	0
T4	2426	422	0	0
T5	405	4	0	0
T6	9065	7880	0	0
T13	423	22	0	0
T14	5416	5015	0	0
T15	418	17	0	0
T16	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	8945427	0	0
T1	540	140	0	0
T2	17755	16494	0	0
T3	9207	4030	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	7882	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	448	0	0
T2	17755	5	0	0
T3	9207	11	0	0
T6	9065	0	0	0
T8	0	2	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	1	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	0	3	0	0
T39	0	3	0	0
T53	403	0	0	0
T54	798	0	0	0
T82	0	2	0	0
T107	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	395	0	0
T2	17755	5	0	0
T3	9207	10	0	0
T6	9065	0	0	0
T8	0	2	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	1	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	0	3	0	0
T39	0	2	0	0
T53	403	0	0	0
T54	798	0	0	0
T82	0	2	0	0
T107	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	341	0	0
T2	17755	5	0	0
T3	9207	10	0	0
T6	9065	0	0	0
T8	0	2	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	1	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	0	3	0	0
T39	0	2	0	0
T53	403	0	0	0
T54	798	0	0	0
T82	0	2	0	0
T107	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	341	0	0
T2	17755	5	0	0
T3	9207	10	0	0
T6	9065	0	0	0
T8	0	2	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	1	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	0	3	0	0
T39	0	2	0	0
T53	403	0	0	0
T54	798	0	0	0
T82	0	2	0	0
T107	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	13929	0	0
T2	17755	277	0	0
T3	9207	439	0	0
T6	9065	0	0	0
T8	0	92	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	63	0	0
T35	0	6	0	0
T36	0	34	0	0
T37	0	210	0	0
T39	0	34	0	0
T53	403	0	0	0
T54	798	0	0	0
T82	0	125	0	0
T107	0	11	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	9355557	0	0
T1	540	140	0	0
T2	17755	17328	0	0
T3	9207	8798	0	0
T4	2426	426	0	0
T5	405	5	0	0
T6	9065	8658	0	0
T13	423	23	0	0
T14	5416	5016	0	0
T15	418	18	0	0
T16	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10081786	304	0	0
T3	9207	10	0	0
T6	9065	0	0	0
T8	0	2	0	0
T15	418	0	0	0
T16	425	0	0	0
T17	522	0	0	0
T25	494	0	0	0
T27	20242	0	0	0
T28	676	0	0	0
T34	0	1	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	0	3	0	0
T39	0	2	0	0
T53	403	0	0	0
T54	798	0	0	0
T107	0	3	0	0
T180	0	3	0	0
T228	0	1	0	0